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REJ09B0403-0200
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16
H8S/2472, H8S/2463, H8S/2462 Group
Hardware Manual
Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2400 Series H8S/2472 H8S/2463 H8S/2462 R4F2472 R4F2463 R4F2462
Rev.2.00 Revision Date: Aug. 20, 2008
Rev. 2.00 Aug. 20, 2008 Page ii of xlviii
Notes regarding these materials
1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products. 7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above. 8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries.
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General Precautions on Handling of Product
1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed. 2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level. Generally, the input pins of CMOS products are high-impedance input pins. If unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a passthrough current flows internally, and a malfunction may occur. 3. Processing before Initialization Note: When power is first supplied, the product's state is undefined. The states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin. During the period where the states are undefined, the register settings and the output state of each pin are also undefined. Design your system so that it does not malfunction because of processing while it is in this undefined state. For those products which have a reset function, reset the LSI immediately after the power supply has been turned on. 4. Prohibition of Access to Undefined or Reserved Addresses Note: Access to undefined or reserved addresses is prohibited. The undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these addresses. Do not access these registers; the system's operation is not guaranteed if they are accessed.
Rev. 2.00 Aug. 20, 2008 Page iv of xlviii
Configuration of This Manual
This manual comprises the following items: 1. General Precautions on Handling of Product 2. Configuration of This Manual 3. Preface 4. Contents 5. Overview 6. Description of Functional Modules * CPU and System-Control Modules * On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module. However, the generic style includes the following items: i) Feature ii) Input/Output Pin iii) Register Description iv) Operation v) Usage Note When designing an application system that includes this LSI, take notes into account. Each section includes notes in relation to the descriptions given, and usage notes are given, as required, as the final part of each section. 7. List of Registers 8. Electrical Characteristics 9. Appendix 10. Main Revisions and Additions in this Edition (only for revised versions) The list of revisions is a summary of points that have been revised or added to earlier versions. This does not include all of the revised contents. For details, see the actual locations in this manual. 11. Index
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Preface
The H8S/2472 Group, H8S/2463 Group, and H8S/2462 Group products are single-chip microcomputers made up of the high-speed H8S/2600 CPU employing Renesas Technology original architecture as its core, and the peripheral functions required to configure a system. The H8S/2600 CPU has an instruction set that is compatible with the H8/300 and H8/300H CPUs. Target Users: This manual was written for users who will be using the H8S/2472 Group, H8S/2463 Group, and H8S/2462 Group in the design of application systems. Target users are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers. Objective: This manual was written to explain the hardware functions and electrical characteristics of the H8S/2472 Group, H8S/2463 Group, and H8S/2462 Group to the target users. Refer to the H8S/2600 Series, H8S/2000 Series Software Manual for a detailed description of the instruction set.
Notes on reading this manual: * In order to understand the overall functions of the chip Read the manual according to the contents. This manual can be roughly categorized into parts on the CPU, system control functions, peripheral functions and electrical characteristics. * In order to understand the details of the CPU's functions Read the H8S/2600 Series, H8S/2000 Series Software Manual. * In order to understand the details of a register when its name is known Read the index that is the final part of the manual to find the page number of the entry on the register. The addresses, bits, and initial values of the registers are summarized in section 29, List of Registers. Examples: Register name: The following notation is used for cases when the same or a similar function, e.g. 16-bit timer pulse unit or serial communication, is implemented on more than one channel: XXX_N (XXX is the register name and N is the channel number) The MSB is on the left and the LSB is on the right.
Bit order:
Rev. 2.00 Aug. 20, 2008 Page vi of xlviii
Related Manuals:
The latest versions of all related manuals are available from our web site. Please ensure you have the latest versions of all documents you require. http://www.renesas.com/
H8S/2472 Group, H8S/2463 Group, and H8S/2462 Group manuals:
Document Title Document No.
H8S/2472 Group, H8S/2463 Group, and H8S/2462 Group Hardware Manual This manual H8S/2600 Series, H8S/2000 Series Software Manual REJ09B0139
User's manuals for development tools:
Document Title Document No.
H8S, H8/300 Series C/C++ Compiler, Assembler, Optimizing Linkage Editor REJ10B0058 User's Manual Microcomputer Development Environment System H8S, H8/300 Series Simulator/Debugger User's Manual H8S, H8/300 Series High-performance Embedded Workshop 3 Tutorial H8S, H8/300 Series High-performance Embedded Workshop 3 User's Manual ADE-702-282 REJ10B0024 REJ10B0026
All trademarks and registered trademarks are the property of their respective owners.
Rev. 2.00 Aug. 20, 2008 Page vii of xlviii
Rev. 2.00 Aug. 20, 2008 Page viii of xlviii
Contents
Section 1 Overview................................................................................................1
1.1 1.2 1.3 Overview................................................................................................................................ 1 Block Diagram ....................................................................................................................... 3 Pin Description....................................................................................................................... 4 1.3.1 Pin Assignments ....................................................................................................... 4 1.3.2 Pin Assignment in Each Operating Mode................................................................. 7 1.3.3 Pin Functions .......................................................................................................... 14
Section 2 CPU......................................................................................................25
2.1 Features................................................................................................................................ 25 2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU ..................................... 26 2.1.2 Differences from H8/300 CPU ............................................................................... 27 2.1.3 Differences from H8/300H CPU............................................................................. 27 CPU Operating Modes ......................................................................................................... 28 2.2.1 Normal Mode.......................................................................................................... 28 2.2.2 Advanced Mode...................................................................................................... 30 Address Space...................................................................................................................... 32 Registers............................................................................................................................... 33 2.4.1 General Registers .................................................................................................... 34 2.4.2 Program Counter (PC) ............................................................................................ 35 2.4.3 Extended Control Register (EXR) .......................................................................... 35 2.4.4 Condition-Code Register (CCR) ............................................................................. 36 2.4.5 Multiply-Accumulate Register (MAC) ................................................................... 37 2.4.6 Initial Values of CPU Registers .............................................................................. 37 Data Formats........................................................................................................................ 38 2.5.1 General Register Data Formats ............................................................................... 38 2.5.2 Memory Data Formats ............................................................................................ 40 Instruction Set ...................................................................................................................... 41 2.6.1 Table of Instructions Classified by Function .......................................................... 42 2.6.2 Basic Instruction Formats ....................................................................................... 52 Addressing Modes and Effective Address Calculation ........................................................ 53 2.7.1 Register DirectRn................................................................................................ 53 2.7.2 Register Indirect@ERn ....................................................................................... 53 2.7.3 Register Indirect with Displacement@(d:16, ERn) or @(d:32, ERn)................. 54 2.7.4 Register Indirect with Post-Increment or Pre-Decrement@ERn+ or @-ERn ..... 54 2.7.5 Absolute Address@aa:8, @aa:16, @aa:24, or @aa:32....................................... 54
2.2
2.3 2.4
2.5
2.6
2.7
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2.8 2.9
2.7.6 Immediate#xx:8, #xx:16, or #xx:32.................................................................... 55 2.7.7 Program-Counter Relative@(d:8, PC) or @(d:16, PC)....................................... 55 2.7.8 Memory Indirect@@aa:8 ................................................................................... 56 2.7.9 Effective Address Calculation ................................................................................ 57 Processing States.................................................................................................................. 59 Usage Note........................................................................................................................... 61 2.9.1 Notes on Using the Bit Operation Instruction......................................................... 61
Section 3 MCU Operating Modes .......................................................................63
3.1 3.2 Operating Mode Selection ................................................................................................... 63 Register Descriptions ........................................................................................................... 64 3.2.1 Mode Control Register (MDCR) ............................................................................ 64 3.2.2 System Control Register (SYSCR) ......................................................................... 65 3.2.3 Serial Timer Control Register (STCR) ................................................................... 66 Operating Mode Descriptions .............................................................................................. 68 3.3.1 Mode 2.................................................................................................................... 68 Address Map ........................................................................................................................ 69
3.3 3.4
Section 4 Exception Handling .............................................................................71
4.1 4.2 4.3 Exception Handling Types and Priority............................................................................... 71 Exception Sources and Exception Vector Table.................................................................. 72 Reset .................................................................................................................................... 74 4.3.1 Reset Exception Handling ...................................................................................... 74 4.3.2 Interrupts after Reset............................................................................................... 75 4.3.3 On-Chip Peripheral Modules after Reset is Cancelled............................................ 75 Interrupt Exception Handling............................................................................................... 76 Trap Instruction Exception Handling................................................................................... 76 Stack Status after Exception Handling................................................................................. 77 Usage Note........................................................................................................................... 78
4.4 4.5 4.6 4.7
Section 5 Interrupt Controller..............................................................................79
5.1 5.2 5.3 Features................................................................................................................................ 79 Input/Output Pins................................................................................................................. 80 Register Descriptions ........................................................................................................... 81 5.3.1 Interrupt Control Registers A to D (ICRA to ICRD) .............................................. 81 5.3.2 Address Break Control Register (ABRKCR) ......................................................... 82 5.3.3 Break Address Registers A to C (BARA to BARC)............................................... 83 5.3.4 IRQ Sense Control Registers (ISCR16H, ISCR16L, ISCRH, ISCRL)................... 84 5.3.5 IRQ Enable Registers (IER16, IER) ....................................................................... 86 5.3.6 IRQ Status Registers (ISR16, ISR) ......................................................................... 87
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5.4
5.5 5.6
5.7
Interrupt Sources.................................................................................................................. 88 5.4.1 External Interrupts .................................................................................................. 88 5.4.2 Internal Interrupts ................................................................................................... 89 Interrupt Exception Handling Vector Table......................................................................... 90 Interrupt Control Modes and Interrupt Operation ................................................................ 93 5.6.1 Interrupt Control Mode 0 ........................................................................................ 95 5.6.2 Interrupt Control Mode 1 ........................................................................................ 97 5.6.3 Interrupt Exception Handling Sequence ............................................................... 100 5.6.4 Interrupt Response Times ..................................................................................... 101 5.6.5 DTC Activation by Interrupt................................................................................. 102 Usage Notes ....................................................................................................................... 104 5.7.1 Conflict between Interrupt Generation and Disabling .......................................... 104 5.7.2 Instructions that Disable Interrupts ....................................................................... 105 5.7.3 Interrupts during Execution of EEPMOV Instruction........................................... 105 5.7.4 IRQ Status Registers (ISR16, ISR) ....................................................................... 105
Section 6 Bus Controller (BSC).........................................................................107
6.1 6.2 6.3 Features.............................................................................................................................. 107 Input/Output Pins ............................................................................................................... 110 Register Descriptions ......................................................................................................... 111 6.3.1 Bus Control Register (BCR) ................................................................................. 111 6.3.2 Bus Control Register 2 (BCR2) ............................................................................ 113 6.3.3 Wait State Control Register (WSCR) ................................................................... 114 6.3.4 Wait State Control Register 2 (WSCR2) .............................................................. 116 6.3.5 System Control Register 2 (SYSCR2) .................................................................. 117 Bus Control ........................................................................................................................ 118 6.4.1 Bus Specifications................................................................................................. 118 6.4.2 Advanced Mode.................................................................................................... 125 6.4.3 I/O Select Signals.................................................................................................. 126 Bus Interface ...................................................................................................................... 127 6.5.1 Data Size and Data Alignment.............................................................................. 127 6.5.2 Valid Strobes......................................................................................................... 129 6.5.3 Valid Strobes (in Glueless Extension) .................................................................. 130 6.5.4 Basic Operation Timing in Normal Extended Mode ............................................ 131 6.5.5 Basic Operation Timing in Address-Data Multiplex Extended Mode .................. 142 6.5.6 Wait Control ......................................................................................................... 150 Burst ROM Interface.......................................................................................................... 154 6.6.1 Basic Operation Timing........................................................................................ 154 6.6.2 Wait Control ......................................................................................................... 155 Idle Cycle........................................................................................................................... 156
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6.4
6.5
6.6
6.7
6.8
Bus Arbitration .................................................................................................................. 157 6.8.1 Overview .............................................................................................................. 157 6.8.2 Operation .............................................................................................................. 157 6.8.3 Bus Mastership Transfer Timing .......................................................................... 158
Section 7 Data Transfer Controller (DTC)........................................................161
7.1 7.2 Features.............................................................................................................................. 161 Register Descriptions ......................................................................................................... 163 7.2.1 DTC Mode Register A (MRA) ............................................................................. 164 7.2.2 DTC Mode Register B (MRB).............................................................................. 165 7.2.3 DTC Source Address Register (SAR)................................................................... 165 7.2.4 DTC Destination Address Register (DAR)........................................................... 165 7.2.5 DTC Transfer Count Register A (CRA) ............................................................... 166 7.2.6 DTC Transfer Count Register B (CRB)................................................................ 166 7.2.7 DTC Enable Registers (DTCER).......................................................................... 166 7.2.8 DTC Vector Register (DTVECR)......................................................................... 167 7.2.9 Keyboard Comparator Control Register (KBCOMP)........................................... 168 7.2.10 Event Counter Control Register (ECCR).............................................................. 169 7.2.11 Event Counter Status Register (ECS) ................................................................... 170 DTC Event Counter ........................................................................................................... 171 7.3.1 Event Counter Handling Priority .......................................................................... 173 7.3.2 Usage Notes .......................................................................................................... 173 Activation Sources............................................................................................................. 174 Location of Register Information and DTC Vector Table ................................................. 175 Operation ........................................................................................................................... 177 7.6.1 Normal Mode........................................................................................................ 178 7.6.2 Repeat Mode......................................................................................................... 179 7.6.3 Block Transfer Mode ............................................................................................ 180 7.6.4 Chain Transfer ...................................................................................................... 181 7.6.5 Interrupt Sources................................................................................................... 182 7.6.6 Operation Timing.................................................................................................. 182 7.6.7 Number of DTC Execution States ........................................................................ 184 Procedures for Using DTC................................................................................................. 185 7.7.1 Activation by Interrupt.......................................................................................... 185 7.7.2 Activation by Software ......................................................................................... 185 Examples of Use of the DTC ............................................................................................. 186 7.8.1 Normal Mode........................................................................................................ 186 7.8.2 Software Activation .............................................................................................. 187 Usage Notes ....................................................................................................................... 188 7.9.1 Module Stop Mode Setting ................................................................................... 188
7.3
7.4 7.5 7.6
7.7
7.8
7.9
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7.9.2 7.9.3 7.9.4
On-Chip RAM ...................................................................................................... 188 DTCE Bit Setting.................................................................................................. 188 DTC Activation by Interrupt Sources of SCI, IIC, or A/D Converter .................. 188
Section 8 I/O Ports .............................................................................................189
8.1 I/O Ports for the H8S/2472 Group ..................................................................................... 189 8.1.1 Port 1..................................................................................................................... 194 8.1.2 Port 2..................................................................................................................... 197 8.1.3 Port 3..................................................................................................................... 202 8.1.4 Port 4..................................................................................................................... 208 8.1.5 Port 5..................................................................................................................... 216 8.1.6 Port 6..................................................................................................................... 221 8.1.7 Port 7..................................................................................................................... 227 8.1.8 Port 8..................................................................................................................... 231 8.1.9 Port 9..................................................................................................................... 236 8.1.10 Port A.................................................................................................................... 240 8.1.11 Port B .................................................................................................................... 248 8.1.12 Port C .................................................................................................................... 254 8.1.13 Port D.................................................................................................................... 259 8.1.14 Port E .................................................................................................................... 264 8.1.15 Port F .................................................................................................................... 268 I/O Ports for the H8S/2463 Group and the H8S/2462 Group ............................................ 272 8.2.1 Port 1..................................................................................................................... 277 8.2.2 Port 2..................................................................................................................... 280 8.2.3 Port 3..................................................................................................................... 285 8.2.4 Port 4..................................................................................................................... 291 8.2.5 Port 5..................................................................................................................... 299 8.2.6 Port 6..................................................................................................................... 304 8.2.7 Port 7..................................................................................................................... 311 8.2.8 Port 8..................................................................................................................... 315 8.2.9 Port 9..................................................................................................................... 320 8.2.10 Port A.................................................................................................................... 324 8.2.11 Port B .................................................................................................................... 332 8.2.12 Port C .................................................................................................................... 338 8.2.13 Port D.................................................................................................................... 343 8.2.14 Port E .................................................................................................................... 348 8.2.15 Port F .................................................................................................................... 353 Change of Peripheral Function Pins................................................................................... 356 8.3.1 IRQ Sense Port Select Register 16 (ISSR16), IRQ Sense Port Select Register (ISSR) .......................................................................................... 356
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8.2
8.3
8.3.2
Port Control Register 0 (PTCNT0) ....................................................................... 358
Section 9 14-Bit PWM Timer (PWMX) ...........................................................359
9.1 9.2 9.3 Features.............................................................................................................................. 359 Input/Output Pins............................................................................................................... 360 Register Descriptions ......................................................................................................... 360 9.3.1 PWMX (D/A) Counter (DACNT) ........................................................................ 361 9.3.2 PWMX (D/A) Data Registers A and B (DADRA and DADRB).......................... 362 9.3.3 PWMX (D/A) Control Register (DACR) ............................................................. 364 9.3.4 Peripheral Clock Select Register (PCSR) ............................................................. 365 Bus Master Interface .......................................................................................................... 366 Operation ........................................................................................................................... 367
9.4 9.5
Section 10 16-Bit Free-Running Timer (FRT).................................................. 375
10.1 Features.............................................................................................................................. 375 10.2 Register Descriptions ......................................................................................................... 377 10.2.1 Free-Running Counter (FRC) ............................................................................... 377 10.2.2 Output Compare Registers A and B (OCRA and OCRB) .................................... 377 10.2.3 Output Compare Registers AR and AF (OCRAR and OCRAF) .......................... 378 10.2.4 Timer Interrupt Enable Register (TIER)............................................................... 379 10.2.5 Timer Control/Status Register (TCSR)................................................................. 380 10.2.6 Timer Control Register (TCR).............................................................................. 381 10.2.7 Timer Output Compare Control Register (TOCR) ............................................... 382 10.3 Operation Timing............................................................................................................... 383 10.3.1 FRC Increment Timing......................................................................................... 383 10.3.2 Output Compare Output Timing........................................................................... 383 10.3.3 FRC Clear Timing ................................................................................................ 384 10.3.4 Timing of Output Compare Flag (OCF) Setting ................................................... 384 10.3.5 Timing of FRC Overflow Flag (OVF) Setting...................................................... 385 10.3.6 Automatic Addition Timing.................................................................................. 386 10.4 Interrupt Sources................................................................................................................ 386 10.5 Usage Notes ....................................................................................................................... 387 10.5.1 Conflict between FRC Write and Clear ................................................................ 387 10.5.2 Conflict between FRC Write and Increment......................................................... 388 10.5.3 Conflict between OCR Write and Compare-Match .............................................. 389 10.5.4 Switching of Internal Clock and FRC Operation.................................................. 390
Section 11 8-Bit Timer (TMR).......................................................................... 393
11.1 Features.............................................................................................................................. 393 11.2 Register Descriptions ......................................................................................................... 396
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11.3
11.4
11.5 11.6
11.2.1 Timer Counter (TCNT)......................................................................................... 396 11.2.2 Time Constant Register A (TCORA).................................................................... 397 11.2.3 Time Constant Register B (TCORB) .................................................................... 397 11.2.4 Timer Control Register (TCR).............................................................................. 398 11.2.5 Timer Control/Status Register (TCSR)................................................................. 401 11.2.6 Timer Connection Register S (TCONRS)............................................................. 405 Operation Timing............................................................................................................... 406 11.3.1 TCNT Count Timing............................................................................................. 406 11.3.2 Timing of CMFA and CMFB Setting at Compare-Match .................................... 406 11.3.3 Timing of Counter Clear at Compare-Match ........................................................ 407 11.3.4 Timing of Overflow Flag (OVF) Setting .............................................................. 407 TMR_0 and TMR_1 Cascaded Connection ....................................................................... 408 11.4.1 16-Bit Count Mode ............................................................................................... 408 11.4.2 Compare-Match Count Mode ............................................................................... 408 Interrupt Sources................................................................................................................ 409 Usage Notes ....................................................................................................................... 410 11.6.1 Conflict between TCNT Write and Counter Clear................................................ 410 11.6.2 Conflict between TCNT Write and Increment...................................................... 411 11.6.3 Conflict between TCOR Write and Compare-Match............................................ 412 11.6.4 Switching of Internal Clocks and TCNT Operation.............................................. 413 11.6.5 Mode Setting with Cascaded Connection ............................................................. 414
Section 12 Watchdog Timer (WDT)..................................................................415
12.1 Features.............................................................................................................................. 415 12.2 Input/Output Pins ............................................................................................................... 417 12.3 Register Descriptions ......................................................................................................... 417 12.3.1 Timer Counter (TCNT)......................................................................................... 417 12.3.2 Timer Control/Status Register (TCSR)................................................................. 418 12.4 Operation ........................................................................................................................... 422 12.4.1 Watchdog Timer Mode ......................................................................................... 422 12.4.2 Interval Timer Mode............................................................................................. 424 12.4.3 RESO Signal Output Timing ................................................................................ 425 12.5 Interrupt Sources................................................................................................................ 426 12.6 Usage Notes ....................................................................................................................... 427 12.6.1 Notes on Register Access...................................................................................... 427 12.6.2 Conflict between Timer Counter (TCNT) Write and Increment........................... 428 12.6.3 Changing Values of CKS2 to CKS0 Bits.............................................................. 428 12.6.4 Changing Value of PSS Bit................................................................................... 428 12.6.5 Switching between Watchdog Timer Mode and Interval Timer Mode................. 429 12.6.6 System Reset by RESO Signal.............................................................................. 429
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Section 13 Serial Communication Interface (SCI)............................................431
13.1 Features.............................................................................................................................. 431 13.2 Input/Output Pins............................................................................................................... 434 13.3 Register Descriptions ......................................................................................................... 434 13.3.1 Receive Shift Register (RSR) ............................................................................... 435 13.3.2 Receive Data Register (RDR) ............................................................................... 435 13.3.3 Transmit Data Register (TDR).............................................................................. 435 13.3.4 Transmit Shift Register (TSR) .............................................................................. 435 13.3.5 Serial Mode Register (SMR) ................................................................................ 436 13.3.6 Serial Control Register (SCR) .............................................................................. 439 13.3.7 Serial Status Register (SSR) ................................................................................. 442 13.3.8 Smart Card Mode Register (SCMR)..................................................................... 446 13.3.9 Bit Rate Register (BRR) ....................................................................................... 447 13.4 Operation in Asynchronous Mode ..................................................................................... 451 13.4.1 Data Transfer Format............................................................................................ 452 13.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode............................................................................................. 453 13.4.3 Clock..................................................................................................................... 454 13.4.4 SCI Initialization (Asynchronous Mode).............................................................. 455 13.4.5 Serial Data Transmission (Asynchronous Mode) ................................................. 456 13.4.6 Serial Data Reception (Asynchronous Mode) ...................................................... 458 13.5 Multiprocessor Communication Function.......................................................................... 462 13.5.1 Multiprocessor Serial Data Transmission ............................................................. 464 13.5.2 Multiprocessor Serial Data Reception .................................................................. 465 13.6 Operation in Clock Synchronous Mode............................................................................. 468 13.6.1 Clock..................................................................................................................... 468 13.6.2 SCI Initialization (Clock Synchronous Mode)...................................................... 469 13.6.3 Serial Data Transmission (Clock Synchronous Mode)......................................... 470 13.6.4 Serial Data Reception (Clock Synchronous Mode) .............................................. 473 13.6.5 Simultaneous Serial Data Transmission and Reception (Clock Synchronous Mode) .................................................................................. 475 13.7 Smart Card Interface Description ...................................................................................... 477 13.7.1 Sample Connection ............................................................................................... 477 13.7.2 Data Format (Except in Block Transfer Mode) .................................................... 477 13.7.3 Block Transfer Mode ............................................................................................ 479 13.7.4 Receive Data Sampling Timing and Reception Margin ....................................... 480 13.7.5 Initialization.......................................................................................................... 481 13.7.6 Serial Data Transmission (Except in Block Transfer Mode) ................................ 482 13.7.7 Serial Data Reception (Except in Block Transfer Mode) ..................................... 485 13.7.8 Clock Output Control............................................................................................ 487
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13.8 Interrupt Sources................................................................................................................ 489 13.8.1 Interrupts in Normal Serial Communication Interface Mode ............................... 489 13.8.2 Interrupts in Smart Card Interface Mode .............................................................. 490 13.9 Usage Notes ....................................................................................................................... 491 13.9.1 Module Stop Mode Setting ................................................................................... 491 13.9.2 Break Detection and Processing ........................................................................... 491 13.9.3 Mark State and Break Sending.............................................................................. 491 13.9.4 Receive Error Flags and Transmit Operations (Clock Synchronous Mode Only) ......................................................................... 491 13.9.5 Relation between Writing to TDR and TDRE Flag .............................................. 491 13.9.6 Restrictions on Using DTC ................................................................................... 492 13.9.7 SCI Operations during Mode Transitions ............................................................. 493 13.9.8 Notes on Switching from SCK Pins to Port Pins .................................................. 497
Section 14 CRC Operation Circuit (CRC).........................................................499
14.1 Features.............................................................................................................................. 499 14.2 Register Descriptions ......................................................................................................... 500 14.2.1 CRC Control Register (CRCCR) .......................................................................... 500 14.2.2 CRC Data Input Register (CRCDIR).................................................................... 501 14.2.3 CRC Data Output Register (CRCDOR)................................................................ 501 14.3 CRC Operation Circuit Operation...................................................................................... 501 14.4 Note on CRC Operation Circuit......................................................................................... 505
Section 15 Serial Communication Interface with FIFO (SCIF) ........................507
15.1 Features.............................................................................................................................. 507 15.2 Input/Output Pins ............................................................................................................... 509 15.3 Register Descriptions ......................................................................................................... 510 15.3.1 Receive Shift Register (FRSR) ............................................................................. 511 15.3.2 Receive Buffer Register (FRBR) .......................................................................... 511 15.3.3 Transmitter Shift Register (FTSR)........................................................................ 511 15.3.4 Transmitter Holding Register (FTHR).................................................................. 512 15.3.5 Divisor Latch H, L (FDLH, FDLL) ...................................................................... 512 15.3.6 Interrupt Enable Register (FIER) .......................................................................... 513 15.3.7 Interrupt Identification Register (FIIR)................................................................. 514 15.3.8 FIFO Control Register (FFCR) ............................................................................. 516 15.3.9 Line Control Register (FLCR) .............................................................................. 517 15.3.10 Modem Control Register (FMCR) ........................................................................ 518 15.3.11 Line Status Register (FLSR) ................................................................................. 520 15.3.12 Modem Status Register (FMSR)........................................................................... 524 15.3.13 Scratch Pad Register (FSCR)................................................................................ 525
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15.3.14 SCIF Control Register (SCIFCR) ......................................................................... 526 15.4 Operation ........................................................................................................................... 528 15.4.1 Baud Rate ............................................................................................................. 528 15.4.2 Operation in Asynchronous Communication........................................................ 529 15.4.3 Initialization of the SCIF ...................................................................................... 530 15.4.4 Data Transmission/Reception with Flow Control................................................. 533 15.4.5 Data Transmission/Reception Through the LPC Interface ................................... 539 15.5 Interrupt Sources................................................................................................................ 541 15.6 Usage Note......................................................................................................................... 541 15.6.1 Power-Down Mode When LCLK is Selected for SCLK ...................................... 541
Section 16 Serial Pin Multiplexed Modes .........................................................543
16.1 Features.............................................................................................................................. 543 16.2 Input/Output Pins............................................................................................................... 544 16.3 Register Descriptions ......................................................................................................... 545 16.3.1 Serial Multiplexed Mode Register 0 (SMR0) ....................................................... 545 16.3.2 Serial Multiplexed Mode Register 1 (SMR1) ....................................................... 546 16.4 Operation of Serial Pin Multiplexed Modes ...................................................................... 547 16.4.1 Serial Pin Multiplexed Mode 0 (Default; SMR0 Register [bits SM2, SM1, SM0] = [0 0 0])................................. 547 16.4.2 Serial Pin Multiplexed Mode 1 (SMR0 Register [bits SM2, SM1, SM0] = [0 0 1])............................................... 548 16.4.3 Serial Pin Multiplexed Mode 2 (SMR0 Register [bits SM2, SM1, SM0] = [0 1 0])............................................... 549 16.4.4 Serial Pin Multiplexed Mode 3 (SMR0 Register [bits SM2, SM1, SM0] = [0 1 1])............................................... 550 16.4.5 Serial Pin Multiplexed Mode 4 (SMR0 Register [bits SM2, SM1, SM0] = [1 0 0])............................................... 551 16.5 Serial Port Pin Configuration............................................................................................. 552
Section 17 Synchronous Serial Communication Unit (SSU) ............................ 553
17.1 Features.............................................................................................................................. 553 17.2 Input/Output Pins............................................................................................................... 555 17.3 Register Descriptions ......................................................................................................... 555 17.3.1 SS Control Register H (SSCRH) .......................................................................... 556 17.3.2 SS Control Register L (SSCRL) ........................................................................... 558 17.3.3 SS Mode Register (SSMR) ................................................................................... 559 17.3.4 SS Enable Register (SSER) .................................................................................. 560 17.3.5 SS Status Register (SSSR) .................................................................................... 561 17.3.6 SS Control Register 2 (SSCR2) ............................................................................ 563
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17.3.7 SS Transmit Data Registers 0 to 3 (SSTDR0 to SSTDR3)................................... 564 17.3.8 SS Receive Data Registers 0 to 3 (SSRDR0 to SSRDR3) .................................... 565 17.3.9 SS Shift Register (SSTRSR) ................................................................................. 565 17.4 Operation ........................................................................................................................... 566 17.4.1 Transfer Clock ...................................................................................................... 566 17.4.2 Relationship of Clock Phase, Polarity, and Data .................................................. 566 17.4.3 Relationship between Data Input/Output Pins and Shift Register ........................ 567 17.4.4 Communication Modes and Pin Functions ........................................................... 568 17.4.5 SSU Mode............................................................................................................. 570 17.4.6 SCS Pin Control and Conflict Error...................................................................... 578 17.4.7 Clock Synchronous Communication Mode .......................................................... 579 17.5 Interrupt Requests .............................................................................................................. 585 17.6 Usage Note......................................................................................................................... 585 17.6.1 Setting of Module Stop Mode............................................................................... 585
Section 18 I2C Bus Interface (IIC) .....................................................................587
18.1 Features.............................................................................................................................. 587 18.2 Input/Output Pins ............................................................................................................... 590 18.3 Register Descriptions ......................................................................................................... 591 2 18.3.1 I C Bus Data Register (ICDR) .............................................................................. 591 18.3.2 Slave Address Register (SAR) .............................................................................. 592 18.3.3 Second Slave Address Register (SARX) .............................................................. 593 2 18.3.4 I C Bus Mode Register (ICMR)............................................................................ 595 2 18.3.5 I C Bus Transfer Rate Select Register (IICX3)..................................................... 597 2 18.3.6 I C Bus Control Register (ICCR) .......................................................................... 600 2 18.3.7 I C Bus Status Register (ICSR)............................................................................. 609 2 18.3.8 I C Bus Extended Control Register (ICXR).......................................................... 613 2 18.3.9 I C SMBus Control Register (ICSMBCR)............................................................ 617 18.4 Operation ........................................................................................................................... 619 2 18.4.1 I C Bus Data Format ............................................................................................. 619 18.4.2 Initialization .......................................................................................................... 621 18.4.3 Master Transmit Operation ................................................................................... 621 18.4.4 Master Receive Operation..................................................................................... 625 18.4.5 Slave Receive Operation....................................................................................... 634 18.4.6 Slave Transmit Operation ..................................................................................... 642 18.4.7 IRIC Setting Timing and SCL Control ................................................................. 645 18.4.8 Operation Using the DTC ..................................................................................... 648 18.4.9 Noise Canceler ...................................................................................................... 650 18.4.10 Initialization of Internal State ............................................................................... 650 18.5 Interrupt Source ................................................................................................................. 652
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18.6 Usage Notes ....................................................................................................................... 653
Section 19 LPC Interface (LPC)........................................................................665
19.1 Features.............................................................................................................................. 665 19.2 Input/Output Pins............................................................................................................... 668 19.3 Register Descriptions ......................................................................................................... 669 19.3.1 Host Interface Control Registers 0 and 1 (HICR0 and HICR1)............................ 671 19.3.2 Host Interface Control Registers 2 and 3 (HICR2 and HICR3)............................ 679 19.3.3 Host Interface Control Register 4 (HICR4) .......................................................... 682 19.3.4 Host Interface Control Register 5 (HICR5) .......................................................... 683 19.3.5 Pin Function Control Register (PINFNCR) .......................................................... 684 19.3.6 LPC Channel 1, 2 Address Register H, L (LADR12H, LADR12L)..................... 684 19.3.7 LPC Channel 3 Address Register H, L (LADR3H, LADR3L)............................. 686 19.3.8 Input Data Registers 1 to 3 (IDR1 to IDR3) ......................................................... 689 19.3.9 Output Data Registers 0 to 3 (ODR1 to ODR3) ................................................... 689 19.3.10 Bidirectional Data Registers 0 to 15 (TWR0 to TWR15)..................................... 690 19.3.11 Status Registers 1 to 3 (STR1 to STR3) ............................................................... 691 19.3.12 SERIRQ Control Register 0 (SIRQCR0).............................................................. 699 19.3.13 SERIRQ Control Register 1 (SIRQCR1).............................................................. 703 19.3.14 SERIRQ Control Register 2 (SIRQCR2).............................................................. 707 19.3.15 SERIRQ Control Register 3 (SIRQCR3).............................................................. 708 19.3.16 SERIRQ Control Register 4 (SIRQCR4).............................................................. 709 19.3.17 SERIRQ Control Register 5 (SIRQCR5).............................................................. 710 19.3.18 Host Interface Select Register (HISEL)................................................................ 711 19.3.19 SCIF Address Register (SCIFADRH, SCIFADRL) ............................................. 712 19.3.20 SMIC Flag Register (SMICFLG) ......................................................................... 713 19.3.21 SMIC Control Status Register (SMICCSR).......................................................... 714 19.3.22 SMIC Data Register (SMICDTR) ........................................................................ 714 19.3.23 SMIC Interrupt Register 0 (SMICIR0) ................................................................. 715 19.3.24 SMIC Interrupt Register 1 (SMICIR1) ................................................................. 717 19.3.25 BT Status Register 0 (BTSR0).............................................................................. 718 19.3.26 BT Status Register 1 (BTSR1).............................................................................. 721 19.3.27 BT Control Status Register 0 (BTCSR0) .............................................................. 724 19.3.28 BT Control Status Register 1 (BTCSR1) .............................................................. 725 19.3.29 BT Control Register (BTCR)................................................................................ 727 19.3.30 BT Data Buffer (BTDTR)..................................................................................... 730 19.3.31 BT Interrupt Mask Register (BTIMSR)................................................................ 730 19.3.32 BT FIFO Valid Size Register 0 (BTFVSR0) ........................................................ 732 19.3.33 BT FIFO Valid Size Register 1 (BTFVSR1) ........................................................ 732
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19.4 Operation ........................................................................................................................... 733 19.4.1 LPC interface Activation ...................................................................................... 733 19.4.2 LPC I/O Cycles ..................................................................................................... 733 19.4.3 SMIC Mode Transfer Flow................................................................................... 735 19.4.4 BT Mode Transfer Flow ....................................................................................... 738 19.4.5 Gate A20 ............................................................................................................... 740 19.4.6 LPC Interface Shutdown Function (LPCPD)........................................................ 743 19.4.7 LPC Interface Serialized Interrupt Operation (SERIRQ)...................................... 747 19.4.8 LPC Interface Clock Start Request ....................................................................... 749 19.4.9 SCIF Control from LPC Interface......................................................................... 749 19.5 Interrupt Sources................................................................................................................ 750 19.5.1 IBFI1, IBFI2, IBFI3, and ERRI ............................................................................ 750 19.5.2 SMI, HIRQ1, HIRQ3, HIRQ4, HIRQ5, HIRQ6, HIRQ7, HIRQ8, HIRQ9, HIRQ10, HIRQ11, HIRQ12, HIRQ13, HIRQ14, and HIRQ15............................ 751 19.6 Usage Note......................................................................................................................... 754 19.6.1 Data Conflict......................................................................................................... 754
Section 20 Ethernet Controller (EtherC)............................................................757
20.1 Features.............................................................................................................................. 757 20.2 Input/Output Pins ............................................................................................................... 759 20.3 Register Description........................................................................................................... 760 20.3.1 EtherC Mode Register (ECMR)............................................................................ 761 20.3.2 EtherC Status Register (ECSR)............................................................................. 764 20.3.3 EtherC Interrupt Permission Register (ECSIPR) .................................................. 766 20.3.4 PHY Interface Register (PIR) ............................................................................... 767 20.3.5 MAC Address High Register (MAHR)................................................................. 768 20.3.6 MAC Address Low Register (MALR).................................................................. 768 20.3.7 Receive Frame Length Register (RFLR) .............................................................. 769 20.3.8 PHY Status Register (PSR)................................................................................... 770 20.3.9 Transmit Retry Over Counter Register (TROCR) ................................................ 770 20.3.10 Delayed Collision Detect Counter Register (CDCR)............................................ 771 20.3.11 Lost Carrier Counter Register (LCCR) ................................................................. 771 20.3.12 Carrier Not Detect Counter Register (CNDCR) ................................................... 771 20.3.13 CRC Error Frame Counter Register (CEFCR)...................................................... 772 20.3.14 Frame Receive Error Counter Register (FRECR)................................................. 772 20.3.15 Too-Short Frame Receive Counter Register (TSFRCR)....................................... 772 20.3.16 Too-Long Frame Receive Counter Register (TLFRCR)....................................... 773 20.3.17 Residual-Bit Frame Counter Register (RFCR) ..................................................... 773 20.3.18 Multicast Address Frame Counter Register (MAFCR)......................................... 773 20.3.19 IPG Register (IPGR) ............................................................................................. 774
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20.3.20 Automatic PAUSE Frame Set Register (APR) ..................................................... 774 20.3.21 Manual PAUSE Frame Set Register (MPR) ......................................................... 775 20.3.22 Automatic PAUSE Frame Retransmission Count Set Register (TPAUSER) ....... 775 20.4 Operation ........................................................................................................................... 776 20.4.1 Transmission......................................................................................................... 776 20.4.2 Reception .............................................................................................................. 779 20.4.3 RMII Frame Timing.............................................................................................. 780 20.4.4 Accessing MII Registers ....................................................................................... 782 20.4.5 Magic Packet Detection ........................................................................................ 785 20.4.6 Operation by IPG Setting...................................................................................... 786 20.4.7 Flow Control......................................................................................................... 786 20.5 Usage Notes ....................................................................................................................... 788 20.5.1 Conditions for Setting LCHNG Bit ...................................................................... 788 20.5.2 Flow Control Defect 1 .......................................................................................... 788 20.5.3 Flow Control Defect 2 .......................................................................................... 788 20.5.4 Operation Seed...................................................................................................... 789
Section 21 Ethernet Controller Direct Memory Access Controller (E-DMAC).......................................................................................791
21.1 Features.............................................................................................................................. 791 21.2 Register Descriptions ......................................................................................................... 792 21.2.1 E-DMAC Mode Register (EDMR) ....................................................................... 794 21.2.2 E-DMAC Transmit Request Register (EDTRR)................................................... 795 21.2.3 E-DMAC Receive Request Register (EDRRR).................................................... 796 21.2.4 Transmit Descriptor List Address Register (TDLAR).......................................... 797 21.2.5 Receive Descriptor List Address Register (RDLAR) ........................................... 797 21.2.6 EtherC/E-DMAC Status Register (EESR) ............................................................ 798 21.2.7 EtherC/E-DMAC Status Interrupt Permission Register (EESIPR) ....................... 803 21.2.8 Transmit/Receive Status Copy Enable Register (TRSCER)................................. 806 21.2.9 Receive Missed-Frame Counter Register (RMFCR) ............................................ 806 21.2.10 Transmit FIFO Threshold Register (TFTR).......................................................... 807 21.2.11 FIFO Depth Register (FDR) ................................................................................. 809 21.2.12 Receiving method Control Register (RMCR)....................................................... 810 21.2.13 Receiving-Buffer Write Address Register (RBWAR) .......................................... 810 21.2.14 Receiving-Descriptor Fetch Address Register (RDFAR) ..................................... 811 21.2.15 Transmission-Buffer Read Address Register (TBRAR) ....................................... 811 21.2.16 Transmission-Descriptor Fetch Address Register (TDFAR) ................................ 811 21.2.17 Flow Control FIFO Threshold Register (FCFTR) ................................................ 812 21.2.18 Bit Rate Setting Register (ECBRR) ...................................................................... 813 21.2.19 Transmit Interrupt Register (TRIMD) .................................................................. 814
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21.3 Operation ........................................................................................................................... 815 21.3.1 Descriptor List and Data Buffers .......................................................................... 815 21.3.2 Transmission......................................................................................................... 825 21.3.3 Reception .............................................................................................................. 827 21.3.4 Multi-Buffer Frame Transmit/Receive Processing ............................................... 829
Section 22 USB Function Module (USB)..........................................................831
22.1 Features.............................................................................................................................. 831 22.2 Input/Output Pins ............................................................................................................... 832 22.3 Register Descriptions ......................................................................................................... 833 22.3.1 Interrupt Flag Register 0 (IFR0) ........................................................................... 834 22.3.2 Interrupt Flag Register 1 (IFR1) ........................................................................... 836 22.3.3 Interrupt Flag Register 2 (IFR2) ........................................................................... 837 22.3.4 Interrupt Select Register 0 (ISR0)......................................................................... 838 22.3.5 Interrupt Select Register 1 (ISR1)......................................................................... 839 22.3.6 Interrupt Select Register 2 (ISR2)......................................................................... 839 22.3.7 Interrupt Enable Register 0 (IER0) ....................................................................... 840 22.3.8 Interrupt Enable Register 1 (IER1) ....................................................................... 840 22.3.9 Interrupt Enable Register 2 (IER2) ....................................................................... 841 22.3.10 EP0i Data Register (EPDR0i) ............................................................................... 841 22.3.11 EP0o Data Register (EPDR0o) ............................................................................. 842 22.3.12 EP0s Data Register (EPDR0s) .............................................................................. 842 22.3.13 EP1 Data Register (EPDR1) ................................................................................. 843 22.3.14 EP2 Data Register (EPDR2) ................................................................................. 843 22.3.15 EP3 Data Register (EPDR3) ................................................................................. 843 22.3.16 EP0o Receive Data Size Register (EPSZ0o) ........................................................ 844 22.3.17 EP1 Receive Data Size Register (EPSZ1) ............................................................ 844 22.3.18 Trigger Register (TRG)......................................................................................... 844 22.3.19 Data Status Register (DASTS).............................................................................. 846 22.3.20 FIFO Clear Register (FCLR) ................................................................................ 847 22.3.21 DTC Transfer Setting Register (DMA) ................................................................ 848 22.3.22 Endpoint Stall Register (EPSTL).......................................................................... 851 22.3.23 Configuration Value Register (CVR) ................................................................... 852 22.3.24 Control Register (CTLR) ...................................................................................... 852 22.3.25 Endpoint Information Register (EPIR) ................................................................. 854 22.3.26 Transceiver Test Register 0 (TRNTREG0)........................................................... 858 22.3.27 Transceiver Test Register 1 (TRNTREG1)........................................................... 859 22.4 Interrupt Sources................................................................................................................ 861 22.5 Operation ........................................................................................................................... 863 22.5.1 Operation at Cable Connection ............................................................................. 863
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22.6 22.7
22.8
22.9 22.10
22.5.2 Operation at Cable Disconnection ........................................................................ 864 22.5.3 Suspend and Resume Operations.......................................................................... 865 22.5.4 Control Transfer.................................................................................................... 870 22.5.5 EP1 Bulk-Out Transfer (Dual FIFOs)................................................................... 876 22.5.6 EP2 Bulk-In Transfer (Dual FIFOs) ..................................................................... 877 22.5.7 EP3 Interrupt-In Transfer...................................................................................... 879 Processing of USB Standard Commands and Class/Vendor Commands .......................... 880 22.6.1 Processing of Commands Transmitted by Control Transfer................................. 880 Stall Operations.................................................................................................................. 881 22.7.1 Overview .............................................................................................................. 881 22.7.2 Forcible Stall by Application ................................................................................ 881 22.7.3 Automatic Stall by USB Function Module ........................................................... 883 DTC Transfer..................................................................................................................... 884 22.8.1 Overview .............................................................................................................. 884 22.8.2 DTC Transfer for Endpoint 1................................................................................ 885 22.8.3 DTC Transfer for Endpoint 2................................................................................ 886 22.8.4 DTC Transfer End Interrupt.................................................................................. 887 Example of USB External Circuitry .................................................................................. 888 Usage Notes ....................................................................................................................... 890 22.10.1 Receiving Setup Data............................................................................................ 890 22.10.2 Clearing the FIFO ................................................................................................. 890 22.10.3 Overreading and Overwriting the Data Registers ................................................. 890 22.10.4 Assigning Interrupt Sources to EP0 ...................................................................... 891 22.10.5 Clearing the FIFO When DTC Transfer is Enabled.............................................. 891 22.10.6 Notes on TR Interrupt ........................................................................................... 891 22.10.7 Restrictions on Peripheral Module Clock () Operating Frequency..................... 892
Section 23 A/D Converter .................................................................................893
23.1 Features.............................................................................................................................. 893 23.2 Input/Output Pins............................................................................................................... 895 23.3 Register Descriptions ......................................................................................................... 896 23.3.1 A/D Data Registers A to H (ADDRA to ADDRH) .............................................. 896 23.3.2 A/D Control/Status Register (ADCSR) ................................................................ 897 23.3.3 A/D Control Register (ADCR) ............................................................................. 899 23.4 Operation ........................................................................................................................... 900 23.4.1 Single Mode.......................................................................................................... 900 23.4.2 Scan Mode ............................................................................................................ 901 23.4.3 Input Sampling and A/D Conversion Time .......................................................... 903 23.4.4 Timing of External Trigger Input ......................................................................... 906 23.5 Interrupt Source ................................................................................................................. 907
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23.6 A/D Conversion Accuracy Definitions .............................................................................. 907 23.7 Usage Notes ....................................................................................................................... 909 23.7.1 Setting of Module Stop Mode............................................................................... 909 23.7.2 Permissible Signal Source Impedance .................................................................. 909 23.7.3 Influences on Absolute Accuracy ......................................................................... 910 23.7.4 Setting Range of Analog Power Supply and Other Pins ....................................... 910 23.7.5 Notes on Board Design ......................................................................................... 910 23.7.6 Notes on Noise Countermeasures ......................................................................... 911 23.7.7 Note on the Usage in Software Standby Mode ..................................................... 912
Section 24 RAM ................................................................................................913 Section 25 Flash Memory ..................................................................................915
25.1 Features.............................................................................................................................. 915 25.1.1 Operating Mode .................................................................................................... 917 25.1.2 Mode Comparison................................................................................................. 918 25.1.3 Flash Memory MAT Configuration ...................................................................... 919 25.1.4 Block Division ...................................................................................................... 919 25.1.5 Programming/Erasing Interface ............................................................................ 921 25.2 Input/Output Pins ............................................................................................................... 923 25.3 Register Descriptions ......................................................................................................... 924 25.3.1 Programming/Erasing Interface Register .............................................................. 926 25.3.2 Programming/Erasing Interface Parameter ........................................................... 934 25.4 On-Board Programming Mode .......................................................................................... 945 25.4.1 Boot Mode ............................................................................................................ 946 25.4.2 USB Boot Mode.................................................................................................... 950 25.4.3 User Program Mode.............................................................................................. 954 25.4.4 User Boot Mode.................................................................................................... 965 25.4.5 Procedure Program and Storable Area for Programming Data............................. 970 25.5 Protection ........................................................................................................................... 980 25.5.1 Hardware Protection ............................................................................................. 980 25.5.2 Software Protection............................................................................................... 982 25.5.3 Error Protection..................................................................................................... 982 25.6 Switching between User MAT and User Boot MAT ......................................................... 984 25.7 Programmer Mode ............................................................................................................. 985 25.8 Serial Communication Interface Specification for Boot Mode.......................................... 986 25.9 Usage Notes ..................................................................................................................... 1014
Section 26 Boundary Scan (JTAG)..................................................................1017
26.1 Features............................................................................................................................ 1017
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26.2 Input/Output Pins............................................................................................................. 1019 26.3 Register Descriptions ....................................................................................................... 1020 26.3.1 Instruction Register (SDIR) ................................................................................ 1021 26.3.2 Bypass Register (SDBPR) .................................................................................. 1022 26.3.3 Boundary Scan Register (SDBSR) ..................................................................... 1022 26.3.4 ID Code Register (SDIDR)................................................................................. 1040 26.4 Operation ......................................................................................................................... 1041 26.4.1 TAP Controller State Transitions........................................................................ 1041 26.4.2 JTAG Reset......................................................................................................... 1042 26.5 Boundary Scan................................................................................................................. 1042 26.5.1 Supported Instructions ........................................................................................ 1042 26.6 Usage Notes ..................................................................................................................... 1045
Section 27 Clock Pulse Generator...................................................................1049
27.1 Oscillator.......................................................................................................................... 1050 27.1.1 Connecting Crystal Resonator ............................................................................ 1050 27.1.2 External Clock Input Method.............................................................................. 1051 27.2 PLL Multiplier Circuit ..................................................................................................... 1052 27.3 Medium-Speed Clock Divider ......................................................................................... 1052 27.4 Bus Master Clock Select Circuit...................................................................................... 1052 27.5 Subclock Input Circuit ..................................................................................................... 1052 27.6 Subclock Waveform Shaping Circuit .............................................................................. 1052 27.7 Clock Select Circuit ......................................................................................................... 1053 27.8 Usage Notes ..................................................................................................................... 1054 27.8.1 Note on Resonator .............................................................................................. 1054 27.8.2 Notes on Board Design ....................................................................................... 1054 27.8.3 Note on Operation Check ................................................................................... 1054
Section 28 Power-Down Modes ......................................................................1055
28.1 Register Descriptions ....................................................................................................... 1056 28.1.1 Standby Control Register (SBYCR) ................................................................... 1056 28.1.2 Low-Power Control Register (LPWRCR) .......................................................... 1059 28.1.3 Module Stop Control Registers H, L, and A (MSTPCRH, MSTPCRL, MSTPCRA) .............................................................. 1060 28.1.4 Sub-Chip Module Stop Control Registers BH, BL (SUBMSTPBH, SUBMSTPBL)......................................................................... 1062 28.2 Mode Transitions and LSI States ..................................................................................... 1063 28.3 Medium-Speed Mode....................................................................................................... 1065 28.4 Sleep Mode ...................................................................................................................... 1066 28.5 Software Standby Mode................................................................................................... 1067
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28.6 Hardware Standby Mode ................................................................................................. 1069 28.7 Module Stop Mode .......................................................................................................... 1070 28.8 Usage Notes ..................................................................................................................... 1070 28.8.1 I/O Port Status..................................................................................................... 1070 28.8.2 Current Consumption when Waiting for Oscillation Settling ............................. 1070 28.8.3 DTC Module Stop Mode .................................................................................... 1070 28.8.4 Notes on Subclock Usage ................................................................................... 1070
Section 29 List of Registers .............................................................................1071
29.1 Register Addresses (Address Order)................................................................................ 1072 29.2 Register Bits..................................................................................................................... 1086 29.3 Register States in Each Operating Mode.......................................................................... 1104
Section 30 Platform Environment Control Interface (PECI)...........................1117 Section 31 Electrical Characteristics ...............................................................1119
31.1 Absolute Maximum Ratings ............................................................................................ 1119 31.2 DC Characteristics ........................................................................................................... 1120 31.3 AC Characteristics ........................................................................................................... 1125 31.3.1 Clock Timing ...................................................................................................... 1125 31.3.2 Control Signal Timing ........................................................................................ 1130 31.3.3 Bus Timing ......................................................................................................... 1132 31.3.4 Multiplex Bus Timing......................................................................................... 1141 31.3.5 Timing of On-Chip Peripheral Modules ............................................................. 1144 31.4 A/D Conversion Characteristics....................................................................................... 1161 31.5 Flash Memory Characteristics ......................................................................................... 1162 31.6 Usage Notes ..................................................................................................................... 1163
Appendix
A. B. C.
........................................................................................................1165
I/O Port States in Each Processing State.......................................................................... 1165 Product Lineup................................................................................................................. 1168 Package Dimensions ........................................................................................................ 1169
Main Revisions and Additions in this Edition ...................................................1173 Index ........................................................................................................1191
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Figures
Section 1 Figure 1.1 Figure 1.2 Figure 1.3 Figure 1.4 Overview Internal Block Diagram ................................................................................................ 3 Pin Assignments (H8S/2472 Group) ............................................................................ 4 Pin Assignments (H8S/2463 Group) ............................................................................ 5 Pin Assignments (H8S/2462 Group) ............................................................................ 6
Section 2 CPU Figure 2.1 Exception Vector Table (Normal Mode).................................................................... 29 Figure 2.2 Stack Structure in Normal Mode................................................................................ 29 Figure 2.3 Exception Vector Table (Advanced Mode)................................................................ 30 Figure 2.4 Stack Structure in Advanced Mode............................................................................ 31 Figure 2.5 Memory Map.............................................................................................................. 32 Figure 2.6 CPU Registers ............................................................................................................ 33 Figure 2.7 Usage of General Registers ........................................................................................ 34 Figure 2.8 Stack........................................................................................................................... 35 Figure 2.9 General Register Data Formats (1)............................................................................. 38 Figure 2.9 General Register Data Formats (2)............................................................................. 39 Figure 2.10 Memory Data Formats ............................................................................................. 40 Figure 2.11 Instruction Formats (Examples) ............................................................................... 52 Figure 2.12 Branch Address Specification in Memory Indirect Mode........................................ 56 Figure 2.13 State Transitions....................................................................................................... 60 Section 3 MCU Operating Modes Figure 3.1 Address Map .............................................................................................................. 69 Section 4 Figure 4.1 Figure 4.2 Figure 4.3 Section 5 Figure 5.1 Figure 5.2 Figure 5.3 Figure 5.4 Figure 5.5 Figure 5.6 Figure 5.7 Figure 5.8 Exception Handling Reset Sequence........................................................................................................... 75 Stack Status after Exception Handling ....................................................................... 77 Operation When SP Value is Odd .............................................................................. 78 Interrupt Controller Block Diagram of Interrupt Controller....................................................................... 80 Block Diagram of Interrupts IRQ15 to IRQ0............................................................. 89 Block Diagram of Interrupt Control Operation .......................................................... 93 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 0 ..... 96 State Transition in Interrupt Control Mode 1 ............................................................. 97 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 1.... 99 Interrupt Exception Handling................................................................................... 100 Interrupt Control for DTC ........................................................................................ 102
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Figure 5.9 Conflict between Interrupt Generation and Disabling.............................................. 104 Section 6 Bus Controller (BSC) Figure 6.1 Block Diagram of Bus Controller............................................................................. 109 Figure 6.2 IOS Signal Output Timing ....................................................................................... 126 Figure 6.3 Access Sizes and Data Alignment Control (8-bit Access Space) ............................. 127 Figure 6.4 Access Sizes and Data Alignment Control (16-bit Access Space) ........................... 128 Figure 6.5 Bus Timing for 8-Bit, 2-State Access Space ............................................................ 131 Figure 6.6 Bus Timing for 8-Bit, 3-State Access Space ............................................................ 132 Figure 6.7 Bus Timing for 16-Bit, 2-State Access Space (Even Byte Access).......................... 133 Figure 6.8 Bus Timing for 16-Bit, 2-State Access Space (Odd Byte Access) ........................... 134 Figure 6.9 Bus Timing for 16-Bit, 2-State Access Space (Word Access) ................................. 135 Figure 6.10 Bus Timing for 16-Bit, 3-State Access Space (Even Byte Access)........................ 136 Figure 6.11 Bus Timing for 16-Bit, 3-State Access Space (Odd Byte Access) ......................... 137 Figure 6.12 Bus Timing for 16-Bit, 3-State Access Space (Word Access) ............................... 138 Figure 6.13 Glueless Extension Even Byte Access (ADMXE = 0)........................................... 139 Figure 6.14 Glueless Extension Odd Byte Access (ADMXE = 0) ............................................ 140 Figure 6.15 Glueless Extension Word Access (ADMXE = 0) .................................................. 141 Figure 6.16 Bus Timing for 8-Bit, 2-State Access Space .......................................................... 142 Figure 6.17 Bus Timing for 8-Bit, 2-State Access Space .......................................................... 143 Figure 6.18 Bus Timing for 8-Bit, 3-State Access Space .......................................................... 143 Figure 6.19 Bus Timing for 16-Bit, 2-State Access Space (1) (Even Byte Access) .................. 144 Figure 6.20 Bus Timing for 16-Bit, 2-State Access Space (2) (Even Byte Access) .................. 145 Figure 6.21 Bus Timing for 16-Bit, 2-State Access Space (3) (Odd Byte Access) ................... 145 Figure 6.22 Bus Timing for 16-Bit, 2-State Access Space (4) (Odd Byte Access) ................... 146 Figure 6.23 Bus Timing for 16-Bit, 2-State Access Space (5) (Word Access).......................... 147 Figure 6.24 Bus Timing for 16-Bit, 2-State Access Space (6) (Word Access).......................... 147 Figure 6.25 Bus Timing for 16-Bit, 3-State Access Space (1) (Even Byte Access) .................. 148 Figure 6.26 Bus Timing for 16-Bit, 3-State Access Space (2) (Odd Byte Access) ................... 149 Figure 6.27 Bus Timing for 16-Bit, 3-State Access Space (3) (Word Access).......................... 149 Figure 6.28 Example of Wait State Insertion Timing (Pin Wait Mode) .................................... 151 Figure 6.29 Example of Wait State Insertion Timing................................................................ 153 Figure 6.30 Access Timing Example in Burst ROM Space (AST = BRSTS1 = 1)................... 154 Figure 6.31 Access Timing Example in Burst ROM Space (AST = BRSTS1 = 0)................... 155 Figure 6.32 Examples of Idle Cycle Operation ......................................................................... 156 Section 7 Figure 7.1 Figure 7.2 Figure 7.3 Figure 7.4 Data Transfer Controller (DTC) Block Diagram of DTC ............................................................................................ 162 Block Diagram of DTC Activation Source Control ................................................. 174 DTC Register Information Location in Address Space ............................................ 175 DTC Operation Flowchart........................................................................................ 177
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Figure 7.5 Memory Mapping in Normal Mode ......................................................................... 178 Figure 7.6 Memory Mapping in Repeat Mode .......................................................................... 179 Figure 7.7 Memory Mapping in Block Transfer Mode ............................................................. 180 Figure 7.8 Chain Transfer Operation......................................................................................... 181 Figure 7.9 DTC Operation Timing (Example in Normal Mode or Repeat Mode) .................... 182 Figure 7.10 DTC Operation Timing (Example of Block Transfer Mode, with Block Size of 2).............................................................................................. 183 Figure 7.11 DTC Operation Timing (Example of Chain Transfer) ........................................... 183 Section 8 I/O Ports Figure 8.1 Noise Canceler Circuit ............................................................................................. 205 Figure 8.2 Noise Canceler Operation ........................................................................................ 206 Figure 8.3 Noise Canceler Circuit ............................................................................................. 212 Figure 8.4 Noise Canceler Operation ........................................................................................ 212 Figure 8.5 Noise Canceler Circuit ............................................................................................. 251 Figure 8.6 Noise Canceler Operation ........................................................................................ 252 Figure 8.7 Noise Canceler Circuit ............................................................................................. 288 Figure 8.8 Noise Canceler Operation ........................................................................................ 289 Figure 8.9 Noise Canceler Circuit ............................................................................................. 295 Figure 8.10 Noise Canceler Operation ...................................................................................... 295 Figure 8.11 Noise Canceler Circuit ........................................................................................... 335 Figure 8.12 Noise Canceler Operation ...................................................................................... 336 Section 9 Figure 9.1 Figure 9.2 Figure 9.3 Figure 9.4 Figure 9.5 Figure 9.6 Section 10 Figure 10.1 Figure 10.2 Figure 10.3 Figure 10.4 Figure 10.5 Figure 10.6 Figure 10.7 Figure 10.8 Figure 10.9 14-Bit PWM Timer (PWMX) PWMX (D/A) Block Diagram ................................................................................. 359 PWMX (D/A) Operation .......................................................................................... 367 Output Waveform (OS = 0, DADR corresponds to TL) ........................................... 370 Output Waveform (OS = 1, DADR corresponds to TH) ........................................... 371 D/A Data Register Configuration when CFS = 1 ..................................................... 371 Output Waveform when DADR = H'0207 (OS = 1) ................................................ 372 16-Bit Free-Running Timer (FRT) Block Diagram of 16-Bit Free-Running Timer ...................................................... 376 Increment Timing with Internal Clock Source ....................................................... 383 Timing of Output Compare A Output .................................................................... 383 Clearing of FRC by Compare-Match A Signal ...................................................... 384 Timing of Output Compare Flag (OCFA or OCFB) Setting .................................. 384 Timing of Overflow Flag (OVF) Setting................................................................ 385 OCRA Automatic Addition Timing ....................................................................... 386 Conflict between FRC Write and Clear.................................................................. 387 Conflict between FRC Write and Increment .......................................................... 388
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Figure 10.10 Conflict between OCR Write and Compare-Match (When Automatic Addition Function is Not Used).............................................. 389 Figure 10.11 Conflict between OCR Write and Compare-Match (When Automatic Addition Function is Used)..................................................... 390 Section 11 Figure 11.1 Figure 11.2 Figure 11.3 Figure 11.4 Figure 11.5 Figure 11.6 Figure 11.7 Figure 11.8 Figure 11.9 Section 12 Figure 12.1 Figure 12.2 Figure 12.3 Figure 12.4 Figure 12.5 Figure 12.6 Figure 12.7 Figure 12.8 8-Bit Timer (TMR) Block Diagram of 8-Bit Timer (TMR_0 and TMR_1)........................................... 394 Block Diagram of 8-Bit Timer (TMR_Y and TMR_X) ......................................... 395 Count Timing for Internal Clock Input................................................................... 406 Timing of CMF Setting at Compare-Match ........................................................... 406 Timing of Counter Clear by Compare-Match ........................................................ 407 Timing of OVF Flag Setting .................................................................................. 407 Conflict between TCNT Write and Counter Clear ................................................. 410 Conflict between TCNT Write and Increment ....................................................... 411 Conflict between TCOR Write and Compare-Match ............................................. 412 Watchdog Timer (WDT) Block Diagram of WDT ......................................................................................... 416 Watchdog Timer Mode (RST/NMI = 1) Operation................................................ 423 Interval Timer Mode Operation.............................................................................. 424 OVF Flag Set Timing ............................................................................................. 424 Output Timing of RESO signal .............................................................................. 425 Writing to TCNT and TCSR (WDT_0).................................................................. 427 Conflict between TCNT Write and Increment ....................................................... 428 Sample Circuit for Resetting the System by the RESO Signal............................... 429
Section 13 Serial Communication Interface (SCI) Figure 13.1 Block Diagram of SCI_1 and SCI_3 ...................................................................... 433 Figure 13.2 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits)................................................. 451 Figure 13.3 Receive Data Sampling Timing in Asynchronous Mode ....................................... 453 Figure 13.4 Relation between Output Clock and Transmit Data Phase (Asynchronous Mode)............................................................................................ 454 Figure 13.5 Sample SCI Initialization Flowchart ...................................................................... 455 Figure 13.6 Example of Operation in Transmission in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit) ................................................... 456 Figure 13.7 Sample Serial Transmission Flowchart .................................................................. 457 Figure 13.8 Example of SCI Operation in Reception (Example with 8-Bit Data, Parity, One Stop Bit) ................................................... 458 Figure 13.9 Sample Serial Reception Flowchart (1).................................................................. 460 Figure 13.9 Sample Serial Reception Flowchart (2).................................................................. 461
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Figure 13.10 Example of Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A) ......................................... 463 Figure 13.11 Sample Multiprocessor Serial Transmission Flowchart ....................................... 464 Figure 13.12 Example of SCI Operation in Reception (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)........................................................................ 465 Figure 13.13 Sample Multiprocessor Serial Reception Flowchart (1)....................................... 466 Figure 13.13 Sample Multiprocessor Serial Reception Flowchart (2)....................................... 467 Figure 13.14 Data Format in Synchronous Communication (LSB-First).................................. 468 Figure 13.15 Sample SCI Initialization Flowchart .................................................................... 469 Figure 13.16 Sample SCI Transmission Operation in Clock Synchronous Mode..................... 471 Figure 13.17 Sample Serial Transmission Flowchart ................................................................ 472 Figure 13.18 Example of SCI Receive Operation in Clock Synchronous Mode ....................... 473 Figure 13.19 Sample Serial Reception Flowchart ..................................................................... 474 Figure 13.20 Sample Flowchart of Simultaneous Serial Transmission and Reception ............. 476 Figure 13.21 Pin Connection for Smart Card Interface ............................................................. 477 Figure 13.22 Data Formats in Normal Smart Card Interface Mode .......................................... 478 Figure 13.23 Direct Convention (SDIR = SINV = O/E = 0) ..................................................... 478 Figure 13.24 Inverse Convention (SDIR = SINV = O/E = 1) ................................................... 478 Figure 13.25 Receive Data Sampling Timing in Smart Card Interface Mode (When Clock Frequency is 372 Times the Bit Rate) ............................................ 481 Figure 13.26 Data Re-transfer Operation in SCI Transmission Mode....................................... 483 Figure 13.27 TEND Flag Set Timings during Transmission ..................................................... 483 Figure 13.28 Sample Transmission Flowchart .......................................................................... 484 Figure 13.29 Data Re-transfer Operation in SCI Reception Mode............................................ 485 Figure 13.30 Sample Reception Flowchart................................................................................ 486 Figure 13.31 Clock Output Fixing Timing ................................................................................ 487 Figure 13.32 Clock Stop and Restart Procedure........................................................................ 488 Figure 13.33 Sample Transmission using DTC in Clock Synchronous Mode .......................... 492 Figure 13.34 Sample Flowchart for Mode Transition during Transmission.............................. 494 Figure 13.35 Pin States during Transmission in Asynchronous Mode (Internal Clock) ........... 494 Figure 13.36 Pin States during Transmission in Clock Synchronous Mode (Internal Clock) .................................................................................................... 495 Figure 13.37 Sample Flowchart for Mode Transition during Reception ................................... 496 Figure 13.38 Switching from SCK Pins to Port Pins................................................................. 497 Figure 13.39 Prevention of Low Pulse Output at Switching from SCK Pins to Port Pins......... 498 Section 14 Figure 14.1 Figure 14.2 Figure 14.3 Figure 14.4 CRC Operation Circuit (CRC) Block Diagram of CRC Operation Circuit ............................................................. 499 LSB-First Data Transmission ................................................................................. 501 MSB-First Data Transmission................................................................................ 502 LSB-First Data Reception ...................................................................................... 503
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Figure 14.5 MSB-First Data Reception ..................................................................................... 504 Figure 14.6 LSB-First and MSB-First Transmit Data ............................................................... 505 Section 15 Serial Communication Interface with FIFO (SCIF) Figure 15.1 Block Diagram of SCIF.......................................................................................... 508 Figure 15.2 Data Format in Serial Transmission/Reception (Example with 8-Bit Data, Parity and 2 Stop Bits) ................................................ 529 Figure 15.3 Example of Initialization Flowchart ....................................................................... 530 Figure 15.4 Example of Data Transmission Flowchart ............................................................. 531 Figure 15.5 Example of Data Reception Flowchart................................................................... 532 Figure 15.6 Example of Initialization Flowchart ....................................................................... 533 Figure 15.7 Example of Data Transmission/Reception Standby Flowchart .............................. 534 Figure 15.8 Example of Data Transmission Flowchart ............................................................. 535 Figure 15.9 Example of Data Transmission Suspension Flowchart .......................................... 536 Figure 15.10 Example of Data Reception Flowchart................................................................. 537 Figure 15.11 Example of Data Reception Suspension Flowchart.............................................. 538 Section 16 Figure 16.1 Figure 16.2 Figure 16.3 Figure 16.4 Figure 16.5 Serial Pin Multiplexed Modes Serial Pin Multiplexed Mode 0............................................................................... 547 Serial Pin Multiplexed Mode 1............................................................................... 548 Serial Pin Multiplexed Mode 2............................................................................... 549 Serial Pin Multiplexed Mode 3............................................................................... 550 Serial Pin Multiplexed Mode 4............................................................................... 551
Section 17 Synchronous Serial Communication Unit (SSU) Figure 17.1 Block Diagram of SSU........................................................................................... 554 Figure 17.2 Relationship of Clock Phase, Polarity, and Data.................................................... 566 Figure 17.3 Relationship between Data Input/Output Pins and the Shift Register .................... 567 Figure 17.4 Example of Initial Settings in SSU Mode .............................................................. 570 Figure 17.5 Example of Transmission Operation (SSU Mode)................................................. 572 Figure 17.6 Flowchart Example of Data Transmission (SSU Mode) ........................................ 573 Figure 17.7 Example of Reception Operation (SSU Mode) ...................................................... 575 Figure 17.8 Flowchart Example of Data Reception (SSU Mode) ............................................. 576 Figure 17.9 Flowchart Example of Simultaneous Transmission/Reception (SSU Mode)......... 577 Figure 17.10 Conflict Error Detection Timing (Before Transfer) ............................................. 578 Figure 17.11 Conflict Error Detection Timing (After Transfer End) ........................................ 578 Figure 17.12 Example of Initial Settings in Clock Synchronous Communication Mode .......... 579 Figure 17.13 Example of Transmission Operation (Clock Synchronous Communication Mode)......................................................................................... 580 Figure 17.14 Flowchart Example of Transmission Operation (Clock Synchronous Communication Mode)....................................................... 581
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Figure 17.15 Example of Reception Operation (Clock Synchronous Communication Mode)......................................................................................... 582 Figure 17.16 Flowchart Example of Data Reception (Clock Synchronous Communication Mode) ........................................................................................ 583 Figure 17.17 Flowchart Example of Simultaneous Transmission/Reception (Clock Synchronous Communication Mode)....................................................... 584 I2C Bus Interface (IIC) Block Diagram of I2C Bus Interface ...................................................................... 588 I2C Bus Interface Connections (Example: This LSI as Master) ............................. 589 I2C Bus Data Formats (I2C Bus Formats)............................................................... 619 I2C Bus Data Formats (Serial Formats) .................................................................. 619 I2C Bus Timing....................................................................................................... 620 Sample Flowchart for IIC Initialization ................................................................. 621 Sample Flowchart for Operations in Master Transmit Mode ................................. 622 Operation Timing Example in Master Transmit Mode (MLS = WAIT = 0).......... 624 Stop Condition Issuance Operation Timing Example in Master Transmit Mode (MLS = WAIT = 0)................................................................................................ 625 Figure 18.10 Sample Flowchart for Operations in Master Receive Mode (HNDS = 1)............ 626 Figure 18.11 Master Receive Mode Operation Timing Example (MLS = WAIT = 0, HNDS = 1) ........................................................................... 628 Figure 18.12 Stop Condition Issuance Timing Example in Master Receive Mode (MLS = WAIT = 0, HNDS = 1) ........................................................................... 628 Figure 18.13 Sample Flowchart for Operations in Master Receive Mode (receiving multiple bytes) (WAIT = 1) ................................................................ 629 Figure 18.14 Sample Flowchart for Operations in Master Receive Mode (receiving a single byte) (WAIT = 1)................................................................... 630 Figure 18.15 Master Receive Mode Operation Timing Example (MLS = ACKB = 0, WAIT = 1)........................................................................... 633 Figure 18.16 Stop Condition Issuance Timing Example in Master Receive Mode (MLS = ACKB = 0, WAIT = 1)........................................................................... 633 Figure 18.17 Sample Flowchart for Operations in Slave Receive Mode (HNDS = 1) .............. 635 Figure 18.18 Slave Receive Mode Operation Timing Example (1) (MLS = 0, HNDS= 1)....... 637 Figure 18.19 Slave Receive Mode Operation Timing Example (2) (MLS = 0, HNDS= 1)....... 637 Figure 18.20 Sample Flowchart for Operations in Slave Receive Mode (HNDS = 0) .............. 638 Figure 18.21 Slave Receive Mode Operation Timing Example (1) (MLS = ACKB = 0, HNDS = 0).......................................................................... 640 Figure 18.22 Slave Receive Mode Operation Timing Example (2) (MLS = ACKB = 0, HNDS = 0) .......................................................................... 641 Figure 18.23 Sample Flowchart for Slave Transmit Mode........................................................ 642 Figure 18.24 Slave Transmit Mode Operation Timing Example (MLS = 0)............................. 644 Section 18 Figure 18.1 Figure 18.2 Figure 18.3 Figure 18.4 Figure 18.5 Figure 18.6 Figure 18.7 Figure 18.8 Figure 18.9
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Figure 18.25 Figure 18.26 Figure 18.27 Figure 18.28 Figure 18.29 Figure 18.30 Figure 18.31 Figure 18.32 Figure 18.33 Figure 18.34 Figure 18.35
IRIC Setting Timing and SCL Control (1) ........................................................... 645 IRIC Setting Timing and SCL Control (2) ........................................................... 646 IRIC Setting Timing and SCL Control (3) ........................................................... 647 Block Diagram of Noise Canceler........................................................................ 650 Notes on Reading Master Receive Data ............................................................... 658 Flowchart for Start Condition Issuance Instruction for Retransmission and Timing ............................................................................ 659 Stop Condition Issuance Timing .......................................................................... 660 IRIC Flag Clearing Timing When WAIT = 1 ...................................................... 661 ICDR Register Read and ICCR Register Access Timing in Slave Transmit Mode ........................................................................................... 662 TRS Bit Set Timing in Slave Mode...................................................................... 663 Diagram of Erroneous Operation when Arbitration Lost ..................................... 665
Section 19 LPC Interface (LPC) Figure 19.1 Block Diagram of LPC........................................................................................... 669 Figure 19.2 Typical LFRAME Timing...................................................................................... 737 Figure 19.3 Abort Mechanism ................................................................................................... 737 Figure 19.4 SMIC Write Transfer Flow .................................................................................... 738 Figure 19.5 SMIC Read Transfer Flow ..................................................................................... 739 Figure 19.6 BT Write Transfer Flow ......................................................................................... 740 Figure 19.7 BT Read Transfer Flow.......................................................................................... 741 Figure 19.8 GA20 Output .......................................................................................................... 743 Figure 19.9 Power-Down State Termination Timing ................................................................ 748 Figure 19.10 SERIRQ Timing ................................................................................................... 749 Figure 19.11 Clock Start Request Timing ................................................................................. 751 Figure 19.12 HIRQ Flowchart (Example of Channel 1)............................................................ 755 Section 20 LPC Interface (LPC) Figure 20.1 Configuration of EtherC......................................................................................... 760 Figure 20.2 EtherC Transmitter State Transitions ..................................................................... 779 Figure 20.3 EtherC Receiver State Transmissions .................................................................... 781 Figure 20.4 RMII Frame Transmit Timing (Normal Transmission).......................................... 782 Figure 20.5 RMII Frame Receive Timing (Normal Reception) ................................................ 782 Figure 20.6 RMII Frame Receive Timing (Reception with False Carrier) ................................ 783 Figure 20.7 MII Management Frame Format ............................................................................ 784 Figure 20.8 1-Bit Data Write Flowchart .................................................................................... 785 Figure 20.9 Bus Release Flowchart (TA in Read in Figure 20.7).............................................. 785 Figure 20.10 1-Bit Data Read Flowchart................................................................................... 786 Figure 20.11 Independent Bus Release Flowchart (IDLE in Write in Figure 20.7) .................. 786 Figure 20.12 Changing IPG and Transmission Efficiency ........................................................ 788
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Section 21 Figure 21.1 Figure 21.2 Figure 21.3 Figure 21.4 Figure 21.5 Figure 21.6 Figure 21.7
Ethernet Controller Direct Memory Access Controller (E-DMAC) Configuration of E-DMAC, and Descriptors and Buffers...................................... 794 Relationship between Transmit Descriptor and Transmit Buffer ........................... 818 Relationship between Receive Descriptor and Receive Buffer .............................. 822 Sample Transmission Flowchart ............................................................................ 828 Sample Reception Flowchart.................................................................................. 830 E-DMAC Operation after Transmit Error .............................................................. 831 E-DMAC Operation after Receive Error................................................................ 832
Section 22 USB Function Module (USB) Figure 22.1 Block Diagram of USB .......................................................................................... 834 Figure 22.2 Operation at Cable Connection .............................................................................. 865 Figure 22.3 Operation at Cable Disconnection.......................................................................... 866 Figure 22.4 Suspend Operation ................................................................................................. 867 Figure 22.5 Resume Operation from Up-Stream....................................................................... 868 Figure 22.6 Flow of Transition to and Canceling Software Standby Mode .............................. 869 Figure 22.7 Timing of Transition to and Canceling Software Standby Mode........................... 870 Figure 22.8 Remote-Wakeup..................................................................................................... 871 Figure 22.9 Transfer Stages in Control Transfer ....................................................................... 872 Figure 22.10 Setup Stage Operation .......................................................................................... 873 Figure 22.11 Data Stage (Control-In) Operation ....................................................................... 874 Figure 22.12 Data Stage (Control-Out) Operation .................................................................... 875 Figure 22.13 Status Stage (Control-In) Operation ..................................................................... 876 Figure 22.14 Status Stage (Control-Out) Operation .................................................................. 877 Figure 22.15 EP1 Bulk-Out Transfer Operation........................................................................ 878 Figure 22.16 EP2 Bulk-In Transfer Operation .......................................................................... 879 Figure 22.17 Operation of EP3 Interrupt-In Transfer ................................................................ 881 Figure 22.18 Forcible Stall by Application ............................................................................... 884 Figure 22.19 Automatic Stall by USB Function Module........................................................... 885 Figure 22.20 RDFN Bit Operation for EP1 ............................................................................... 887 Figure 22.21 PKTE Bit Operation for EP2................................................................................ 888 Figure 22.22 Example of Circuitry in Self-Powered Mode ....................................................... 891 Figure 22.23 TR Interrupt Flag Set Timing ............................................................................... 893 Section 23 A/D Converter Figure 23.1 Block Diagram of the A/D Converter .................................................................... 896 Figure 23.2 Example of A/D Converter Operation (When Channel 1 is Selected in Single Mode) ....................................................................................... 903 Figure 23.3 Example of A/D Converter Operation (When Channels AN0 to AN3 are Selected in Scan Mode).......................................................................................... 904 Figure 23.4 A/D Conversion Timing......................................................................................... 906
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Figure 23.5 Timing of External Trigger Input ........................................................................... 908 Figure 23.6 A/D Conversion Accuracy Definitions................................................................... 910 Figure 23.7 A/D Conversion Accuracy Definitions................................................................... 910 Figure 23.8 Example of Analog Input Circuit ........................................................................... 911 Figure 23.9 Example of Analog Input Protection Circuit .......................................................... 913 Figure 23.10 Analog Input Pin Equivalent Circuit .................................................................... 914 Section 25 Flash Memory Figure 25.1 Block Diagram of Flash Memory........................................................................... 918 Figure 25.2 Mode Transition of Flash Memory......................................................................... 919 Figure 25.3 Flash Memory Configuration ................................................................................. 921 Figure 25.4 Block Division of User MAT ................................................................................. 922 Figure 25.5 Overview of User Procedure Program.................................................................... 923 Figure 25.6 System Configuration in Boot Mode...................................................................... 948 Figure 25.7 Automatic-Bit-Rate Adjustment Operation of SCI ................................................ 949 Figure 25.8 Overview of Boot Mode State Transition Diagram................................................ 951 Figure 25.9 System Configuration in USB Boot Mode ............................................................. 952 Figure 25.10 USB Boot Mode State Transition Diagram.......................................................... 954 Figure 25.11 Programming/Erasing Overview Flow................................................................. 956 Figure 25.12 RAM Map When Programming/Erasing is Executed .......................................... 957 Figure 25.13 Programming Procedure....................................................................................... 958 Figure 25.14 Erasing Procedure................................................................................................. 963 Figure 25.15 Repeating Procedure of Erasing and Programming.............................................. 965 Figure 25.16 Procedure for Programming User MAT in User Boot Mode ............................... 968 Figure 25.17 Procedure for Erasing User MAT in User Boot Mode ......................................... 970 Figure 25.18 Transitions to Error-Protection State.................................................................... 985 Figure 25.19 Switching between the User MAT and User Boot MAT...................................... 986 Figure 25.20 Boot Program States.............................................................................................989 Figure 25.21 Bit-Rate-Adjustment Sequence ............................................................................ 990 Figure 25.22 Communication Protocol Format ......................................................................... 991 Figure 25.23 New Bit-Rate Selection Sequence...................................................................... 1002 Figure 25.24 Programming Sequence...................................................................................... 1006 Figure 25.25 Erasure Sequence ............................................................................................... 1009 Section 26 Figure 26.1 Figure 26.2 Figure 26.3 Figure 26.4 Figure 26.5 Boundary Scan (JTAG) JTAG Block Diagram........................................................................................... 1020 TAP Controller State Transitions ......................................................................... 1043 Reset Signal Circuit Without Reset Signal Interference....................................... 1047 Serial Data Input/Output (1)................................................................................. 1048 Serial Data Input/Output (2)................................................................................. 1049
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Section 27 Figure 27.1 Figure 27.2 Figure 27.3 Figure 27.4 Figure 27.5 Section 28 Figure 28.1 Figure 28.2 Figure 28.3 Figure 28.4
Clock Pulse Generator Block Diagram of Clock Pulse Generator ............................................................ 1051 Typical Connection to Crystal Resonator............................................................. 1052 Equivalent Circuit of Crystal Resonator............................................................... 1052 Example of External Clock Input ......................................................................... 1053 Note on Board Design of Oscillation Circuit Section .......................................... 1056 Power-Down Modes Mode Transition Diagram .................................................................................... 1065 Medium-Speed Mode Timing .............................................................................. 1068 Software Standby Mode Application Example .................................................... 1070 Hardware Standby Mode Timing ......................................................................... 1071
Section 31 Electrical Characteristics Figure 31.1 Darlington Transistor Drive Circuit (Example).................................................... 1125 Figure 31.2 LED Drive Circuit (Example) .............................................................................. 1126 Figure 31.3 Output Load Circuit ............................................................................................. 1127 Figure 31.4 System Clock Timing........................................................................................... 1129 Figure 31.5 Oscillation Stabilization Timing .......................................................................... 1129 Figure 31.6 Oscillation Stabilization Timing (Exiting Software Standby Mode).................... 1129 Figure 31.7 External Clock Input Timing................................................................................ 1130 Figure 31.8 Timing of External Clock Output Stabilization Delay Time................................ 1130 Figure 31.9 Subclock Input Timing......................................................................................... 1131 Figure 31.10 Reset Input Timing............................................................................................. 1132 Figure 31.11 Interrupt Input Timing........................................................................................ 1133 Figure 31.12 Basic Bus Timing/2-State Access ...................................................................... 1135 Figure 31.13 Basic Bus Timing/3-State Access ...................................................................... 1136 Figure 31.14 Basic Bus Timing/3-State Access with One Wait State ..................................... 1137 Figure 31.15 Even Byte Access (ADMXE = 0) ...................................................................... 1138 Figure 31.16 Odd Byte Access (ADMXE = 0)........................................................................ 1139 Figure 31.17 Word Access (ADMXE = 0) .............................................................................. 1140 Figure 31.18 Burst ROM Access Timing/2-State Access........................................................ 1141 Figure 31.19 Burst ROM Access Timing/1-State Access........................................................ 1142 Figure 31.20 Multiplex Bus Timing/Data 2-State Access ....................................................... 1144 Figure 31.21 Multiplex Bus Timing/Data 3-State Access ....................................................... 1145 Figure 31.22 I/O Port Input/Output Timing............................................................................. 1149 Figure 31.23 PWMX Output Timing....................................................................................... 1149 Figure 31.24 SCK Clock Input Timing ................................................................................... 1149 Figure 31.25 SCI Input/Output Timing (Clock Synchronous Mode) ...................................... 1149 Figure 31.26 A/D Converter External Trigger Input Timing................................................... 1150 Figure 31.27 WDT Output Timing (RESO) ............................................................................ 1150
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Figure 31.28 Figure 31.29 Figure 31.30 Figure 31.31 Figure 31.32 Figure 31.33 Figure 31.34 Figure 31.35 Figure 31.36 Figure 31.37 Figure 31.38 Figure 31.39 Figure 31.40 Figure 31.41 Figure 31.42 Figure 31.43 Figure 31.44 Figure 31.45 Figure 31.46
SSU Timing (Master, CPHS = 1) ....................................................................... 1150 SSU Timing (Master, CPHS = 0) ....................................................................... 1151 SSU Timing (Slave, CPHS = 1) ......................................................................... 1151 SSU Timing (Slave, CPHS = 0) ......................................................................... 1152 I2C Bus Interface Input/Output Timing .............................................................. 1154 LPC Interface (LPC) Timing.............................................................................. 1155 Timing of RM_REF-CLK and RMII Signals..................................................... 1156 RMII Transmit Timing ....................................................................................... 1157 RMII Receive Timing (Normal Operation)........................................................ 1157 RMII Receive Timing (When an Error is Detected) .......................................... 1157 MDIO Input Timing ........................................................................................... 1158 MDIO Output Timing ........................................................................................ 1158 WOL Output Timing .......................................................................................... 1158 Data Signal Timing ............................................................................................ 1160 Load Condition................................................................................................... 1160 JTAG ETCK Timing .......................................................................................... 1161 Reset Hold Timing ............................................................................................. 1162 JTAG Input/Output Timing................................................................................ 1162 Connecting Capacitors to VCC and VCL Pins................................................... 1165
Appendix Figure C.1 Package Dimensions (PLBGA0176GA-A) ........................................................... 1171 Figure C.2 Package Dimensions (PLQP0144KA-A)............................................................... 1172 Figure C.3 Package Dimensions (PTQP0144LC-A) ............................................................... 1173
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Tables
Section 1 Overview Table 1.1 Pin Assignments in Each Operating Mode..................................................................... 7 Table 1.2 Pin Functions................................................................................................................ 14 Section 2 Table 2.1 Table 2.2 Table 2.3 Table 2.4 Table 2.4 Table 2.5 Table 2.6 Table 2.7 Table 2.7 Table 2.8 Table 2.9 Table 2.10 Table 2.11 Table 2.12 Table 2.13 Table 2.13 CPU Instruction Classification ............................................................................................. 41 Operation Notation....................................................................................................... 42 Data Transfer Instructions............................................................................................ 43 Arithmetic Operations Instructions (1)......................................................................... 44 Arithmetic Operations Instructions (2)......................................................................... 45 Logic Operations Instructions ...................................................................................... 46 Shift Instructions .......................................................................................................... 46 Bit Manipulation Instructions (1) ................................................................................. 47 Bit Manipulation Instructions (2) ................................................................................. 48 Branch Instructions ...................................................................................................... 49 System Control Instructions ......................................................................................... 50 Block Data Transfer Instructions ............................................................................... 51 Addressing Modes...................................................................................................... 53 Absolute Address Access Ranges .............................................................................. 55 Effective Address Calculation (1) .............................................................................. 57 Effective Address Calculation (2) .............................................................................. 58
Section 3 MCU Operating Modes Table 3.1 MCU Operating Mode Selection.................................................................................. 63 Section 4 Table 4.1 Table 4.2 Table 4.3 Section 5 Table 5.1 Table 5.2 Table 5.3 Table 5.4 Table 5.5 Table 5.6 Table 5.7 Table 5.8 Exception Handling Exception Types and Priority....................................................................................... 71 Exception Handling Vector Table................................................................................ 72 Status of CCR after Trap Instruction Exception Handling........................................... 76 Interrupt Controller Pin Configuration ......................................................................................................... 80 Correspondence between Interrupt Source and ICR .................................................... 82 Interrupt Sources, Vector Addresses, and Interrupt Priorities...................................... 90 Interrupt Control Modes............................................................................................... 93 Interrupts Selected in Each Interrupt Control Mode .................................................... 94 Operations and Control Signal Functions in Each Interrupt Control Mode ................. 95 Interrupt Response Times .......................................................................................... 101 Number of States in Interrupt Handling Routine Execution Status............................ 101
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Table 5.9 Interrupt Source Selection and Clearing Control ....................................................... 103 Section 6 Table 6.1 Table 6.2 Table 6.3 Table 6.4 Table 6.5 Table 6.6 Table 6.7 Table 6.8 Table 6.9 Table 6.10 Table 6.11 Table 6.12 Table 6.13 Table 6.14 Table 6.15 Section 7 Table 7.1 Table 7.2 Table 7.3 Table 7.4 Table 7.5 Table 7.6 Table 7.7 Table 7.8 Table 7.9 Section 8 Table 8.1 Table 8.2 Table 8.3 Table 8.4 Table 8.5 Table 8.6 Table 8.7 Table 8.8 Bus Controller (BSC) Pin Configuration....................................................................................................... 110 Address Ranges and External Address Spaces........................................................... 119 Bit Settings and Bus Specifications of Basic Bus Interface ....................................... 120 Bus Specifications for Basic Extended Area/Basic Bus Interface ............................. 120 Bus Specifications for 256-Kbyte Extended Area/Basic Bus Interface ..................... 121 Address-Data Multiplex Address Spaces ................................................................... 123 Bit Settings and Bus Specifications of Basic Bus Interface ....................................... 124 Bus Specifications for IOS Extended Area/Multiplex Bus Interface (Address Cycle) ......................................................................................................... 124 Bus Specifications for IOS Extended Area/Multiplex Bus Interface (Data Cycle).... 124 Bus Specifications for 256-Kbyte Extended Area/Multiplex Bus Interface (Address Cycle) ....................................................................................................... 125 Bus Specifications for 256-Kbyte Extended Area/Multiplex Bus Interface (Data Cycle)............................................................................................................. 125 Address Range for IOS Signal Output ..................................................................... 126 Data Buses Used and Valid Strobes......................................................................... 129 Data Buses Used and Valid Strobes (Gluless Extension) ........................................ 130 Pin States in Idle Cycle ............................................................................................ 157 Data Transfer Controller (DTC) Correspondence between Interrupt Sources and DTCER .......................................... 167 DTC Event Counter Conditions ................................................................................. 171 Flag Status/Address Code .......................................................................................... 172 Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs.................... 176 Register Functions in Normal Mode .......................................................................... 178 Register Functions in Repeat Mode ........................................................................... 179 Register Functions in Block Transfer Mode .............................................................. 180 DTC Execution Status................................................................................................ 184 Number of States Required for Each Execution Status.............................................. 184 I/O Ports Port Functions ............................................................................................................ 190 Port 1 Input Pull-Up MOS States............................................................................... 196 Port 2 Input Pull-Up MOS States............................................................................... 201 Port 3 Input Pull-Up MOS States............................................................................... 207 Port 4 Input Pull-Up MOS States............................................................................... 215 Port 6 Input Pull-Up MOS States............................................................................... 226 Input Pull-Up MOS States ......................................................................................... 247 Port D Input Pull-Up MOS States .............................................................................. 263
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Table 8.9 Table 8.10 Table 8.11 Table 8.12 Table 8.13 Table 8.14 Table 8.15 Table 8.16 Section 9 Table 9.1 Table 9.2 Table 9.3 Table 9.4
Port Functions ............................................................................................................ 273 Port 1 Input Pull-Up MOS States ............................................................................. 279 Port 2 Input Pull-Up MOS States ............................................................................. 284 Port 3 Input Pull-Up MOS States ............................................................................. 290 Port 4 Input Pull-Up MOS States ............................................................................. 298 Port 6 Input Pull-Up MOS States ............................................................................. 310 Input Pull-Up MOS States........................................................................................ 331 Port D Input Pull-Up MOS States ............................................................................ 347 14-Bit PWM Timer (PWMX) Pin Configuration ....................................................................................................... 360 Clock Select of PWMX_1 and PWMX_0.................................................................. 365 Settings and Operation (Examples when = 34 MHz).............................................. 368 Locations of Additional Pulses Added to Base Pulse (When CFS = 1) ..................... 373
Section 10 16-Bit Free-Running Timer (FRT) FRT Interrupt Sources........................................................................................... 386 Table 10.1 Table 10.2 Switching of Internal Clock and FRC Operation .................................................. 391 Section 11 8-Bit Timer (TMR) Table 11.1 (1) Clock Input to TCNT and Count Condition (TMR_0) ....................................... 399 Table 11.1 (2) Clock Input to TCNT and Count Condition (TMR_1) ....................................... 400 Table 11.1 (3) Clock Input to TCNT and Count Condition (TMR_X, TMR_Y)....................... 400 Table 11.2 Registers Accessible by TMR_X/TMR_Y............................................................... 405 Table 11.3 Interrupt Sources of 8-Bit Timers TMR_0, TMR_1, TMR_Y, and TMR_X........... 409 Table 11.4 Switching of Internal Clocks and TCNT Operation................................................. 413 Section 12 Watchdog Timer (WDT) Table 12.1 Pin Configuration ..................................................................................................... 417 Table 12.2 WDT Interrupt Source.............................................................................................. 426 Section 13 Table 13.1 Table 13.2 Table 13.3 Table 13.4 Table 13.5 Table 13.6 Table 13.7 Table 13.8 Serial Communication Interface (SCI) Pin Configuration ..................................................................................................... 434 Relationships between N Setting in BRR and Bit Rate B ........................................ 447 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) ............... 448 Maximum Bit Rate for Each Frequency (Asynchronous Mode).............................. 448 Maximum Bit Rate with External Clock Input (Asynchronous Mode).................... 448 BRR Settings for Various Bit Rates (Clock Synchronous Mode)............................ 449 Maximum Bit Rate with External Clock Input (Clock Synchronous Mode) ........... 450 BRR Settings for Various Bit Rates (Smart Card Interface Mode, n = 0, s = 372) .................................................................................................................... 450 Table 13.9 Maximum Bit Rate for Each Frequency (Smart Card Interface Mode, S = 372) ..... 450 Table 13.10 Serial Transfer Formats (Asynchronous Mode) ..................................................... 452
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Table 13.11 SSR Status Flags and Receive Data Handling ....................................................... 459 Table 13.12 SCI Interrupt Sources............................................................................................. 489 Table 13.13 SCI Interrupt Sources............................................................................................. 490 Section 15 Table 15.1 Table 15.2 Table 15.3 Table 15.4 Table 15.5 Table 15.6 Table 15.7 Table 15.8 Table 15.9 Serial Communication Interface with FIFO (SCIF) Pin Configuration..................................................................................................... 509 Register Access ........................................................................................................ 510 Interrupt Control Function ....................................................................................... 515 SCIF Output Setting................................................................................................. 527 Example of Baud Rate Settings................................................................................ 528 Correspondence Between LPC Interface I/O Address and the SCIF Registers ....... 539 Register States.......................................................................................................... 540 Interrupt Sources ...................................................................................................... 541 Interrupt Source, Vector Address, and Interrupt Priority ......................................... 541
Section 16 Serial Pin Multiplexed Modes Table 16.1 Pin Configuration..................................................................................................... 544 Section 17 Table 17.1 Table 17.2 Table 17.3 Table 17.4 Table 17.5 Section 18 Table 18.1 Table 18.2 Table 18.3 Table 18.3 Table 18.4 Table 18.5 Table 18.6 Table 18.7 Table 18.8 Table 18.9 Table 18.10 Table 18.11 Table 18.12 Table 18.13 Synchronous Serial Communication Unit (SSU) Pin Configuration..................................................................................................... 555 Communication Modes and Pin States of SSI and SSO Pins................................... 568 Communication Modes and Pin States of SSCK Pin ............................................... 569 Communication Modes and Pin States of SCS Pin .................................................. 569 Interrupt Sources ...................................................................................................... 585 I2C Bus Interface (IIC) Pin Configuration..................................................................................................... 590 Transfer Format........................................................................................................ 594 I2C bus Transfer Rate (1) ......................................................................................... 598 I2C bus Transfer Rate (2) ......................................................................................... 599 Flags and Transfer States (Master Mode) ................................................................ 606 Flags and Transfer States (Slave Mode)................................................................... 607 Output Data Hold Time............................................................................................ 618 ISCMBCR Setting.................................................................................................... 618 I2C Bus Data Format Symbols ................................................................................. 620 Examples of Operation Using the DTC ................................................................... 649 IIC Interrupt Source ............................................................................................... 652 I2C Bus Timing (SCL and SDA Outputs) .............................................................. 653 Permissible SCL Rise Time (tsr) Values................................................................. 654 I2C Bus Timing (with Maximum Influence of tSr/tSf) ............................................. 656
Section 19 LPC Interface (LPC) Table 19.1 Pin Configuration..................................................................................................... 670
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Table 19.2 Table 19.3 Table 19.4 Table 19.5 Table 19.6 Table 19.7 Table 19.8 Table 19.9 Table 19.10 Table 19.11 Table 19.12 Table 19.13 Table 19.14
LADR1, LADR2 Initial Values ............................................................................... 686 Host Register Selection ............................................................................................ 687 Slave Selection Internal Registers............................................................................ 687 LPC I/O Cycle.......................................................................................................... 736 GA20 Setting/Clearing Timing ................................................................................ 742 Fast Gate A20 Output Signals.................................................................................. 744 Scope of LPC Interface Pin Shutdown..................................................................... 746 Scope of Initialization in Each LPC interface Mode................................................ 747 Serialized Interrupt Transfer Cycle Frame Configuration...................................... 750 Receive Complete Interrupts and Error Interrupt ................................................... 752 HIRQ Setting and Clearing Conditions when LPC Channels are Used ................. 754 HIRQ Setting and Clearing Conditions when SCIF Channels are Used ................ 755 Host Address Example ........................................................................................... 757
Section 20 Ethernet Controller (EtherC) Table 20.1 Pin Configuration ..................................................................................................... 761 Section 22 Table 22.1 Table 22.2 Table 22.3 Table 22.4 Table 22.5 Table 22.6 Table 22.7 Table 22.8 Section 23 Table 23.1 Table 23.2 Table 23.3 Table 23.4 Table 23.5 Table 23.6 Section 25 Table 25.1 Table 25.2 Table 25.3 Table 25.4 Table 25.5 Table 25.6 USB Function Module (USB) Pin Configuration ..................................................................................................... 834 Example of Limitations for Setting Values .............................................................. 858 Example of Setting ................................................................................................... 859 Relationship between TRNTREG0 Setting and Pin Output..................................... 861 Relationship between Pin Input and TRNTREG1 Monitoring Value ...................... 862 Interrupt Sources ...................................................................................................... 863 Command Decoding on Application Side................................................................ 882 Selection of Peripheral Module Clock () when USB Connection is Made ............ 894 A/D Converter Pin Configuration ..................................................................................................... 897 Analog Input Channels and Corresponding ADDR Registers ................................. 899 A/D Conversion Characteristics (Single Mode)....................................................... 907 A/D Conversion Characteristics (Scan Mode) ......................................................... 907 A/D Converter Interrupt Source ............................................................................... 909 Standard of Analog Pins........................................................................................... 913 Flash Memory Comparison of Programming Modes ....................................................................... 920 Pin Configuration ..................................................................................................... 925 Register/Parameter and Target Mode....................................................................... 927 Parameters and Target Modes .................................................................................. 937 Setting On-Board Programming Mode .................................................................... 947 System Clock Frequency for Automatic-Bit-Rate Adjustment by This LSI ............ 949
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Table 25.7 Enumeration Information ......................................................................................... 953 Table 25.8 Executable MAT ...................................................................................................... 973 Table 25.9 (1) Useable Area for Programming in User Program Mode .................................... 974 Table 25.9 (2) Useable Area for Erasure in User Program Mode .............................................. 976 Table 25.9 (3) Useable Area for Programming in User Boot Mode .......................................... 978 Table 25.9 (4) Useable Area for Erasure in User Boot Mode .................................................... 980 Table 25.10 Hardware Protection .............................................................................................. 983 Table 25.11 Software Protection................................................................................................ 984 Table 25.12 Inquiry and Selection Commands .......................................................................... 992 Table 25.13 Programming/Erasing Command ......................................................................... 1005 Table 25.14 Status Code .......................................................................................................... 1014 Table 25.15 Error Code............................................................................................................ 1015 Section 26 Table 26.1 Table 26.2 Table 26.3 Boundary Scan (JTAG) Pin Configuration................................................................................................... 1021 JTAG Register Serial Transfer............................................................................... 1022 Correspondence between Pins and Boundary Scan Register (H8S/2472 Group) ................................................................................................. 1025 Table 26.4 Correspondence between Pins and Boundary Scan Register (H8S/2462 Group and H8S/2463 Group) .............................................................. 1034 Clock Pulse Generator Damping Resistance Values................................................................................... 1052 Crystal Resonator Parameters ................................................................................ 1053 Ranges of Multiplied Clock Frequency ................................................................. 1054
Section 27 Table 27.1 Table 27.2 Table 27.3
Section 28 Power-Down Modes Table 28.1 Operating Frequency and Wait Time ..................................................................... 1060 Table 28.2 LSI Internal States in Each Mode .......................................................................... 1066 Section 31 Table 31.1 Table 31.2 Table 31.2 Table 31.3 Table 31.4 Table 31.5 Table 31.6 Table 31.7 Table 31.8 Table 31.9 Table 31.10 Electrical Characteristics Absolute Maximum Ratings .................................................................................. 1121 DC Characteristics (1)............................................................................................ 1122 DC Characteristics (2)............................................................................................ 1124 Permissible Output Currents .................................................................................. 1125 Clock Timing ......................................................................................................... 1127 External Clock Input Conditions............................................................................ 1128 Subclock Input Conditions..................................................................................... 1128 Control Signal Timing ........................................................................................... 1132 Bus Timing............................................................................................................. 1134 Multiplex Bus Timing ............................................................................................ 1143 Timing of On-Chip Peripheral Modules .............................................................. 1147
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Table 31.11 Table 31.12 Table 31.13 Table 31.14 Table 31.15
Timing of On-Chip Peripheral Modules (2)......................................................... 1148 I2C Bus Timing .................................................................................................... 1153 LPC Module Timing ............................................................................................ 1154 Ethernet Controller Signal Timing ....................................................................... 1156 USB Characteristics when On-Chip USB Transceiver is Used (USD+, USD- pin characteristics)....................................................................... 1159 Table 31.16 JTAG Timing ....................................................................................................... 1161 Table 31.17 A/D Conversion Characteristics (AN7 to AN0 Input: 80/160-State Conversion) ................................................... 1163 Table 31.18 Flash Memory Characteristics.............................................................................. 1164 Appendix Table A.1 I/O Port States in Each Processing State ................................................................. 1167
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Rev. 2.00 Aug. 20, 2008 Page xlviii of xlviii
Section 1 Overview
Section 1 Overview
1.1 Overview
* High-speed H8S/2600 central processing unit with an internal 16-bit architecture Upward-compatible with H8/300 and H8/300H CPUs on an object level Sixteen 16-bit general registers 69 basic instructions Multiplication and accumulation instructions * Various peripheral functions Data transfer controller (DTC) 14-bit PWM timer (PWMX) 16-bit free-running timer (FRT) 8-bit timer (TMR) Watchdog timer (WDT) Asynchronous or synchronous serial communication interface (SCI) CRC operation circuit (CRC) Serial communication interface with FIFO (SCIF) Synchronous serial communication unit (SSU) I C bus interface (IIC) LPC interface (LPC) Ethernet controller (EtherC) Direct memory access controller for Ethernet controller (E-DMAC) USB function module (USB)* 10-bit A/D converter Platform Environment Control Interface (PECI)* Boundary scan (JTAG) Clock pulse generator Notes: 1. Supported only by the H8S/2472 Group. 2. Supported only by the H8S/2472 Group and the H8S/2462 Group.
2 1 2
Rev. 2.00 Aug. 20, 2008 Page 1 of 1198 REJ09B0403-0200
Section 1 Overview
* On-chip memory
ROM Type Flash memory Version Model R4F2472 R4F2463 ROM 512 Kbytes 512 Kbytes RAM 40 Kbytes 40 Kbytes Remarks 176 pins, USB incorporated 144 pins, USB and PECI not incorporated 144 pins, USB not incorporated
R4F2462
512 Kbytes
40 Kbytes
* Reprogramming count: 1000 times (Tpy.) * General I/O ports I/O pins: 110 (for 176-pin), 106 (for 144-pin) Input-only pins: 9 * Supports various power-down states * Compact package
Package (code) PLBG0176GA-A PTQP0144LC-A PLQP0144KA-A Body Size 13 x 13 mm 16 x 16 mm 20 x 20 mm Pin Pitch 0.8 mm 0.4 mm 0.5 mm
Rev. 2.00 Aug. 20, 2008 Page 2 of 1198 REJ09B0403-0200
Section 1 Overview
1.2
Block Diagram
ROM (Flash) 512K (+16K UB)
Clock pulse generator
DTC
H8S/2600 CPU
RAM 40K
Port 1
LPC
EtherC E-DMAC
WDT x 2
EVC
Interrupt controller
Bus controller
14-bit PWM x 4 A/D converter
SCI_1, SCI_3
JTAG
8-bit timer x 4
SCIF
Port 5
SSU
CRC calculator
FRT
Port 6
USB* 1 PECI* 2
Port A
IIC_0 to IIC_5
Port 7
[Legend] CPU: DTC: EVC: SCI: SCIF: IIC: EtherC: E-DMAC: SSU: USB: FRT: PWM: LPC: WDT: JTAG: PECI:
Port 8
Port 9
Central processing unit Data transfer controller Event counter Serial communication interface Serial communication interface with FIFO I2C bus interface Ethernet controller Direct memory access controller for Ethernet controller Synchronous serial communication unit USB function module 16-bit free running timer 14-bit PWM timer LPC interface Watchdog timer Boundary scan PECI interface
Notes: 1. Supported only by the H8S/2472 Group. 2. Supported only by the H8S/2472 Group and the H8S/2462 Group.
Figure 1.1 Internal Block Diagram
Rev. 2.00 Aug. 20, 2008 Page 3 of 1198 REJ09B0403-0200
Port B
Port C
Port 4
Port D
Port 3
Port E
Port 2
Port F
Section 1 Overview
1.3
1.3.1
Pin Description
Pin Assignments
A B C D E F G H J K L M N P R
15
P11
P13
P16
P21
P24
P27
PF1
ETDI
PUPDPLS
USD-
P67
P64
P61
AVCC
P76
15
14
P10
P12
P14
P20
P23
P26
PF0
ETCK
VBUS
USD+
P66
P62
AVref
P75
P74
14
13
PB5
PB7
VSS
P17
P25
VSS
PF2
ETD0
DrVSS
DrVCC
P65
P60
P77
P73
P71
13
12
PB2
PB4
PB6
P15
P22
NC
ETRST
ETMS
NC
VCC
P63
P72
P70
AVSS
NC
12
11
VCC
PB0
PB1
PB3
PD0
PD3
PD1
PD2
11
10
P32
P33
P31
P30
PD7
PD6
PD4
PD5
10
9
P36
P37
P35
P34
PE2
PE1
VCC
PE0
9
8
P42
P43
P41
P40
H8S/2472 Group PLBG0176GA-A BP-176V (Top view)
PE6
PE5
PE3
PE4
8
7
P52
P53
PECI
PEVref
P80
NC
NC
PE7
7
6
P55
P44
P54
FWE
P84
P83
P81
P82
6
5
UXTAL UEXTAL
VCC
UXSEL
UXSEL
F
PEVref
P34
P30
PB3
VSS
P87
P86
P85
5
4
PF5
PF4
NC
PF3
RES
NC
P50
P94
P91
PC6
PC1
PA5
NC
NC
NC
4
3
VSS
RESO
P45
P56
PF6
VCL
P97
P93
P90
PC5
NC
PA7
PA2
PA1
PA0
3
2
XTAL
EXTAL
P47
VSS
NMI
P51
P95
P92
PC7
PC3
NC
PC0
VCC
PA3
NC
2
1
VCC A
P46 B
P57 C
MD1 D
STBY E
MD2 F
P96 G
NC H
NC J
PC4 K
PC2 L
NC M
PA6 N
PA4 P
NC R
1
: NC pin
Figure 1.2 Pin Assignments (H8S/2472 Group)
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Section 1 Overview
P61/IRQ15/PWX1/D1
P67/ExIRQ8/SSCK
P65/ExIRQ10/RTS
P66/ExIRQ9/SCS
PF0/RS8/MDIO
P22/A10/AD10
P23/A11/AD11
PF1/RS9/MDC
P64/ExIRQ11/CTS
P12/A2/AD2
P13/A3/AD3
P14/A4/AD4
P15/A5/AD5
P16/A6/AD6
P17/A7/AD7
P20/A8/AD8
P21/A9/AD9
P24/DCD
P26/DSR
P27/DTR
P60/IRQ14/PWX0/D0
P63/PWX3/D3
P62/PWX2/D2
P77/AN7
P76/AN6 PA5/ExIRQ5/EVENT5/WOL/A21
ETRST
P25/RI
ETMS
ETDO
ETCK
ETDI
108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
VCC
VSS
NC
P75/AN5
AVCC
P11/A1/AD1 109 VSS 110 P10/A0/AD0 111 PB7/EVENT15/RM_RX-ER 112 PB6/EVENT14/RM_CRS-DV 113 PB5/EVENT13/RM_REF-CLK 114 PB4/EVENT12/RM_TX-EN 115 PB3/EVENT11/DB3/RM_RXD1 116 PB2/EVENT10/DB2/RM_RXD0 117 PB1/EVENT9/DB1/RM_TXD1 118 PB0/EVENT8/DB0/RM_TXD0 119 VCC 120 P30/ExDB0/D8 121 P31/ExDB1/D9 122 P32/ExDB2/D10 123 P33/ExDB3/D11 124 P34/ExDB4/D12 125 P35/ExDB5/D13 126 P36/ExDB6/D14 127 P37/ExDB7/D15 128 P40/IRQ0/RS0/HC0/D4 129 P41/IRQ1/RS1/HC1/D5 130 P42/IRQ2/RS2/HC2/D6 131 P43/IRQ3/RS3/HC3/D7 132 P52/IRQ10/TxD1 133 P53/IRQ11/RxD1 134 FWE 135 P54/IRQ12/SSO 136 P55/IRQ13/SSI 137 P44/IRQ4/RS4/DB4/HC4/A12/AD12 138 NC 139 NC 140 VSS 141 RESO 142 XTAL 143 EXTAL 144
12
P45/IRQ5/RS5/DB5/HC5/A13/AD13 VCC
72 P74/AN4 71 P73/AN3 70 P72/AN2 69 P71/AN1 68 P70/AN0 67 AVSS 66 PD0/LSCI 65 PD1/LSMI 64 PD2/PME 63 PD3/GA20 62 PD4/CLKRUN 61 PD5/LPCPD 60 PD6/SCL5 59 PD7/SDA5 58 PE0/LAD0 57 PE1/LAD1 56 PE2/LAD2 55 PE3/LAD3 54 PE4/LFRAME 53 PE5/LRESET 52 PE6/LCLK 51 PE7/SERIRQ 50 P80/SCL0 49 P81/SDA0 48 P82/SCL1 47 P83/SDA1 46 P84/ExIRQ12/SCK3 45 P85/ExIRQ13/SCK1 44 P86/ExIRQ14/RxD3 43 P87/ExIRQ15/TxD3/ADTRG 42 VSS 41 PA0/ExIRQ0/EVENT0/A16 40 PA1/ExIRQ1/EVENT1/A17 39 PA2/ExIRQ2/EVENT2/A18 38 PA3/ExIRQ3/EVENT3/A19 37 PA4/ExIRQ4/EVENT4/A20
3
P46/IRQ6/RS6/DB6/HC6/A14/AD14
H8S/2463 Group PTQP0144LC-A TFP-144V (Top view)
4
P47/IRQ7/RS7/DB7/HC7/A15/AD15
567
P56/EXCL/ P57/WR/HWR VSS
8
RES
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
P92/HBE P94/ExPWX1 PF6/ExPWX2/RS14 P93/ExPWX0 P90/LBE PA7/ExIRQ7/EVENT7/EXOUT/A23 PA6/ExIRQ6/EVENT6/LNKSTA/A22 P91/AH P50/IRQ8/TxDF PC7/RD MD1 STBY PC5/SDA4 PC3/SDA3 P51/IRQ9/RxDF P95/AS/IOS PC1/SDA2 MD2 PC4/SCL4 PC2/SCL3 P97/CS256/WAIT PC0/SCL2 PC6/LWR VCC NMI VCL P96
Figure 1.3 Pin Assignments (H8S/2463 Group)
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Section 1 Overview
P61/IRQ15/PWX1/D1
P67/ExIRQ8/SSCK
P65/ExIRQ10/RTS
P66/ExIRQ9/SCS
PF0/RS8/MDIO
P22/A10/AD10
P23/A11/AD11
PF1/RS9/MDC
P64/ExIRQ11/CTS
P12/A2/AD2
P13/A3/AD3
P14/A4/AD4
P15/A5/AD5
P16/A6/AD6
P17/A7/AD7
P20/A8/AD8
P21/A9/AD9
P24/DCD
P26/DSR
P27/DTR
P60/IRQ14/PWX0/D0
P63/PWX3/D3
P62/PWX2/D2
P77/AN7
P76/AN6 PA5/ExIRQ5/EVENT5/WOL/A21
ETRST
P25/RI
ETMS
ETDO
ETCK
ETDI
108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
VCC
VSS
P75/AN5
72 P74/AN4 71 P73/AN3 70 P72/AN2 69 P71/AN1 68 P70/AN0 67 AVSS 66 PD0/LSCI 65 PD1/LSMI 64 PD2/PME 63 PD3/GA20 62 PD4/CLKRUN 61 PD5/LPCPD 60 PD6/SCL5 59 PD7/SDA5 58 PE0/LAD0 57 PE1/LAD1 56 PE2/LAD2 55 PE3/LAD3 54 PE4/LFRAME 53 PE5/LRESET 52 PE6/LCLK 51 PE7/SERIRQ 50 P80/SCL0 49 P81/SDA0 48 P82/SCL1 47 P83/SDA1 46 P84/ExIRQ12/SCK3 45 P85/ExIRQ13/SCK1 44 P86/ExIRQ14/RxD3 43 P87/ExIRQ15/TxD3/ADTRG 42 VSS 41 PA0/ExIRQ0/EVENT0/A16 40 PA1/ExIRQ1/EVENT1/A17 39 PA2/ExIRQ2/EVENT2/A18 38 PA3/ExIRQ3/EVENT3/A19 37 PA4/ExIRQ4/EVENT4/A20
P11/A1/AD1 109 VSS 110 P10/A0/AD0 111 PB7/EVENT15/RM_RX-ER 112 PB6/EVENT14/RM_CRS-DV 113 PB5/EVENT13/RM_REF-CLK 114 PB4/EVENT12/RM_TX-EN 115 PB3/EVENT11/DB3/RM_RXD1 116 PB2/EVENT10/DB2/RM_RXD0 117 PB1/EVENT9/DB1/RM_TXD1 118 PB0/EVENT8/DB0/RM_TXD0 119 VCC 120 P30/ExDB0/D8 121 P31/ExDB1/D9 122 P32/ExDB2/D10 123 P33/ExDB3/D11 124 P34/ExDB4/D12 125 P35/ExDB5/D13 126 P36/ExDB6/D14 127 P37/ExDB7/D15 128 P40/IRQ0/RS0/HC0/D4 129 P41/IRQ1/RS1/HC1/D5 130 P42/IRQ2/RS2/HC2/D6 131 P43/IRQ3/RS3/HC3/D7 132 PEVref 133 PECI 134 P52/IRQ10/TxD1 135 P53/IRQ11/RxD1 136 FWE 137 P54/IRQ12/SSO 138 P55/IRQ13/SSI 139 P44/IRQ4/RS4/DB4/HC4/A12/AD12 140 VSS 141 RESO 142 XTAL 143 EXTAL 144 12 3 4 567 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
H8S/2462 Group PLQP0144KA-A FP-144LV (Top view)
P97/CS256/WAIT
P92/HBE
P90/LBE
P91/AH
PA7/ExIRQ7/EVENT7/EXOUT/A23
AVCC
AVref PC0/SCL2
PA6/ExIRQ6/EVENT6/LNKSTA/A22
P95/AS/IOS
PC6/LWR
PC4/SCL4
P50/IRQ8/TxDF
P94/ExPWX1
P93/ExPWX0
P56/EXCL/
PC5/SDA4
PC3/SDA3
PC2/SCL3
PC7/RD
P45/IRQ5/RS5/DB5/HC5/A13/AD13
P46/IRQ6/RS6/DB6/HC6/A14/AD14
P47/IRQ7/RS7/DB7/HC7/A15/AD15
P57/WR/HWR
PF6/ExPWX2/RS14
P51/IRQ9/RxDF
PC1/SDA2
VSS
P96
VCC
MD1
Figure 1.4 Pin Assignments (H8S/2462 Group)
Rev. 2.00 Aug. 20, 2008 Page 6 of 1198 REJ09B0403-0200
STBY
MD2
VCC
RES
VCL
NMI
Section 1 Overview
1.3.2 Table 1.1
Pin Assignment in Each Operating Mode Pin Assignments in Each Operating Mode
Pin No. Pin Name Single-Chip Mode (EXPE = 0) VCC Flash Memory Programmer Mode VCC
H8S/2462 H8S/2463 H8S/2472 Extended Mode (FP-144LV) (TFP-144V) (BP-176V) (EXPE = 1) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 A1 C3 B1 C2 D3 C1 D2 E4 D1 E3 E2 E1 F4 F3 F1 F2 G4 G3 G1 G2 H4 H3 H1 H2 VCC
P45/IRQ5/RS5/DB5/ P45/IRQ5/RS5/DB5/ FA13 HC5/A13/AD13 HC5 P46/IRQ6/RS6/DB6/ P46/IRQ6/RS6/DB6/ FA14 HC6/A14/AD14 HC6 P47/IRQ7/RS7/DB7/ P47/IRQ7/RS7/DB7/ FA15 HC7/A15/AD15 HC7 P56/EXCL/phi WR/HWR VSS RES MD1 PF6/ExPWX2/RS14 NMI STBY NC VCL MD2 P51/IRQ9/RxDF P50/IRQ8/TxDF P97/CS256/WAIT P96 AS/IOS P94/ExPWX1 P93/ExPWX0 NC P92/HBE P56/EXCL/phi P57 VSS RES MD1 PF6/ExPWX2/RS14 NMI STBY NC VCL MD2 P51/IRQ9/RxDF P50/IRQ8/TxDF P97 P96 P95 P94/ExPWX1 P93/ExPWX0 NC P92 NC NC VSS RES VSS VSS FA9 VCC NC VCL VCC NC NC NC NC NC NC NC NC NC
Rev. 2.00 Aug. 20, 2008 Page 7 of 1198 REJ09B0403-0200
Section 1 Overview
Pin No. H8S/2462 H8S/2463 H8S/2472 Extended Mode (FP-144LV) (TFP-144V) (BP-176V) (EXPE = 1) 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 J4 J3 J1 J2 K4 K3 K1 K2 L3 L1 L2 L4 M1 M2 M3 N1 M4 N2 P1 P2 R1 N3 R2 P3 P91/AH P90/LBE NC RD PC6/LWR PC5/SDA4 PC4/SCL4 PC3/SDA3 NC PC2/SCL3 NC PC1/SDA2 NC PC0/SCL2
Pin Name Single-Chip Mode (EXPE = 0) P91 P90 NC PC7 PC6 PC5/SDA4 PC4/SCL4 PC3/SDA3 NC PC2/SCL3 NC PC1/SDA2 NC PC0/SCL2 Flash Memory Programmer Mode NC NC NC WE NC NC NC NC NC NC NC NC NC NC VCC VCC VSS VCC CE FA19 NC FA18 NC FA17
PA7/ExIRQ7/ PA7/ExIRQ7/ EVENT7/EXOUT/A23 EVENT7/EXOUT
PA6/ExIRQ6/ EVENT6/LNKSTA/A22 PA6/ExIRQ6/ EVENT6/LNKSTA
PA5/ExIRQ5/ EVENT5/WOL/A21 VCC
PA4/ExIRQ4/EVENT4/ A20 PA3/ExIRQ3/EVENT3/ A19
PA5/ExIRQ5/ EVENT5/WOL VCC
PA4/ExIRQ4/EVENT4 PA3/ExIRQ3/EVENT3
NC
PA2/ExIRQ2/EVENT2/ A18
NC
PA2/ExIRQ2/EVENT2
NC
PA1/ExIRQ1/EVENT1/ A17
NC
PA1/ExIRQ1/EVENT1
Rev. 2.00 Aug. 20, 2008 Page 8 of 1198 REJ09B0403-0200
Section 1 Overview
Pin No. H8S/2462 H8S/2463 H8S/2472 Extended Mode (FP-144LV) (TFP-144V) (BP-176V) (EXPE = 1) 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 N4 R3 P4 M5 R4 N5 P5 R5 M6 N6 R6 P6 M7 N7 R7 P7 M8 N8 R8 P8 M9 N9 R9 P9 M10 N10 R10 P10 NC
Pin Name Single-Chip Mode (EXPE = 0) NC
PA0/ExIRQ0/EVENT0
Flash Memory Programmer Mode NC FA16 NC VSS NC
PA0/ExIRQ0/EVENT0/ A16
NC VSS NC
NC VSS NC
P87/ExIRQ15/TxD3/ P87/ExIRQ15/TxD3/ NC ADTRG ADTRG P86/ExIRQ14/RxD3 P86/ExIRQ14/RxD3 NC
P85/ExIRQ13/SCK1 P85/ExIRQ13/SCK1 NC P84/ExIRQ12/SCK3 P84/ExIRQ12/SCK3 NC P83/SDA1 P82/SCL1 P81/SDA0 P80/SCL0 NC PE7/SERIRQ NC PE6/LCLK PE5/LRESET PE4/LFRAME PE3/LAD3 PE2/LAD2 PE1/LAD1 PE0/LAD0 VCC PD7/SDA5 PD6/SCL5 PD5/LPCPD PD4/CLKRUN P83/SDA1 P82/SCL1 P81/SDA0 P80/SCL0 NC PE7/SERIRQ NC PE6/LCLK PE5/LRESET PE4/LFRAME PE3/LAD3 PE2/LAD2 PE1/LAD1 PE0/LAD0 VCC PD7/SDA5 PD6/SCL5 PD5/LPCPD PD4/CLKRUN NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC
Rev. 2.00 Aug. 20, 2008 Page 9 of 1198 REJ09B0403-0200
Section 1 Overview
Pin No. H8S/2462 H8S/2463 H8S/2472 Extended Mode (FP-144LV) (TFP-144V) (BP-176V) (EXPE = 1) 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 N11 R11 P11 M11 R12 P12 N12 R13 M12 P13 R14 P14 R15 N13 P15 N14 M13 N15 M14 L12 M15 L13 L14 L15 K12 K13 K15 K14 PD3/GA20 PD2/PME PD1/LCMI PD0/LSCI NC AVSS P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6 P77/AN7 AVCC AVref
Pin Name Single-Chip Mode (EXPE = 0) PD3/GA20 PD2/PME PD1/LCMI PD0/LSCI NC AVSS P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6 P77/AN7 AVCC AVref Flash Memory Programmer Mode NC NC NC NC NC VSS NC NC NC NC NC NC NC NC VCC VCC NC NC NC NC NC NC NC NC VCC VCC NC NC
P60/IRQ14/PWX0/D0 P60/IRQ14/PWX0 P61/IRQ15/PWX1/D1 P61/IRQ15/PWX1 P62/PWX2/D2 P63/PWX3/D3 P64/ExIRQ11/CTS P65/ExIRQ10/RTS P66/ExIRQ9/SCS P67/ExIRQ8/SSCK VCC DrVCC USD- USD+ P62/PWX2 P63/PWX3 P64/ExIRQ11/CTS P65/ExIRQ10/RTS P66/ExIRQ9/SCS P67/ExIRQ8/SSCK VCC DrVCC USD- USD+
Rev. 2.00 Aug. 20, 2008 Page 10 of 1198 REJ09B0403-0200
Section 1 Overview
Pin No. H8S/2462 H8S/2463 H8S/2472 Extended Mode (FP-144LV) (TFP-144V) (BP-176V) (EXPE = 1) 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 J12 J13 J15 J14 H12 H13 H15 H14 G12 G13 G15 G14 F12 F13 F15 F14 E13 E15 E14 E12 D15 D14 D13 C15 D12 C14 B15 B14 NC DrVSS PUPDPLS VBUS ETMS ETDO ETDI ETCK ETRST PF2/RS10 NC PF1/RS9/MDC PF0/RS8/MDIO NC VSS P27/DTR P26/DSR P25/RI P24/DCD P23/A11/AD11 P22/A10/AD10 P21/A9/AD9 P20/A8/AD8 P17/A7/AD7 P16/A6/AD6 P15/A5/AD5 P14/A4/AD4 P13/A3/AD3 P12/A2/AD2
Pin Name Single-Chip Mode (EXPE = 0) NC DrVSS PUPDPLS VBUS ETMS ETDO ETDI ETCK ETRST PF2/RS10 NC PF1/RS9/MDC PF0/RS8/MDIO NC VSS P27/DTR P26/DSR P25/RI P24/DCD P23 P22 P21 P20 P17 P16 P15 P14 P13 P12 Flash Memory Programmer Mode NC VSS NC NC NC NC NC NC RES NC NC NC NC NC VSS NC NC NC NC FA11 FA10 OE FA8 FA7 FA6 FA5 FA4 FA3 FA2
Rev. 2.00 Aug. 20, 2008 Page 11 of 1198 REJ09B0403-0200
Section 1 Overview
Pin No. H8S/2462 H8S/2463 H8S/2472 Extended Mode (FP-144LV) (TFP-144V) (BP-176V) (EXPE = 1) 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 A15 C13 A14 B13 C12 A13 B12 D11 A12 C11 B11 A11 D10 C10 A10 B10 D9 C9 A9 B9 D8 C8 P11/A1/AD1 VSS P10/A0/AD0 PB7/EVENT15/ RM_RX-ER PB6/EVENT14/ RM_CRS-DV PB5/EVENT13/ RM_REF-CLK PB4/EVENT12/ RM_TX-EN
Pin Name Single-Chip Mode (EXPE = 0) P11 VSS P10 PB7/EVENT15/ RM_RX-ER PB6/EVENT14/ RM_CRS-DV PB5/EVENT13/ RM_REF-CLK PB4/EVENT12/ RM_TX-EN Flash Memory Programmer Mode FA1 VSS FA0 NC NC NC NC
PB3/EVENT11/DB3/ PB3/EVENT11/DB3/ NC RM_RXD1 RM_RXD1 PB2/EVENT10/DB2/ PB2/EVENT10/DB2/ NC RM_RXD0 RM_RXD0 PB1/EVENT9/DB1/ RM_TXD1 PB0/EVENT8/DB0/ RM_TXD0 VCC D8 D9 D10 D11 D12 D13 D14 D15 PB1/EVENT9/DB1/ RM_TXD1 PB0/EVENT8/DB0/ RM_TXD0 VCC P30/ExDB0 P31/ExDB1 P32/ExDB2 P33/ExDB3 P34/ExDB4 P35/ExDB5 P36/ExDB6 P37/ExDB7 NC NC VCC FO0 FO1 FO2 FO3 FO4 FO5 FO6 FO7 NC NC
P40/IRQ0/RS0/HC0/ P40/IRQ0/RS0/HC0 D4 P41/IRQ1/RS1/HC1/ P41/IRQ1/RS1/HC1 D5
Rev. 2.00 Aug. 20, 2008 Page 12 of 1198 REJ09B0403-0200
Section 1 Overview
Pin No. H8S/2462 H8S/2463 H8S/2472 Extended Mode (FP-144LV) (TFP-144V) (BP-176V) (EXPE = 1) 131 132 133 134 135 136 137 138 139 140 141 142 143 144 131 132 133 134 135 136 137 138 139 140 141 142 143 144 A8 B8 D7 C7 A7 B7 D6 C6 A6 B6 C5 A5 B5 D5 A4 B4 C4 A3 D4 B3 A2 B2
Pin Name Single-Chip Mode (EXPE = 0) Flash Memory Programmer Mode NC NC VSS NC VCC VSS FWE NC NC
P42/IRQ2/RS2/HC2/ P42/IRQ2/RS2/HC2 D6 P43/IRQ3/RS3/HC3/ P43/IRQ3/RS3/HC3 D7 PEVref PECI P52/IRQ10/TxD1 P53/IRQ11/RxD1 FWE P54/IRQ12/SSO P55/IRQ13/SSI PEVref PECI P52/IRQ10/TxD1 P53/IRQ11/RxD1 FWE P54/IRQ12/SSO P55/IRQ13/SSI
P44/IRQ4/RS4/DB4/ P44/IRQ4/RS4/DB4/ FA12 HC4/A12/AD12 HC4 VCC UXTAL UEXTAL UXSEL PF5/RS13 PF4/RS12 NC NC VSS PF3/ExPWX3/RS11 RESO XTAL EXTAL VCC UXTAL UEXTAL UXSEL PF5/RS13 PF4/RS12 NC NC VSS PF3/ExPWX3/RS11 RESO XTAL EXTAL VCC NC NC NC NC NC NC NC VSS NC NC XTAL EXTAL
Rev. 2.00 Aug. 20, 2008 Page 13 of 1198 REJ09B0403-0200
Section 1 Overview
1.3.3 Table 1.2
Pin Functions Pin Functions
Pin No.
H8S/2462 H8S/2463 H8S/2472
Type Power supply
Symbol VCC
144-Pin
144-Pin
176-Pin
I/O
Name and Function Power supply pins. Connect all these pins to the system power supply. Connect the bypass capacitor between VCC and VSS (near VCC). External capacitance pin for internal step-down power. Connect this pin to Vss through an external capacitor (that is located near this pin) to stabilize internal step-down power. Ground pins. Connect all these pins to the system power supply (0V). For connection to a crystal resonator. An external clock can be supplied from the EXTAL pin. For an example of crystal resonator connection, see section 27, Clock Pulse Generator. For connection to a crystal resonator for USB USB clock source select pin Supplies the system clock to external devices. 32.768-kHz external clock for sub clock should be supplied. These pins set the operating mode. Inputs at these pins should not be changed during operation. Reset pin. When this pin is low, the chip is reset.
1, 36, 1, 36, A1, N2, Input 86, 120 86, 120 P9, K12, A11, C5 13 13 F3 Input
VCL
VSS
7, 42, 7, 42, D2, M5, Input 94, 110, 94, 110, F13, 141 141 C13, A3 143 144 143 144 A2 B2 Input Input
Clock
XTAL EXTAL
UXTAL UEXTAL UXSEL EXCL
5 5
5 5
A5 B5 D5 D3 D3
Input Input Input Output Input
Operating MD2 mode control MD1 System control RES
14 9 8
14 9 8
F1 D1 E4
Input
Input
Rev. 2.00 Aug. 20, 2008 Page 14 of 1198 REJ09B0403-0200
Section 1 Overview
Pin No.
H8S/2462 H8S/2463 H8S/2472
Type System control
Symbol RESO STBY FWE
144-Pin
144-Pin
176-Pin
I/O 142 12 Input
Name and Function Outputs a reset signal to an external device. When this pin is low, a transition is made to hardware standby mode. Pin for use by flash memory. Address output pins
142 12 137 33 to 35, 37 to 41
142 12 135 33 to 35, 37 to 41 4 to 2, 138, 99 to 109, 111
B3 E1 D6
Address bus A23 to A16
M3, N1, Output M4, P1, P2, N3, P3, R3 C2, B1, C3, B6, E14, E12, D15, D14, D13, C15, D12, C14, B15, B14, A15, A14 B9, A9, Input/ C9, D9, Output B10, A10, C10, D10
A15 to A0 4 to 2, 140, 99 to 109, 111
Data bus
D15 to D8 128 to 121
128 to 121
Upper 8 bits of bidirectional bus
D7 to D0
132 to 132 to B8, A8, 129, 129, C8, D8, 81 to 78 80 to 77 L12, M14, N15, M13
Lower 8 bits of bidirectional bus
Rev. 2.00 Aug. 20, 2008 Page 15 of 1198 REJ09B0403-0200
Section 1 Overview
Pin No.
H8S/2462 H8S/2463 H8S/2472
Type
Symbol
144-Pin
144-Pin
176-Pin
I/O
Name and Function 8 bit bus or upper 8 bits of 16-bit bus
AddressAD15 to data AD8 multiplex bus
4 to 2, 140, 99 to 102
4 to 2, 138, 99 to 102
C2, B1, Input/ C3, B6, Output E14, E12, D15, D14 D13, C15, D12, C14, B15, B14, A15, A14 E2 Input
AD7 to AD0
103 to 109, 111
103 to 109, 111
Lower 8 bits of 16-bit bus
Interrupts
NMI IRQ15 to IRQ0
11 79, 78, 139, 138, 136, 135, 15, 16, 4 to 2, 140, 132 to 129
11 78, 77, 137, 136, 134, 133, 15, 16, 4 to 2, 138, 132 to 129 43 to 46, 81 to 84, 33 to 35, 37 to 41
Nonmaskable interrupt request input pin These pins are used to request maskable interrupts. Either IRQn or ExIRQn can be selected as the IRQn interrupt signal input pin.
N15, Input M13, A6, C6, B7, D6, F2, G4, C2, B1, C3, B6, B8, A8, C8, D8 N5, P5, Input R5, M6, M15, L13, L14, L15, M3, N1, M4, P1, P2, N3, P3, R3 G3 Input
ExIRQ15 43 to to ExIRQ0 46, 82 to 85, 33 to 35, 37 to 41
These pins are used to request maskable interrupts. Either IRQn or ExIRQn can be selected as the IRQn interrupt signal input pin.
Bus control
WAIT
17
17
Requests wait state insertion to bus cycles when an external tristate address space is accessed.
Rev. 2.00 Aug. 20, 2008 Page 16 of 1198 REJ09B0403-0200
Section 1 Overview
Pin No.
H8S/2462 H8S/2463 H8S/2472
Type Bus control
Symbol RD
144-Pin
144-Pin
176-Pin
I/O Output
Name and Function Low level on this pin indicates that the MCU is reading from an external address space. Low level on this pin indicates that the MCU is writing to an external address space. The upper byte of the data bus is valid. Low level on this pin indicates that the MCU is writing to an external address space. The lower byte of the data bus is valid. Low level on this pin indicates that the address output on the address bus is valid. Indicates access to the 256-Kbyte area of H'F80000 to H'FBFFFF. Low level on this pin indicates that the MCU is writing to an external address space. Low level on this pin indicates that the MCU is accessing an external address space. The upper byte of the data bus is valid. Low level on this pin indicates that the MCU is accessing an external address space. The lower byte of the data bus is valid. Address latch signal for the address-data multiplex bus Boundary scan interface pins
25
25
J2
HWR
6
6
C1
Output
LWR
26
26
K4
Output
AS/IOS
19
19
G2
Output
CS256 Bus control WR
17 6
17 6
G3 C1
Output Output
HBE
22
22
H2
Output
LBE
24
24
J3
Output
AH Boundary scan ETRST ETMS ETDO ETDI ETCK
23 91 87 88 89 90
23 90 86 87 88 89
J4 G12 H12 H13 H15 H14
Output Input Input Output Input Input
Rev. 2.00 Aug. 20, 2008 Page 17 of 1198 REJ09B0403-0200
Section 1 Overview
Pin No.
H8S/2462 H8S/2463 H8S/2472
Type 14-bit PWM timer (PWMX)
Symbol PWX0 to PWX3 ExPWX0 to ExPWX2 ExPWX3
144-Pin
144-Pin
176-Pin
I/O
Name and Function PWM D/A pulse output pins Pin ExPWX3 is supported only by the H8S/2472 Group.
78 to 81, 21, 20, 10
77 to 80, 21, 20, 10
Output M13, N15, M14, L12, H3, H4, E3 D4 Output Input
Serial communication interface (SCI_1 and SCI_3) Serial communication interface with FIFO (SCIF)
TxD1, TxD3 RxD1, RxD3 SCK1, SCK3 TxDF RxDF CTS RTS DTR DSR RI DCD
135, 43 133, 43 A7, N5 136, 44 134, 44 B7, P5 45, 46 16 15 82 83 95 96 97 98 85 139 138 84 50, 48, 32, 30, 28, 60 45, 46 16 15 81 82 95 96 97 98 84 137 136 83 50, 48, 32, 30, 28, 60
Transmit data output pins Receive data input pins Clock input/output pins. Transmit data output pin Receive data input pin Transmit grant input pin Transmit request output pin Data terminal ready output pin Data set ready input pin Ring indicator input pin Data carrier detection input pin SSU clock I/O pin SSU data I/O pin SSU data I/O pin SSU chip select I/O pin IIC clock input/output pins. These pins can drive a bus directly with the NMOS open drain output.
R5, M6 Input/ Output G4 F2 M15 L13 F15 F14 E13 E15 L15 A6 C6 L14 Output Input Input Output Output Input Input Input Input/ Output Input/ Output Input/ Output Input/ Output
Synchronous SSCK serial communiSSI cation unit (SSU) SSO SCS I C bus interface (IIC)
2
SCL0 to SCL5
M7, R6, Input/ M2, L1, Output K1, N10
Rev. 2.00 Aug. 20, 2008 Page 18 of 1198 REJ09B0403-0200
Section 1 Overview
Pin No.
H8S/2462 H8S/2463 H8S/2472
Type I C bus interface (IIC) A/D converter
2
Symbol SDA0 to SDA5 AN7 to AN0
144-Pin
144-Pin
176-Pin
I/O
Name and Function IIC data input/output pins. These pins can drive a bus directly with the NMOS open drain output. Analog input pins
49, 47, 31, 29, 27, 59
49, 47, 31, 29, 27, 59
P6, N6, Input/ L4, K2, Output K3, M10 Input
75 to 68 75 to 68 N13, R15, P14, R14, P13, M12, R13, N12 76 76 P15
AVCC
Input
Analog power supply pins. When the A/D converter is not used, these pins should be connected to the system power supply (+3.3 V). Analog reference voltage input pin. When the A/D converter is not used, this pin should be connected to the system power supply (+3.3 V). Analog ground pins. These pins should be connected to the system power supply (0 V). External trigger input pin to start A/D conversion Transfer cycle type/address/data I/O pins Input pin indicating transfer cycle start and forced termination LPC reset pin. When this pin is low, a reset state is entered. PCI clock input pin LPC serialized host interrupt request signal LPC auxiliary output. Their functions are general I/O port.
AVref
77
N14
Input
AVSS
67
67
P12
Input
ADTRG LPC Interface (LPC) LAD3 to LAD0 LFRAME LRESET LCLK SERIRQ LSCI, LSMI, PME
43
43
N5
Input
55 to 58 55 to 58 P8, M9, Input/ N9, R9 Output 54 53 52 51 66 65 64 54 53 52 51 66 65 64 R8 N8 M8 R7 M11 P11 R11 Input Input Input Input/ Output Input/ Output
Rev. 2.00 Aug. 20, 2008 Page 19 of 1198 REJ09B0403-0200
Section 1 Overview
Pin No.
H8S/2462 H8S/2463 H8S/2472
Type LPC Interface (LPC)
Symbol GA20
144-Pin
144-Pin
176-Pin
I/O Input/ Output Input/ Output Input Input Output Output Output Input Input Input Input Input Input/ Output Input Output Output Input Input/ Output Input/ Output Input Input Output
Name and Function GATE A20 control signal output pin; also used as the input pin for monitoring the output state. Input/output pin used to request starting the LCLK operation while LCLK is stopped. Input pin used to control shutdown of the LCP module Transmit/receive Clock Transmit enable Transmit data Carrier detection/receive data valid Receive data Receive error Management data clock Management data I/O Link status General-purpose external output Wake-on-LAN USB cable connection monitor pin USB data I/O pin USB data I/O pin Power supply pin for USB built-in transceiver Ground pin for USB built-in transceiver USB+ pull-up control pin
63
63
N11
CLKRUN
62
62
P10
LPCPD Ethernet controller (EtherC)
61
61 114 115 118 119 113 116 117 112 92 93 34 33 35
R10 A13 B12 C11 B11 C12 D11 A12 B13 G15 G14 N1 M3 M4 J14 K14 K15 K13 J13 J15
RM_REF- 114 CLK RM_TXEN 115
RM_TXD1 118 RM_TXD0 119 RM_CRS- 113 DV RM_RXD1 116 RM_RXD0 117 RM_RXER MDC MDIO LNKSTA EXOUT WOL USB function VBUS module USD+ (USB) USD- DrVcc DrVss 112 92 93 34 33 35
PUPDPLS
Rev. 2.00 Aug. 20, 2008 Page 20 of 1198 REJ09B0403-0200
Section 1 Overview
Pin No.
H8S/2462 H8S/2463 H8S/2472
Type Event Counter
Symbol
144-Pin
144-Pin
176-Pin
I/O
Name and Function Event counter input pins
EVENT15 112 to to 119, EVENT0 33 to 35, 37 to 41
112 to 119, 33 to 35, 37 to 41
Input B13, C12, A13, B12, D11, A12, C11, B11, M3, N1, M4, P1, P2, N3, P3, R3 E3 A4, B4, D4, G13 G15, G14, C2, B1, C3, B6, B8, A8, C8, D8 C2, B1, Input C3, B6, D11, A12, C11, B11 B9, A9, C9, D9, B10, A10, C10, D10 Output
Retain state RS14 output pins RS13 to RS10 RS9 to RS0
10 92, 93, 4 to 2, 140, 132 to 129 4 to 2, 140, 116 to 119
10 92,93,4 to 2, 138, 132 to 129 4 to 2, 138, 116 to 119
Retain state output pins. The outputs on these pins are only initialized by a system reset. Pins RS13 to RS10 are supported only by the H8S/2472 Group.
Debounced input pins
DB7 to DB0
Pins with noise eliminating functions.
ExDB7 to 128 to ExDB0 121
128 to 121
Rev. 2.00 Aug. 20, 2008 Page 21 of 1198 REJ09B0403-0200
Section 1 Overview
Pin No.
H8S/2462 H8S/2463 H8S/2472
Type Large current output pins I/O ports
Symbol HC7 to HC0
144-Pin
144-Pin
176-Pin
I/O
Name and Function These pins can be used to drive LEDs or for other purposes where large currents are required. 8-bit input/output pins
4 to 2, 140, 132 to 129 103 to 109, 111
4 to 2, 138, 132 to 129 103 to 109, 111
C2, B1, Output C3, B6, B8, A8, C8, D8 D13, C15, D12, C14, B15, B14, A15 F15, F14, E13, E15, E14, E12, D15, D14 Input/ Output
P17 to P10
P27 to P20
95 to 102
95 to 102
Input/ Output
8-bit input/output pins
P37 to P30
128 to 121
128 to 121
B9, A9, Input/ C9, D9, Output B10, A10, C10, D10 C2, B1, Input/ C3, B6, Output B8, A8, C8, D8 C1, D3, Input/ A6, C6, Output B7, A7, F2, G4
8-bit input/output pins
P47 to P40
4 to 2, 140, 132 to 129 6, 5, 139, 138, 136, 135, 15, 16
4 to 2, 138, 132 to 129 6, 5, 137, 136, 134, 133, 15, 16
8-bit input/output pins
P57 to P50
8-bit input/output pins
Rev. 2.00 Aug. 20, 2008 Page 22 of 1198 REJ09B0403-0200
Section 1 Overview
Pin No.
H8S/2462 H8S/2463 H8S/2472
Type I/O ports
Symbol P67 to P60
144-Pin
144-Pin
176-Pin
I/O Input/ Output
Name and Function 8-bit input/output pins
85 to 78 84 to 77 L15, L14, L13, M15, L12, M14, N15, M13 75 to 68 75 to 68 N13, R15, P14, R14, P13, M12, R13, N12
P77 to P70
Input
8-bit input pins
P87 to P80
43 to 50 43 to 50 N5, P5, Input/ R5, M6, Output N6, R6, P6, M7 17 to 24 17 to 24 G3, G1, Input/ G2, H4, Output H3, H2, J4, J3 33 to 35, 37 to 41 112 to 119 33 to 35, 37 to 41 112 to 119 M3, N1, Input/ M4, P1, Output P2, N3, P3, R3 B13, C12, A13, B12, D11, A12, C11, B11 Input/ Output
8-bit input/output pins
P97 to P90
8-bit input/output pins
PA7 to PA0
8-bit input/output pins
PB7 to PB0
8-bit input/output pins
PC7 to PC0
25 to 32 25 to 32 J2, K4, Input/ K3, K1, Output K2, L1, L4, M2
8-bit input/output pins
Rev. 2.00 Aug. 20, 2008 Page 23 of 1198 REJ09B0403-0200
Section 1 Overview
Pin No.
H8S/2462 H8S/2463 H8S/2472
Type I/O ports
Symbol PD7 to PD0
144-Pin
144-Pin
176-Pin
I/O Input/ Output
Name and Function 8-bit input/output pins
59 to 66 59 to 66 M10, N10, R10, P10, N11, R11, P11, M11
PE7 to PE0
51 to 58 51 to 58 R7, M8, Input/ N8, R8, Output P8, M9, N9, R9 10 10 92, 93 E3 A4, B4, D4, G13 G15, G14 Input/ Output
8-bit input/output pins
PF6 PF5 to PF2
7-bit input/output pins. Pins PF5 to PF2 are supported only by the H8S/2472 Group.
PF1, PF0 92, 93
Rev. 2.00 Aug. 20, 2008 Page 24 of 1198 REJ09B0403-0200
Section 2 CPU
Section 2 CPU
The H8S/2600 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2600 CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ideal for realtime control. This section describes the H8S/2600 CPU. The usable modes and address spaces differ depending on the product. For details on each product, refer to section 3, MCU Operating Modes.
2.1
Features
* Upward-compatible with H8/300 and H8/300H CPUs Can execute H8/300 and H8/300H CPUs object programs * General-register architecture Sixteen 16-bit general registers also usable as sixteen 8-bit registers or eight 32-bit registers * Sixty-nine basic instructions 8/16/32-bit arithmetic and logic instructions Multiply and divide instructions Powerful bit-manipulation instructions Multiply-and-accumulate instruction * Eight addressing modes Register direct [Rn] Register indirect [@ERn] Register indirect with displacement [@(d:16,ERn) or @(d:32,ERn)] Register indirect with post-increment or pre-decrement [@ERn+ or @-ERn] Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32] Immediate [#xx:8, #xx:16, or #xx:32] Program-counter relative [@(d:8,PC) or @(d:16,PC)] Memory indirect [@@aa:8] * 16-Mbyte address space Program: 16 Mbytes Data: 16 Mbytes * High-speed operation All frequently-used instructions execute in one or two states 8/16/32-bit register-register add/subtract: 1 state 8 x 8-bit register-register multiply: 2 states
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Section 2 CPU
16 / 8-bit register-register divide: 12 states 16 x 16-bit register-register multiply: 3 states 32 / 16-bit register-register divide: 20 states * Two CPU operating modes Normal mode* Advanced mode * Power-down state Transition to power-down state by the SLEEP instruction CPU clock speed selection Note: * Normal mode is not available in this LSI. 2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU
The differences between the H8S/2600 CPU and the H8S/2000 CPU are shown below. * Register configuration The MAC register is supported by the H8S/2600 CPU only. * Basic instructions The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported by the H8S/2600 CPU only. * The number of execution states of the MULXU and MULXS instructions;
Execution States Instruction MULXU Mnemonic MULXU.B Rs, Rd MULXU.W Rs, ERd MULXS MULXS.B Rs, Rd MULXS.W Rs, ERd CLRMAC LDMAC CLRMAC LDMAC ERs,MACH LDMAC ERs,MACL STMAC Note: * STMAC MACH,ERd STMAC MACl,ERd H8S/2600 2* 2* 3* 3* 1* 1* 1* 1* 1* H8S/2000 12 20 13 21 Not supported
This becomes one state greater immediately after a MAC instruction. In addition, there are differences in address space, CCR and EXR register functions, and power-down modes, etc., depending on the model.
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Section 2 CPU
2.1.2
Differences from H8/300 CPU
In comparison to the H8/300 CPU, the H8S/2600 CPU has the following enhancements: * More general registers and control registers Eight 16-bit extended registers, and one 8-bit and two 32-bit control registers, have been added. * Expanded address space Normal mode supports the same 64-kbyte address space as the H8/300 CPU. Advanced mode supports a maximum 16-Mbyte address space. * Enhanced addressing The addressing modes have been enhanced to make effective use of the 16-Mbyte address space. * Enhanced instructions Addressing modes of bit-manipulation instructions have been enhanced. Signed multiply and divide instructions have been added. A multiply-and-accumulate instruction has been added. Two-bit shift instructions have been added. Instructions for saving and restoring multiple registers have been added. A test and set instruction has been added. * Higher speed Basic instructions execute twice as fast. 2.1.3 Differences from H8/300H CPU
In comparison to the H8/300H CPU, the H8S/2600 CPU has the following enhancements: * More control registers One 8-bit and two 32-bit control registers have been added. * Enhanced instructions Addressing modes of bit-manipulation instructions have been enhanced. A multiply-and-accumulate instruction has been added. Two-bit shift instructions have been added. Instructions for saving and restoring multiple registers have been added. A test and set instruction has been added. * Higher speed Basic instructions execute twice as fast.
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Section 2 CPU
2.2
CPU Operating Modes
The H8S/2600 CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte total address space. The mode is selected by the mode pins. 2.2.1 Normal Mode
The exception vector table and stack have the same structure as in the H8/300 CPU. * Address Space Linear access to a 64-kbyte maximum address space is provided. * Extended Registers (En) The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers. When En is used as a 16-bit register it can contain any value, even when the corresponding general register (Rn) is used as an address register. If the general register is referenced in the register indirect addressing mode with pre-decrement (@-Rn) or post-increment (@Rn+) and a carry or borrow occurs, however, the value in the corresponding extended register (En) will be affected. * Instruction Set All instructions and addressing modes can be used. Only the lower 16 bits of effective addresses (EA) are valid. * Exception Vector Table and Memory Indirect Branch Addresses In normal mode the top area starting at H'0000 is allocated to the exception vector table. One branch address is stored per 16 bits. The exception vector table structure in normal mode is shown in figure 2.1. For details of the exception vector table, see section 4, Exception Handling. The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In normal mode the operand is a 16-bit word operand, providing a 16-bit branch address. Branch addresses can be stored in the area from H'0000 to H'00FF. Note that the first part of this range is also used for the exception vector table. * Stack Structure When the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they are stored as shown in figure 2.2. EXR is not pushed onto the stack in interrupt control mode 0. For details, see section 4, Exception Handling. Note: Normal mode is not available in this LSI.
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Section 2 CPU
H'0000 H'0001 H'0002 H'0003 H'0004 H'0005 H'0006 H'0007 H'0008 H'0009 H'000A H'000B
Exception vector 1 Exception vector 2 Exception vector 3 Exception vector 4 Exception vector 5 Exception vector 6 Exception vector table
Figure 2.1 Exception Vector Table (Normal Mode)
SP
PC (16 bits)
SP (SP *
2
EXR*1 Reserved*1,*3 ) CCR CCR*3 PC (16 bits)
(a) Subroutine Branch Notes: 1. When EXR is not used it is not stored on the stack. 2. SP when EXR is not used. 3. lgnored when returning.
(b) Exception Handling
Figure 2.2 Stack Structure in Normal Mode
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Section 2 CPU
2.2.2
Advanced Mode
* Address Space Linear access to a 16-Mbyte maximum address space is provided. * Extended Registers (En) The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers or address registers. * Instruction Set All instructions and addressing modes can be used. * Exception Vector Table and Memory Indirect Branch Addresses In advanced mode, the top area starting at H'00000000 is allocated to the exception vector table in units of 32 bits. In each 32 bits, the upper 8 bits are ignored and a branch address is stored in the lower 24 bits (figure 2.3). For details of the exception vector table, see section 4, Exception Handling.
H'00000000 Reserved Exception vector 1 H'00000003 H'00000004 Reserved Exception vector 2 H'00000007 H'00000008 Reserved Exception vector table Exception vector 3 H'0000000B H'0000000C Reserved Exception vector 4 H'00000010 Reserved Exception vector 5
Figure 2.3 Exception Vector Table (Advanced Mode)
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Section 2 CPU
The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In advanced mode the operand is a 32-bit longword operand, providing a 32-bit branch address. The upper 8 bits of these 32 bits is a reserved area that is regarded as H'00. Branch addresses can be stored in the area from H'00000000 to H'000000FF. Note that the first part of this range is also used for the exception vector table. * Stack Structure In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they are stored as shown in figure 2.4. When EXR is not pushed onto the stack in interrupt control mode 0. For details, see section 4, Exception Handling.
SP SP Reserved PC (24 bits) (SP *2 )
EXR*1 Reserved*1, *3 CCR PC (24 bits)
(a) Subroutine Branch Notes: 1. When EXR is not used it is not stored on the stack. 2. SP when EXR is not used. 3. Ignored when returning.
(b) Exception Handling
Figure 2.4 Stack Structure in Advanced Mode
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Section 2 CPU
2.3
Address Space
Figure 2.5 shows a memory map for the H8S/2600 CPU. The H8S/2600 CPU provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte (architecturally 4-Gbyte) address space in advanced mode. The usable modes and address spaces differ depending on the product. For details on each product, refer to section 3, MCU Operating Modes.
H'0000 64-kbyte H'FFFF H'00000000 16-Mbyte Program area
H'00FFFFFF
Data area
Cannot be used in this LSI
H'FFFFFFFF (a) Normal Mode (b) Advanced Mode
Figure 2.5 Memory Map
Rev. 2.00 Aug. 20, 2008 Page 32 of 1198 REJ09B0403-0200
Section 2 CPU
2.4
Registers
The H8S/2600 CPU has the internal registers shown in figure 2.6. There are two types of registers; general registers and control registers. The control registers are a 24-bit program counter (PC), an 8-bit extended control register (EXR), an 8-bit condition code register (CCR), and a 64-bit multiply-accumulate register (MAC).
General Registers (Rn) and Extended Registers (En)
15 ER0 ER1 ER2 ER3 ER4 ER5 ER6 ER7 (SP) E0 E1 E2 E3 E4 E5 E6 E7 07 R0H R1H R2H R3H R4H R5H R6H R7H 07 R0L R1L R2L R3L R4L R5L R6L R7L 0
Control Registers (CR)
23 PC 0
EXR T
76543210 - - - - I2 I1 I0
76543210
CCR I UI H U N Z V C 63 MAC 31 [Legend] SP: PC: EXR: T: I2 to I0: CCR: I: UI: Stack pointer Program counter Extended control register Trace bit Interrupt mask bits Condition-code register Interrupt mask bit User bit or interrupt mask bit H: U: N: Z: V: C: MAC: Half-carry flag User bit Negative flag Zero flag Overflow flag Carry flag Multiply-accumulate register Sign extension MACL 0 41 MACH 32
Figure 2.6 CPU Registers
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Section 2 CPU
2.4.1
General Registers
The H8S/2600 CPU has eight 32-bit general registers. These general registers are all functionally identical and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.7 illustrates the usage of the general registers. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7). The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R (R0 to R7). These registers are functionally equivalent, providing a maximum of sixteen 16-bit registers. The E registers (E0 to E7) are also referred to as extended registers. The R registers divide into 8-bit general registers designated by the letters RH (R0H to R7H) and RL (R0L to R7L). These registers are functionally equivalent, providing a maximum of sixteen 8bit registers. The usage of each register can be selected independently. General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2.8 shows the stack.
* Address registers * 32-bit registers * 16-bit registers * 8-bit registers
E registers (extended registers) (E0 to E7) ER registers (ER0 to ER7) R registers (R0 to R7) RL registers (R0L to R7L) RH registers (R0H to R7H)
Figure 2.7 Usage of General Registers
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Section 2 CPU
Free area SP (ER7)
Stack area
Figure 2.8 Stack 2.4.2 Program Counter (PC)
This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an instruction is fetched, the least significant PC bit is regarded as 0). 2.4.3 Extended Control Register (EXR)
EXR is an 8-bit register that manipulates the LDC, STC, ANDC, ORC, and XORC instructions. When these instructions, except for the STC instruction, are executed, all interrupts including NMI will be masked for three states after execution is completed.
Bit 7 Bit Name T Initial Value 0 R/W R/W Description Trace Bit When this bit is set to 1, a trace exception is generated each time an instruction is executed. When this bit is cleared to 0, instructions are executed in sequence. 6 to 3 2 1 0 I2 I1 I0 All 1 1 1 1 R/W R/W R/W Reserved These bits are always read as 1. These bits designate the interrupt mask level (0 to 7). For details, refer to section 5, Interrupt Controller.
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Section 2 CPU
2.4.4
Condition-Code Register (CCR)
This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch (Bcc) instructions.
Bit 7 Bit Name I Initial Value 1 R/W R/W Description Interrupt Mask Bit Masks interrupts other than NMI when set to 1. NMI is accepted regardless of the I bit setting. The I bit is set to 1 at the start of an exception-handling sequence. For details, refer to section 5, Interrupt Controller. 6 UI Undefined R/W User Bit or Interrupt Mask Bit Can be read or written by software using the LDC, STC, ANDC, ORC, and XORC instructions. This bit cannot be used as an interrupt mask bit in this LSI. 5 H Undefined R/W Half-Carry Flag When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise. 4 U Undefined R/W User Bit Can be read or written by software using the LDC, STC, ANDC, ORC, and XORC instructions. 3 N Undefined R/W Negative Flag Stores the value of the most significant bit of data as a sign bit. 2 Z Undefined R/W Zero Flag Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data.
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Section 2 CPU
Bit 1
Bit Name V
Initial Value
R/W
Description Overflow Flag Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times.
Undefined R/W
0
C
Undefined R/W
Carry Flag Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by: * * * Add instructions, to indicate a carry Subtract instructions, to indicate a borrow Shift and rotate instructions, to indicate a carry
The carry flag is also used as a bit accumulator by bit manipulation instructions.
2.4.5
Multiply-Accumulate Register (MAC)
This 64-bit register stores the results of multiply-and-accumulate operations. It consists of two 32bit registers denoted MACH and MACL. The lower 10 bits of MACH are valid; the upper bits are a sign extension. 2.4.6 Initial Values of CPU Registers
Reset exception handling loads the CPU's program counter (PC) from the vector table, clears the trace bit in EXR to 0, and sets the interrupt mask bits in CCR and EXR to 1. The other CCR bits and the general registers are not initialized. In particular, the stack pointer (ER7) is not initialized. The stack pointer should therefore be initialized by an MOV.L instruction executed immediately after a reset.
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Section 2 CPU
2.5
Data Formats
The H8S/2600 CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, ..., 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data. 2.5.1 General Register Data Formats
Figure 2.9 shows the data formats in general registers.
Data Type
1-bit data
Register Number
RnH
Data Format
7 0 Don't care 76 54 32 10
7 1-bit data RnL Don't care
0
76 54 32 10
7 4-bit BCD data RnH Upper
43 Lower
0 Don't care
7 4-bit BCD data RnL Don't care Upper
43 Lower
0
7 Byte data RnH MSB
0 Don't care LSB 7 0 LSB
Byte data
RnL
Don't care MSB
Figure 2.9 General Register Data Formats (1)
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Section 2 CPU
Data Type Word data
Register Number Rn
Data Format
15
0
MSB
LSB
Word data
15
En
0
MSB
LSB
Longword data
31
ERn
16 15 0
MSB
En
Rn
LSB
[Legend]
ERn: En: Rn: RnH: RnL: MSB: LSB: General register ER General register E General register R General register RH General register RL Most significant bit Least significant bit
Figure 2.9 General Register Data Formats (2)
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Section 2 CPU
2.5.2
Memory Data Formats
Figure 2.10 shows the data formats in memory. The H8S/2600 CPU can access word data and longword data in memory, however word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, an address error does not occur, however the least significant bit of the address is regarded as 0, so access begins the preceding address. This also applies to instruction fetches. When ER7 is used as an address register to access the stack, the operand size should be word or longword.
Data Type Address
7 1-bit data Address L 7 6 5 4 3 2 1
Data Format
0 0
Byte data
Address L
MSB
LSB
Word data
Address 2M Address 2M+1
MSB LSB
Longword data
Address 2N Address 2N+1 Address 2N+2 Address 2N+3
MSB
LSB
Figure 2.10 Memory Data Formats
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Section 2 CPU
2.6
Instruction Set
The H8S/2600 CPU has 69 instructions. The instructions are classified by function in table 2.1. Table 2.1
Function Data transfer
Instruction Classification
Instructions MOV POP* , PUSH* LDM, STM MOVFPE* , MOVTPE*
3 3 1 1
Size
Types
B/W/L 5 W/L L B B/W/L 23 B B/W/L L B/W W/L B B/W/L 4
Arithmetic operation
ADD, SUB, CMP, NEG ADDX, SUBX, DAA, DAS INC, DEC ADDS, SUBS MULXU, DIVXU, MULXS, DIVXS EXTU, EXTS TAS*
4
MAC, LDMAC, STMAC, CLRMAC Logic operations Shift Bit manipulation Branch System control AND, OR, XOR, NOT
SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR B/W/L 8 BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR Bcc* , JMP, BSR, JSR, RTS
2
B
14 5 9 1 Total: 69
TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP
Block data transfer EEPMOV
Notes: B-byte; W-word; L-longword. 1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+,Rn and MOV.W Rn,@-SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+,ERn and MOV.L ERn,@-SP. 2. Bcc is the general name for conditional branch instructions. 3. Cannot be used in this LSI. 4. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.
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Section 2 CPU
2.6.1
Table of Instructions Classified by Function
Tables 2.3 to 2.10 summarize the instructions in each functional category. The notation used in tables 2.3 to 2.10 is defined below. Table 2.2
Symbol Rd Rs Rn ERn MAC (EAd) (EAs) EXR CCR N Z V C PC SP #IMM disp + - x /
Operation Notation
Description General register (destination)* General register (source)* General register* General register (32-bit register) Multiply-accumulate register (32-bit register) Destination operand Source operand Extended control register Condition-code register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR Program counter Stack pointer Immediate data Displacement Addition Subtraction Multiplication Division Logical AND Logical OR Logical XOR Move NOT (logical complement) 8-, 16-, 24-, or 32-bit length
:8/:16/:24/:32 Note: *
General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit registers (ER0 to ER7).
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Section 2 CPU
Table 2.3
Instruction MOV
Data Transfer Instructions
Size* B/W/L Function (EAs) Rd, Rs (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. Cannot be used in this LSI. Cannot be used in this LSI. @SP+ Rn Pops a general register from the stack. POP.W Rn is identical to MOV.W @SP+, Rn. POP.L ERn is identical to MOV.L @SP+, ERn. Rn @-SP Pushes a general register onto the stack. PUSH.W Rn is identical to MOV.W Rn, @-SP. PUSH.L ERn is identical to MOV.L ERn, @-SP. @SP+ Rn (register list) Pops two or more general registers from the stack. Rn (register list) @-SP Pushes two or more general registers onto the stack.
MOVFPE MOVTPE POP
B B W/L
PUSH
W/L
LDM STM Note: *
L L
Refers to the operand size. B: Byte W: Word L: Longword
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Section 2 CPU
Table 2.4
Instruction ADD SUB
Arithmetic Operations Instructions (1)
Size* B/W/L Function Rd Rs Rd, Rd #IMM Rd Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register (immediate byte data cannot be subtracted from byte data in a general register. Use the SUBX or ADD instruction.) Rd Rs C Rd, Rd #IMM C Rd Performs addition or subtraction with carry on byte data in two general registers, or on immediate data and data in a general register. Rd 1 Rd, Rd 2 Rd Increments or decrements a general register by 1 or 2. (Byte operands can be incremented or decremented by 1 only.) Rd 1 Rd, Rd 2 Rd, Rd 4 Rd Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register. Rd decimal adjust Rd Decimal-adjusts an addition or subtraction result in a general register by referring to the CCR to produce 4-bit BCD data. Rd x Rs Rd Performs unsigned multiplication on data in two general registers: either 8 bits x 8 bits 16 bits or 16 bits x 16 bits 32 bits. Rd x Rs Rd Performs signed multiplication on data in two general registers: either 8 bits x 8 bits 16 bits or 16 bits x 16 bits 32 bits. Rd / Rs Rd Performs unsigned division on data in two general registers: either 16 bits / 8 bits 8-bit quotient and 8-bit remainder or 32 bits / 16 bits 16-bit quotient and 16-bit remainder.
ADDX SUBX INC DEC ADDS SUBS DAA DAS MULXU
B
B/W/L
L B
B/W
MULXS
B/W
DIVXU
B/W
Note:
*
Refers to the operand size. B: Byte W: Word L: Longword
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Section 2 CPU
Table 2.4
Instruction DIVXS
Arithmetic Operations Instructions (2)
Size* B/W
1
Function Rd / Rs Rd Performs signed division on data in two general registers: either 16 bits / 8 bits 8-bit quotient and 8-bit remainder or 32 bits / 16 bits 16-bit quotient and 16-bit remainder. Rd - Rs, Rd - #IMM Compares data in a general register with data in another general register or with immediate data, and sets CCR bits according to the result. 0 - Rd Rd Takes the two's complement (arithmetic complement) of data in a general register. Rd (zero extension) Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by padding with zeros on the left. Rd (sign extension) Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by extending the sign bit. @ERd - 0, 1 ( of @ERd) Tests memory contents, and sets the most significant bit (bit 7) to 1. (EAs) x (EAd) + MAC MAC Performs signed multiplication on memory contents and adds the result to the multiply-accumulate register. The following operations can be performed: 16 bits x 16 bits + 32 bits 32 bits, saturating 16 bits x 16 bits + 42 bits 42 bits, non-saturating 0 MAC Clears the multiply-accumulate register to zero. Rs MAC, MAC Rd Transfers data between a general register and a multiply-accumulate register.
CMP
B/W/L
NEG
B/W/L
EXTU
W/L
EXTS
W/L
TAS* MAC
2
B
CLRMAC LDMAC STMAC Note:
L
1. Refers to the operand size. B: Byte W: Word L: Longword 2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.
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Section 2 CPU
Table 2.5
Instruction AND
Logic Operations Instructions
Size* B/W/L Function Rd Rs Rd, Rd #IMM Rd Performs a logical AND operation on a general register and another general register or immediate data. Rd Rs Rd, Rd #IMM Rd Performs a logical OR operation on a general register and another general register or immediate data. Rd Rs Rd, Rd #IMM Rd Performs a logical exclusive OR operation on a general register and another general register or immediate data.
OR
B/W/L
XOR
B/W/L
NOT
B/W/L
(Rd) (Rd)
Takes the one's complement (logical complement) of general register contents.
Note:
*
Refers to the operand size. B: Byte W: Word L: Longword
Table 2.6
Instruction SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR Note: *
Shift Instructions
Size* B/W/L Function Rd (shift) Rd Performs an arithmetic shift on general register contents. 1-bit or 2-bit shifts are possible. Rd (shift) Rd Performs a logical shift on general register contents. 1-bit or 2-bit shifts are possible. Rd (rotate) Rd Rotates general register contents. 1-bit or 2-bit rotations are possible. Rd (rotate) Rd Rotates general register contents through the carry flag. 1-bit or 2-bit rotations are possible.
B/W/L
B/W/L
B/W/L
Refers to the operand size. B: Byte W: Word L: Longword
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Section 2 CPU
Table 2.7
Instruction BSET
Bit Manipulation Instructions (1)
Size* B Function 1 ( of ) Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. 0 ( of ) Clears a specified bit in a general register or memory operand to 0. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.
BCLR
B
BNOT
B
( of ) ( of )
Inverts a specified bit in a general register or memory operand. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.
BTST
B
( of ) Z
Tests a specified bit in a general register or memory operand and sets or clears the Z flag accordingly. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.
BAND
B
C ( of ) C ANDs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. C [( of )] C ANDs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. C ( of ) C ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. C [( of )] C ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data.
BIAND
B
BOR
B
BIOR
B
Note:
*
Refers to the operand size. B: Byte
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Section 2 CPU
Table 2.7
Instruction BXOR
Bit Manipulation Instructions (2)
Size* B
1
Function C ( of ) C XORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. C [( of )] C XORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. ( of ) C Transfers a specified bit in a general register or memory operand to the carry flag.
BIXOR
B
BLD
B
BILD
B
( of ) C
Transfers the inverse of a specified bit in a general register or memory operand to the carry flag. The bit number is specified by 3-bit immediate data.
BST
B
C ( of ) Transfers the carry flag value to a specified bit in a general register or memory operand.
BIST
B
C ( of )
Transfers the inverse of the carry flag value to a specified bit in a general register or memory operand. The bit number is specified by 3-bit immediate data.
Note:
*
Refers to the operand size. B: Byte
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Section 2 CPU
Table 2.8
Instruction Bcc
Branch Instructions
Size Function Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic BRA(BT) BRN(BF) BHI BLS BCC(BHS) BCS(BLO) BNE BEQ BVC BVS BPL BMI BGE BLT BGT BLE Description Always (true) Never (false) High Low or same Carry clear (high or same) Carry set (low) Not equal Equal Overflow clear Overflow set Plus Minus Greater or equal Less than Greater than Less or equal Condition Always Never CZ=0 CZ=1 C=0 C=1 Z=0 Z=1 V=0 V=1 N=0 N=1 NV=0 NV=1 Z(N V) = 0 Z(N V) = 1
JMP BSR JSR RTS

Branches unconditionally to a specified address. Branches to a subroutine at a specified address. Branches to a subroutine at a specified address. Returns from a subroutine
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Section 2 CPU
Table 2.9
Instruction TRAPA RTE SLEEP LDC
System Control Instructions
Size* B/W Function Starts trap-instruction exception handling. Returns from an exception-handling routine. Causes a transition to a power-down state. (EAs) CCR, (EAs) EXR Moves general register or memory contents or immediate data to CCR or EXR. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid. CCR (EAd), EXR (EAd) Transfers CCR or EXR contents to a general register or memory. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid. CCR #IMM CCR, EXR #IMM EXR Logically ANDs the CCR or EXR contents with immediate data. CCR #IMM CCR, EXR #IMM EXR Logically ORs the CCR or EXR contents with immediate data. CCR #IMM CCR, EXR #IMM EXR Logically XORs the CCR or EXR contents with immediate data. PC + 2 PC Only increments the program counter.
STC
B/W
ANDC ORC XORC NOP Note: *
B B B
Refers to the operand size. B: Byte W: Word
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Section 2 CPU
Table 2.10 Block Data Transfer Instructions
Instruction EEPMOV.B Size Function if R4L 0 then Repeat @ER5+ @ER6+ R4L-1 R4L Until R4L = 0 else next; if R4 0 then Repeat @ER5+ @ER6+ R4-1 R4 Until R4 = 0 else next; Transfers a data block. Starting from the address set in ER5, transfers data for the number of bytes set in R4L or R4 to the address location set in ER6. Execution of the next instruction begins as soon as the transfer is completed.
EEPMOV.W
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Section 2 CPU
2.6.2
Basic Instruction Formats
The H8S/2600 CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op field), a register field (r field), an effective address extension (EA field), and a condition field (cc). Figure 2.11 shows examples of instruction formats. * Operation Field Indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand. The operation field always includes the first four bits of the instruction. Some instructions have two operation fields. * Register Field Specifies a general register. Address registers are specified by 3 bits, and data registers by 3 bits or 4 bits. Some instructions have two register fields. Some have no register field. * Effective Address Extension 8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. * Condition Field Specifies the branching condition of Bcc instructions.
(1) Operation field only op NOP, RTS, etc.
(2) Operation field and register fields op rn rm ADD.B Rn, Rm, etc.
(3) Operation field, register fields, and effective address extension op EA(disp) rn rm MOV.B @(d:16, Rn), Rm, etc.
(4) Operation field, effective address extension, and condition field op cc EA(disp) BRA d:16, etc.
Figure 2.11 Instruction Formats (Examples)
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Section 2 CPU
2.7
Addressing Modes and Effective Address Calculation
The H8S/2600 CPU supports the eight addressing modes listed in table 2.11. Each instruction uses a subset of these addressing modes. Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer instructions can use all addressing modes except programcounter relative and memory indirect. Bit manipulation instructions use register direct, register indirect, or the absolute addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand. Table 2.11 Addressing Modes
No. 1 2 3 4 5 6 7 8 Addressing Mode Register direct Register indirect Register indirect with displacement Register indirect with post-increment Register indirect with pre-decrement Absolute address Immediate Program-counter relative Memory indirect Symbol Rn @ERn @(d:16,ERn)/@(d:32,ERn) @ERn+ @-ERn @aa:8/@aa:16/@aa:24/@aa:32 #xx:8/#xx:16/#xx:32 @(d:8,PC)/@(d:16,PC) @@aa:8
2.7.1
Register DirectRn
The register field of the instruction specifies an 8-, 16-, or 32-bit general register containing the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers. 2.7.2 Register Indirect@ERn
The register field of the instruction code specifies an address register (ERn) which contains the address of the operand on memory. If the address is a program instruction address, the lower 24 bits are valid and the upper 8 bits are all assumed to be 0 (H'00).
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Section 2 CPU
2.7.3
Register Indirect with Displacement@(d:16, ERn) or @(d:32, ERn)
A 16-bit or 32-bit displacement contained in the instruction is added to an address register (ERn) specified by the register field of the instruction, and the sum gives the address of a memory operand. A 16-bit displacement is sign-extended when added. 2.7.4 Register Indirect with Post-Increment or Pre-Decrement@ERn+ or @-ERn
Register indirect with post-increment@ERn+: The register field of the instruction code specifies an address register (ERn) which contains the address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the address register. The value added is 1 for byte access, 2 for word transfer instruction, or 4 for longword transfer instruction. For the word or longword transfer instructions, the register value should be even. Register indirect with pre-decrement@-ERn: The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field in the instruction code, and the result is the address of a memory operand. The result is also stored in the address register. The value subtracted is 1 for byte access, 2 for word transfer instruction, or 4 for longword transfer instruction. For the word or longword transfer instructions, the register value should be even. 2.7.5 Absolute Address@aa:8, @aa:16, @aa:24, or @aa:32
The instruction code contains the absolute address of a memory operand. The absolute address may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24), or 32 bits long (@aa:32). Table 2.12 indicates the accessible absolute address ranges. To access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits (@aa:32) long. For an 8-bit absolute address, the upper 24 bits are all assumed to be 1 (H'FFFF). For a 16-bit absolute address the upper 16 bits are a sign extension. A 32-bit absolute address can access the entire address space. A 24-bit absolute address (@aa:24) indicates the address of a program instruction. The upper 8 bits are all assumed to be 0 (H'00).
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Section 2 CPU
Table 2.12 Absolute Address Access Ranges
Absolute Address Data address 8 bits (@aa:8) 16 bits (@aa:16) 32 bits (@aa:32) Program instruction address 24 bits (@aa:24) Normal Mode* H'FF00 to H'FFFF H'0000 to H'FFFF Advanced Mode H'FFFF00 to H'FFFFFF H'000000 to H'007FFF, H'FF8000 to H'FFFFFF H'000000 to H'FFFFFF
Note: Normal mode is not available in this LSI.
2.7.6
Immediate#xx:8, #xx:16, or #xx:32
The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a vector address. 2.7.7 Program-Counter Relative@(d:8, PC) or @(d:16, PC)
This mode is used in the Bcc and BSR instructions. An 8-bit or 16-bit displacement contained in the instruction is sign-extended and added to the 24-bit PC contents to generate a branch address. Only the lower 24 bits of this branch address are valid; the upper 8 bits are all assumed to be 0 (H00). The PC value to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is -126 to +128 bytes (-63 to +64 words) or -32766 to +32768 bytes (-16383 to +16384 words) from the branch instruction. The resulting value should be an even number.
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Section 2 CPU
2.7.8
Memory Indirect@@aa:8
This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit absolute address specifying a memory operand. This memory operand contains a branch address. The upper bits of the absolute address are all assumed to be 0, so the address range is 0 to 255 (H'0000 to H'00FF in normal mode, H'000000 to H'0000FF in advanced mode). In normal mode, the memory operand is a word operand and the branch address is 16 bits long. In advanced mode, the memory operand is a longword operand, the first byte of which is assumed to be 0 (H'00). Note that the first part of the address range is also the exception vector area. For further details, refer to section 4, Exception Handling. If an odd address is specified in word or longword memory access, or as a branch address, the least significant bit is regarded as 0, causing data to be accessed or instruction code to be fetched at the address preceding the specified address. (For further information, see section 2.5.2, Memory Data Formats.) Note: Normal mode is not available in this LSI.
Specified by @aa:8
Branch address
Specified by @aa:8
Reserved Branch address
(a) Normal Mode*
Note: * Normal mode is not available in this LSI.
(a) Advanced Mode
Figure 2.12 Branch Address Specification in Memory Indirect Mode
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Section 2 CPU
2.7.9
Effective Address Calculation
Table 2.13 indicates how effective addresses are calculated in each addressing mode. In normal mode the upper 8 bits of the effective address are ignored in order to generate a 16-bit address. Note: Normal mode is not available in this LSI. Table 2.13 Effective Address Calculation (1)
No 1
Addressing Mode and Instruction Format
Register direct(Rn)
Effective Address Calculation
Effective Address (EA)
Operand is general register contents.
op 2
rm
rn 31
General register contents
Register indirect(@ERn)
0
31
24 23
0
Don't care
op 3
r
Register indirect with displacement @(d:16,ERn) or @(d:32,ERn)
31
General register contents
0 31 24 23 0
op
r
disp 31
Sign extension
Don't care 0 disp
4
Register indirect with post-increment or pre-decrement *Register indirect with post-increment @ERn+
31
General register contents
0
31
24 23
0
Don't care
op
r 31
1, 2, or 4
*Register indirect with pre-decrement @-ERn
0
General register contents
31
24 23
0
Don't care op r
Operand Size Byte Word Longword 1, 2, or 4
Offset 1 2 4
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Section 2 CPU
Table 2.13 Effective Address Calculation (2)
No 5
Addressing Mode and Instruction Format
Absolute address
Effective Address Calculation
Effective Address (EA)
@aa:8 op abs
31
24 23 H'FFFF
87
0
Don't care
@aa:16 op abs
31
24 23
16 15
0
Don't care Sign extension
@aa:24 op abs
31
24 23
0
Don't care
@aa:32 op abs 31 24 23 0
Don't care
6
Immediate
#xx:8/#xx:16/#xx:32 op IMM
Operand is immediate data.
7
Program-counter relative @(d:8,PC)/@(d:16,PC)
23
PC contents
0
op
disp
23
Sign extension
0 disp 31 24 23 0
Don't care
8
Memory indirect @@aa:8 * Normal mode*
31 op abs H'000000 15
87 abs
0
0
Memory contents
31
24 23
16 15 H'00
0
Don't care
* Advanced mode
31 op abs 31
Memory contents
87 H'000000 abs
0 31 24 23 Don't care 0
0
Note: * Normal mode is not available in this LSI.
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Section 2 CPU
2.8
Processing States
The H8S/2600 CPU has four main processing states: the reset state, exception handling state, program execution state and power-down state. Figure 2.13 indicates the state transitions. * Reset State In this state, the CPU and all on-chip peripheral modules are initialized and not operating. When the RES input goes low, all current processing stops and the CPU enters the reset state. All interrupts are masked in the reset state. Reset exception handling starts when the RES signal changes from low to high. For details, refer to section 4, Exception Handling. The reset state can also be entered by a watchdog timer overflow. * Exception-Handling State The exception-handling state is a transient state that occurs when the CPU alters the normal processing flow due to an exception source, such as a reset, trace, interrupt, or trap instruction. The CPU fetches a start address (vector) from the exception vector table and branches to that address. For further details, refer to section 4, Exception Handling. * Program Execution State In this state, the CPU executes program instructions in sequence. * Program Stop State This is a power-down state in which the CPU stops operating. The program stop state occurs when a SLEEP instruction is executed or the CPU enters software standby mode. For further details, refer to section 28, Power-Down Modes.
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Section 2 CPU
End of bus request
Bus request
Program execution state
End of bus request
Bus request
SLEEP instruction with PSS = 0 and SSBY = 1
SLEEP instruction with SSBY = 0
Bus-released state
End of exception handling
Request for exception handling
Sleep mode
Interrupt request
Exception-handling state
External interrupt request
RES = high
Software standby mode
Reset state*1
STBY = High, RES = Low
Hardware standby mode*2 Power-down state
Notes: 1. From any state except hardware standby mode, a transition to the reset state occurs whenever RES goes low. A transition can also be made to the reset state when the watchdog timer overflows. 2. From any state, a transition to hardware standby mode occurs when STBY goes low.
Figure 2.13 State Transitions
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Section 2 CPU
2.9
2.9.1
Usage Note
Notes on Using the Bit Operation Instruction
Instructions BSET, BCLR, BNOT, BST, and BIST read data in byte units, and write data in byte units after bit operation. Therefore, attention must be paid when these instructions are used for ports or registers including write-only bits. Instruction BCLR can be used to clear the flag in the internal I/O register to 0. If it is obvious that the flag has been set to 1 by the interrupt processing routine, it is unnecessary to read the flag beforehand.
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Section 2 CPU
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Section 3 MCU Operating Modes
Section 3 MCU Operating Modes
3.1 Operating Mode Selection
This LSI supports one operating mode (mode 2). The operating mode is determined by the setting of the mode pins (MD2 and MD1). Table 3.1 shows the MCU operating mode selection. Table 3.1 MCU Operating Mode Selection
MD2 1 CPU Operating Description MD1 Mode 1 Advanced Extended mode with on-chip ROM Single-chip mode
MCU Operating Mode 2
Mode 2 is single-chip mode after a reset. The CPU can switch to extended mode by setting bit EXPE in MDCR to 1. Modes 0, 1, 3, 5, and 7 are not available in this LSI. Modes 4 and 6 are operating mode for a special purpose. Thus, mode pins should be set to enable mode 2 in normal program execution state. Mode pins should not be changed during operation.
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Section 3 MCU Operating Modes
3.2
Register Descriptions
The following registers are related to the operating mode. For details on the bus control register (BCR), see section 6.3.1, Bus Control Register (BCR), and for details on bus control register 2 (BCR2), see section 6.3.2, Bus Control Register 2 (BCR2). * Mode control register (MDCR) * System control register (SYSCR) * Serial timer control register (STCR) 3.2.1 Mode Control Register (MDCR)
MDCR is used to set an operating mode and to monitor the current operating mode.
Bit 7 Bit Name EXPE Initial Value 0 R/W R/W Description Extended Mode Enable Specifies extended mode. 0: Single-chip mode 1: Extended mode 6 to 3 2 1 MDS2 MDS1 All 0 * * R R R Reserved Mode Select 2 and 1 These bits indicate the input levels at mode pins (MD2 and MD1) (the current operating mode). Bits MDS2 and MDS1 correspond to MD2 and MD1, respectively. MDS2 and MDS1 are read-only bits and they cannot be written to. The mode pin (MD2 and MD1) input levels are latched into these bits when MDCR is read. These latches are canceled by a reset. Reserved
0 Note:
*
R
The initial values are determined by the settings of the MD2 and MD1 pins.
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Section 3 MCU Operating Modes
3.2.2
System Control Register (SYSCR)
SYSCR selects a system pin function, monitors a reset source, selects the interrupt control mode and the detection edge for NMI, enables or disables register access to the on-chip peripheral modules, and enables or disables on-chip RAM address space.
Bit 7 Bit Name CS256E Initial Value 0 R/W R/W Description Chip Select 256 Enable Enables or disables P97/WAIT/CS256 pin function in extended mode. 0: P97/WAIT pin WAIT pin function is selected by the settings of WSCR and WSCR2. 1: CS256 pin Outputs low when a 256-kbyte expansion area of addresses H'F80000 to H'FBFFFF is accessed. 6 IOSE 0 R/W IOS Enable Enables or disables AS/IOS pin function in extended mode. 0: AS pin Outputs low when an external area is accessed. 1: IOS pin Outputs low when an IOS expansion area of addresses H'FFF000 to H'FFF7FF is accessed. 5 4 INTM1 INTM0 0 0 R R/W These bits select the control mode of the interrupt controller. For details on the interrupt control modes, see section 5.6, Interrupt Control Modes and Interrupt Operation. 00: Interrupt control mode 0 01: Interrupt control mode 1 10: Setting prohibited 11: Setting prohibited
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Section 3 MCU Operating Modes
Bit 3
Bit Name XRST
Initial Value 1
R/W R
Description External Reset This bit indicates the reset source. A reset is caused by an external reset input, or when the watchdog timer overflows. 0: A reset is caused when the watchdog timer overflows. 1: A reset is caused by an external reset.
2
NMIEG
0
R/W
NMI Edge Select Selects the valid edge of the NMI interrupt input. 0: An interrupt is requested at the falling edge of NMI input 1: An interrupt is requested at the rising edge of NMI input
1 0
RAME
0 1
R/W R/W
Reserved The initial value should not be changed. RAM Enable Enables or disables on-chip RAM. The RAME bit is initialized when the reset state is released. 0: On-chip RAM is disabled 1: On-chip RAM is enabled
3.2.3
Serial Timer Control Register (STCR)
STCR enables or disables register access, IIC operating mode, and on-chip flash memory, and selects the input clock of the timer counter.
Bit 7 6 5 Bit Name IICX2 IICX1 IICX0 Initial Value 0 0 0 R/W R/W R/W R/W Description IIC Transfer Rate Select 2, 1, and 0 These bits control the IIC operation. These bits select a transfer rate in master mode together with bits CKS2 to 2 CKS0 in the I C bus mode register (ICMR). For details on the transfer rate, see table 18.3.
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Section 3 MCU Operating Modes
Bit 4 3
Bit Name FLSHE
Initial Value 0 0
R/W R/W R/W
Description Reserved The initial value should not be changed. Flash Memory Control Register Enable Enables or disables CPU access for flash memory registers (FCCS, FPCS, FECS, FKEY, FMATS, FTDAR), control registers of power-down states (SBYCR, LPWRCR, MSTPCRH, MSTPCRL), and control registers of on-chip peripheral modules (BCR2, WSCR2, PCSR, SYSCR2). 0: Area from H'FFFE88 to H'FFFE8F is reserved. Area from H'FFFEA0 to H'FFFEBF is allocated to registers of AD, serial multiplexed functions, and I/O ports. Area from H'FFFF80 to H'FFFF87 is allocated to control registers of power-down states and on-chip peripheral modules. 1: Area from H'FFFE88 to H'FFFE8F is allocated to control registers of flash memory. Area from H'FFFEA0 to H'FFFEBF is reserved. Area from H'FFFF80 to H'FFFF87 is reserved.
2 1 0
ICKS1 ICKS0
1 0 0
R/(W) R/W R/W
Reserved The initial value should not be changed. Internal Clock Source Select 1, 0 These bits select a clock to be input to the timer counter (TCNT) and a count condition together with bits CKS2 to CKS0 in the timer control register (TCR). For details, see section 11.2.4, Timer Control Register (TCR).
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Section 3 MCU Operating Modes
3.3
3.3.1
Operating Mode Descriptions
Mode 2
The CPU can access a 16 Mbytes address space in advanced mode. The on-chip ROM is enabled. After a reset, the LSI is set to single-chip mode. To access an external address space, bit EXPE in MDCR should be set to 1. * Normal extended mode In extended mode, ports 1, 2 (P23 to P20), and 4 (P47 to P44) function as input ports after a reset. Ports 1 and 2 function as an address bus by setting 1 to the corresponding port data direction register (DDR). Port 3 functions as a data bus port, and parts of port 9 and port C carry bus control signals. Ports 4 (P43 to P40) and 6 (P63 to P60) function as a data bus port when the ABW bit in WSCR is cleared to 0. * Multiplex extended mode When 8-bit bus is specified, port 1 functions as the port for address output and data input/output regardless of the setting of the data direction register (DDR). Ports 2 (P23 to P20) and 4 (P47 to P44) can be used as a general port. When 16-bit bus is specified, ports 1, 2 (P23 to P20), and 4 (P47 to P44) function as the port for address output and data input/output regardless of the setting of the data direction register (DDR).
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Section 3 MCU Operating Modes
3.4
Address Map
Figure 3.1 shows the memory map in operating modes.
ROM: 512 Kbytes, RAM: 40 Kbytes Mode 2 (EXPE = 1) Advanced mode Extended mode with on-chip ROM H'000000 ROM: 512 Kbytes, RAM: 40 Kbytes Mode 2 (EXPE = 0) Advanced mode Single-chip mode H'000000
On-chip ROM
On-chip ROM
H'07FFFF H'080000 H'F7FFFF H'F80000 H'FBFFFF H'FC0000 H'FEFFFF H'FF0000 H'FF07FF H'FF0800
H'07FFFF External address space 256 Kbytes extended area External address space Reserved area On-chip RAM* (36 Kbytes) H'FF0000 H'FF07FF H'FF0800 Reserved area On-chip RAM (36 Kbytes) H'FF97FF H'FF9800 Reserved area Reserved area * H'FFBFFF
H'FF97FF H'FF9800
H'FFDFFF H'FFE000 H'FFE07F H'FFE080 H'FFEFFF H'FFF000 H'FFF7FF H'FFF800 H'FFFE3F H'FFFE40 H'FFFEFF H'FFFF00 H'FFFF7F H'FFFF80 H'FFFFFF
External address space On-chip RAM* (3,968 bytes)
External address space (IOS extended area)
H'FFE080 H'FFEFFF H'FFF800 H'FFFE3F H'FFFE40 H'FFFEFF H'FFFF00 H'FFFF7F H'FFFF80 H'FFFFFF
On-chip RAM (3,968 bytes)
Internal I/O registers 3 Internal I/O registers 2 On-chip RAM* (128 bytes) Internal I/O registers 1
Internal I/O registers 3 Internal I/O registers 2 On-chip RAM (128 bytes) Internal I/O registers 1
Notes: * These areas can be used as an external address space by clearing bit RAME in SYSCR to 0.
Figure 3.1 Address Map
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Section 3 MCU Operating Modes
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Section 4 Exception Handling
Section 4 Exception Handling
4.1 Exception Handling Types and Priority
As table 4.1 indicates, exception handling may be caused by a reset, interrupt, illegal instruction, or trap instruction. Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur simultaneously, they are accepted and processed in order of priority. Table 4.1
Priority High
Exception Types and Priority
Exception Type Reset Illegal instruction Interrupt Start of Exception Handling Starts immediately after a low-to-high transition of the RES pin, or when the watchdog timer overflows. Started by execution of an undefined code. Starts when execution of the current instruction or exception handling ends, if an interrupt request has been issued. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC instruction execution, or on completion of reset exception handling. Started by execution of a trap (TRAPA) instruction. Trap instruction exception handling requests are accepted at all times in program execution state.
Trap instruction Low
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Section 4 Exception Handling
4.2
Exception Sources and Exception Vector Table
Different vector addresses are assigned to different exception sources. Table 4.2 lists the exception sources and their vector addresses. Table 4.2 Exception Handling Vector Table
Vector Address Exception Source Reset Reserved for system use Vector Number 0 1 3 4 5 6 External interrupt (NMI) Trap instruction (four sources) 7 8 9 10 11 Reserved for system use 12 15 16 17 18 19 20 21 22 23 24 29 Advanced Mode H'000000 to H'000003 H'000004 to H'000007 | H'00000C to H'00000F H'000010 to H'000013 H'000014 to H'000017 H'000018 to H'00001B H'00001C to H'00001F H'000020 to H'000023 H'000024 to H'000027 H'000028 to H'00002B H'00002C to H'00002F H'000030 to H'000033 | H'00003C to H'00003F H'000040 to H'000043 H'000044 to H'000047 H'000048 to H'00004B H'00004C to H'00004F H'000050 to H'000053 H'000054 to H'000057 H'000058 to H'00005B H'00005C to H'00005F H'000060 to H'000063 H'000074 to H'000077
Illegal instruction Reserved for system use
External interrupt IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 Internal interrupt*
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Section 4 Exception Handling
Vector Address Exception Source Reserved for system use Vector Number 30 33 Internal interrupt* 34 55 56 57 58 59 60 61 62 63 64 119 Advanced Mode H'000078 to H'00007B H'000084 to H'000087 H'000088 to H'00008B H'0000DC to H'0000DF H'0000E0 to H'0000E3 H'0000E4 to H'0000E7 H'0000E8 to H'0000EB H'0000EC to H'0000EF H'0000F0 to H'0000F3 H'0000F4 to H'0000F7 H'0000F8 to H'0000FB H'0000FC to H'0000FF H'000100 to H'000103 H'0001DC to H'0001DF
External interrupt IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 Internal interrupt*
Note:
*
For details on the internal interrupt vector table, see section 5.5, Interrupt Exception Handling Vector Table.
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Section 4 Exception Handling
4.3
Reset
A reset has the highest exception priority. When the RES pin goes low, all processing halts and this LSI enters the reset. To ensure that this LSI is reset, hold the RES pin low for at least 20 ms at power-on. To reset the chip during operation, hold the RES pin low for at least 20 states. A reset initializes the internal state of the CPU and the registers of on-chip peripheral modules. The chip can also be reset by overflow of the watchdog timer. For details, see section 12, Watchdog Timer (WDT). 4.3.1 Reset Exception Handling
When the RES pin goes high after being held low for the necessary time, this LSI starts reset exception handling as follows: 1. The internal state of the CPU and the registers of the on-chip peripheral modules are initialized and the I bit in CCR is set to 1. 2. The reset exception handling vector address is read and transferred to the PC, and program execution starts from the address indicated by the PC. Figure 4.1 shows an example of the reset sequence.
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Section 4 Exception Handling
Vector fetch
Internal processing
Prefetch of first program instruction
RES
Internal address bus
(1) U
(1) L
(3)
Internal read signal
Internal write signal
High
Internal data bus
(2) U
(2) L
(4)
(1) Reset exception handling vector address (1) U = H'000000 (1) L = H'000002 (2) Start address (contents of reset exception handling vector address) (3) Start address ((3) = (2)U + (2)L) (4) First program instruction
Figure 4.1 Reset Sequence 4.3.2 Interrupts after Reset
If an interrupt is accepted after a reset and before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, including NMI, are disabled immediately after a reset. Since the first instruction of a program is always executed immediately after the reset state ends, make sure that this instruction initializes the stack pointer (example: MOV.L #xx: 32, SP). 4.3.3 On-Chip Peripheral Modules after Reset is Cancelled
After a reset is cancelled, the module stop control registers (MSTPCR, MSTPCRA, and SUBMSTPB) are initialized, and all modules except the DTC operate in module stop mode. Therefore, the registers of on-chip peripheral modules cannot be read from or written to. To read from and write to these registers, clear module stop mode.
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Section 4 Exception Handling
4.4
Interrupt Exception Handling
Interrupts are controlled by the interrupt controller. The sources to start interrupt exception handling are external interrupt sources (NMI and IRQ15 to IRQ0) and internal interrupt sources from the on-chip peripheral modules. NMI is an interrupt with the highest priority. For details, see section 5, Interrupt Controller. Interrupt exception handling is conducted as follows: 1. The values in the program counter (PC) and condition code register (CCR) are saved to the stack. 2. A vector address corresponding to the interrupt source is generated, the start address is loaded from the vector table to the PC, and program execution begins from that address.
4.5
Trap Instruction Exception Handling
Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. Trap instruction exception handling is conducted as follows: 1. The values in the program counter (PC) and condition code register (CCR) are saved to the stack. 2. A vector address corresponding to the interrupt source is generated, the start address is loaded from the vector table to the PC, and program execution starts from that address. The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector number from 0 to 3, as specified in the instruction code. Table 4.3 shows the status of CCR after execution of trap instruction exception handling. Table 4.3 Status of CCR after Trap Instruction Exception Handling
CCR Interrupt Control Mode 0 1 I Set to 1 Set to 1 UI Retains value prior to execution Set to 1
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Section 4 Exception Handling
4.6
Stack Status after Exception Handling
Figure 4.2 shows the stack after completion of trap instruction exception handling and interrupt exception handling.
Advanced mode
SP
CCR PC (24 bits)
Figure 4.2 Stack Status after Exception Handling
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Section 4 Exception Handling
4.7
Usage Note
When accessing word data or longword data, this LSI assumes that the lowest address bit is 0. The stack should always be accessed in words or longwords, and the value of the stack pointer (SP: ER7) should always be kept even. Use the following instructions to save registers:
PUSH.W PUSH.L Rn ERn
(or MOV.W Rn, @-SP) (or MOV.L ERn, @-SP)
Use the following instructions to restore registers:
POP.W POP.L Rn ERn
(or MOV.W @SP+, Rn) (or MOV.L @SP+, ERn)
Setting SP to an odd value may lead to a malfunction. Figure 4.3 shows an example of what happens when the SP value is odd.
Address
CCR SP PC
SP
R1L PC
H'FFFEFA H'FFFEFB H'FFFEFC H'FFFEFD
SP
H'FFFEFF
TRAPA instruction executed SP set to H'FFFEFF [Legend] CCR: PC: R1L: SP: Condition code register Program counter General register R1L Stack pointer
MOV.B R1L, @-ER7 executed Contents of CCR lost
Data saved above SP
Note: This diagram illustrates an example in which the interrupt control mode is 0.
Figure 4.3 Operation When SP Value is Odd
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Section 5 Interrupt Controller
Section 5 Interrupt Controller
5.1 Features
* Two interrupt control modes Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the system control register (SYSCR). * Priorities settable with ICR An interrupt control register (ICR) is provided for setting interrupt priorities. Priority levels can be set for each module for all interrupts except NMI. * Three-level interrupt mask control By means of the interrupt control mode, I and UI bits in CCR, and ICR, 3-level interrupt mask control is performed. * Independent vector addresses All interrupt sources are assigned independent vector addresses, making it unnecessary for the source to be identified in the interrupt handling routine. * Thirty-three external interrupts NMI is the highest-priority interrupt, and is accepted at all times. Rising edge or falling edge detection can be selected for NMI. Falling-edge, rising-edge, or both-edge detection, or level sensing, can be selected for IRQn (n = 15 to 0) and ExIRQn (n = 15 to 0). * DTC control The DTC can be activated by an interrupt request.
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Section 5 Interrupt Controller
INTM1, INTM0 SYSCR NMIEG NMI input IRQ input NMI input IRQ input ISR ISCR IER Priority level determination I, UI Interrupt request Vector number
CPU
CCR Internal interrupt sources SWDTEND to EINT ICR Interrupt controller
[Legend] ICR: ISCR: IER: ISR: SYSCR:
Interrupt control register IRQ sense control register IRQ enable register IRQ status register System control register
Figure 5.1 Block Diagram of Interrupt Controller
5.2
Input/Output Pins
Table 5.1 summarizes the pins of the interrupt controller. Table 5.1
Symbol NMI IRQ15 to IRQ0 ExIRQ15 to ExIRQ0
Pin Configuration
I/O Input Input Function Nonmaskable external interrupt Rising edge or falling edge can be selected Maskable external interrupts Rising edge, falling edge, or both edges, or level sensing can be selected individually for each pin. Pin of IRQn or ExIRQn to input IRQn (n = 15 to 0) interrupt can be selected.
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Section 5 Interrupt Controller
5.3
Register Descriptions
The interrupt controller has the following registers. For details on the system control register (SYSCR), see section 3.2.2, System Control Register (SYSCR), and for details on the IRQ sense port select registers (ISSR16 and ISSR), see section 8.3.1, IRQ Sense Port Select Register 16 (ISSR16), IRQ Sense Port Select Register (ISSR). * Interrupt control registers A to D (ICRA to ICRD) * Address break control register (ABRKCR) * Break address registers A to C (BARA to BARC) * IRQ sense control registers (ISCR16H, ISCR16L, ISCRH, and ISCRL) * IRQ enable registers (IER16 and IER) * IRQ status registers (ISR16 and ISR) 5.3.1 Interrupt Control Registers A to D (ICRA to ICRD)
The ICR registers set interrupt control levels for interrupts other than NMI. The correspondence between interrupt sources and ICRA to ICRD settings is shown in table 5.2.
Bit 7 to 0 Bit Name ICRn7 to IRCn0 Initial Value All 0 R/W R/W Description Interrupt Control Level 0: Corresponding interrupt source is interrupt control level 0 (no priority) 1: Corresponding interrupt source is interrupt control level 1 (priority) [Legend] n: A to D
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Section 5 Interrupt Controller
Table 5.2
Bit 7 6 5 4 3 2 1 0
Correspondence between Interrupt Source and ICR
Register ICRA IRQ0 IRQ1 IRQ2, IRQ3 IRQ4, IRQ5 IRQ6, IRQ7 DTC WDT_0 WDT_1 ICRB A/D converter FRT TMR_X TMR_0 TMR_1 TMR_Y IIC_4, IIC_5 ICRC SCI_3 SCI_1 SSU IIC_0 IIC_1 IIC_2, IIC_3 LPC 1 USB* ICRD IRQ8 to IRQ11 IRQ12 to IRQ15 EtherC 2 PECI* SCIF
Bit Name ICRn7 ICRn6 ICRn5 ICRn4 ICRn3 ICRn2 ICRn1 ICRn0
[Legend] n: A to D : Reserved. The write value should always be 0. Notes: 1. Supported only by the H8S/2472 Group. 2. Supported only by the H8S/2472 Group and the H8S/2462 Group.
5.3.2
Address Break Control Register (ABRKCR)
ABRKCR controls the address breaks. When both the CMF flag and BIE flag are set to 1, an address break is requested.
Bit 7 Bit Name CMF Initial Value R/W Description Condition Match Flag Address break source flag. Indicates that an address specified by BARA to BARC is prefetched. [Clearing condition] When an exception handling is executed for an address break interrupt. [Setting condition] When an address specified by BARA to BARC is prefetched while the BIE flag is set to 1. Reserved These bits are always read as 0 and cannot be modified. Break Interrupt Enable Enables or disables address break. 0: Disabled 1: Enabled
Undefined R
6 to 1 0
BIE
All 0 0
R R/W
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Section 5 Interrupt Controller
5.3.3
Break Address Registers A to C (BARA to BARC)
The BAR registers specify an address that is to be a break address. An address in which the first byte of an instruction exists should be set as a break address. * BARA
Bit 7 to 0 Bit Name A23 to A16 Initial Value All 0 R/W R/W Description Addresses 23 to 16 The A23 to A16 bits are compared with A23 to A16 in the internal address bus.
* BARB
Bit 7 to 0 Bit Name A15 to A8 Initial Value All 0 R/W R/W Description Addresses 15 to 8 The A15 to A8 bits are compared with A15 to A8 in the internal address bus.
* BARC
Bit 7 to 1 Bit Name A7 to A1 Initial Value All 0 R/W R/W Description Addresses 7 to 1 The A7 to A1 bits are compared with A7 to A1 in the internal address bus. 0 0 R Reserved This bit is always read as 0 and cannot be modified.
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Section 5 Interrupt Controller
5.3.4
IRQ Sense Control Registers (ISCR16H, ISCR16L, ISCRH, ISCRL)
The ISCR registers select the source that generates an interrupt request at pins IRQ15 to IRQ0 or pins ExIRQ15 to ExIRQ0. * ISCR16H
Bit 7 6 5 4 3 2 1 0 Bit Name IRQ15SCB IRQ15SCA IRQ14SCB IRQ14SCA IRQ13SCB IRQ13SCA IRQ12SCB IRQ12SCA Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description IRQn Sense Control B IRQn Sense Control A 00: Interrupt request generated at low level of IRQn* or ExIRQn input 01: Interrupt request generated at falling edge of IRQn* or ExIRQn input 10: Interrupt request generated at rising edge of IRQn* or ExIRQn input 11: Interrupt request generated at both falling and rising edges of IRQn* or ExIRQn input (n = 15 to 12) Note: * IRQn stands for IRQ15 to IRQ12.
* ISCR16L
Bit 7 6 5 4 3 2 1 0 Bit Name IRQ11SCB IRQ11SCA IRQ10SCB IRQ10SCA IRQ9SCB IRQ9SCA IRQ8SCB IRQ8SCA Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description IRQn Sense Control B IRQn Sense Control A 00: Interrupt request generated at low level of IRQn* or ExIRQn input 01: Interrupt request generated at falling edge of IRQn* or ExIRQn input 10: Interrupt request generated at rising edge of IRQn* or ExIRQn input 11: Interrupt request generated at both falling and rising edges of IRQn* or ExIRQn input (n = 11 to 8) Note: * IRQn stands for IRQ11 to IRQ8.
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Section 5 Interrupt Controller
* ISCRH
Bit 7 6 5 4 3 2 1 0 Bit Name IRQ7SCB IRQ7SCA IRQ6SCB IRQ6SCA IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description IRQn Sense Control B IRQn Sense Control A 00: Interrupt request generated at low level of IRQn or ExIRQn input 01: Interrupt request generated at falling edge of IRQn or ExIRQn input 10: Interrupt request generated at rising edge of IRQn or ExIRQn input 11: Interrupt request generated at both falling and rising edges of IRQn or ExIRQn input (n = 7 to 4) Note: * IRQn stands for IRQ7 to IRQ4.
* ISCRL
Bit 7 6 5 4 3 2 1 0 Bit Name IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description IRQn Sense Control B IRQn Sense Control A 00: Interrupt request generated at low level of IRQn or ExIRQn input 01: Interrupt request generated at falling edge of IRQn or ExIRQn input 10: Interrupt request generated at rising edge of IRQn or ExIRQn input 11: Interrupt request generated at both falling and rising edges of IRQn or ExIRQn input (n = 3 to 0) Note: * IRQn stands for IRQ3 to IRQ0.
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Section 5 Interrupt Controller
5.3.5
IRQ Enable Registers (IER16, IER)
The IER registers control the enabling and disabling of interrupt requests IRQ15 to IRQ0. * IER16
Bit 7 to 0 Bit Name IRQ15E to IRQ8E Initial Value All 0 R/W R/W Description IRQn Enable (n = 15 to 8) The IRQn interrupt request is enabled when this bit is 1.
* IER
Bit 7 to 0 Bit Name IRQ7E to IRQ0E Initial Value All 0 R/W R/W Description IRQn Enable (n = 7 to 0) The IRQn interrupt request is enabled when this bit is 1.
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Section 5 Interrupt Controller
5.3.6
IRQ Status Registers (ISR16, ISR)
The ISR registers are flag registers that indicate the status of IRQ15 to IRQ0 interrupt requests. * ISR16
Bit 7 to 0 Bit Name IRQ15F to IRQ8F Initial Value All 0 R/W R/W Description [Setting condition] * When the interrupt source selected by the ISCR16 registers occurs When reading 1, then writing 0 When interrupt exception handling is executed when low-level detection is set and IRQn* or ExIRQn input is high
[Clearing conditions] * *
*
When IRQn interrupt exception handling is executed when falling-edge, rising-edge, or both-edge detection is set (n = 15 to 8) Note: * IRQn stands for IRQ15 to IRQ8.
* ISR
Bit 7 to 0 Bit Name IRQ7F to IRQ0F Initial Value All 0 R/W R/W Description [Setting condition] * When the interrupt source selected by the ISCR registers occurs When reading 1, then writing 0 When interrupt exception handling is executed when low-level detection is set and IRQn* or ExIRQn input is high When IRQn interrupt exception handling is executed when falling-edge, rising-edge, or both-edge detection is set
[Clearing conditions] * *
*
(n = 7 to 0) Note: * IRQn stands for IRQ7 to IRQ0.
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Section 5 Interrupt Controller
5.4
5.4.1
Interrupt Sources
External Interrupts
There are four external interrupts: NMI, IRQ15 to IRQ0. These interrupts can be used to restore this LSI from software standby mode. NMI Interrupt: NMI is the highest-priority interrupt, and is always accepted by the CPU regardless of the interrupt control mode or the status of the CPU interrupt mask bits. The NMIEG bit in SYSCR can be used to select whether an interrupt is requested at a rising edge or a falling edge on the NMI pin. IRQ15 to IRQ0 Interrupts: Interrupts IRQ15 to IRQ0 are requested by an input signal at pins IRQ15 to IRQ0 or pins ExIRQ15 to ExIRQ0. Interrupts IRQ15 to IRQ0 have the following features: * The interrupt exception handling for interrupt requests IRQ15 to IRQ0 can be started at an independent vector address. * Using ISCR, it is possible to select whether an interrupt is generated by a low level, falling edge, rising edge, or both edges, at pins IRQ15 to IRQ0 or pins ExIRQ15 to ExIRQ0. * Enabling or disabling of interrupt requests IRQ15 to IRQ0 can be selected with IER. * The status of interrupt requests IRQ15 to IRQ0 is indicated in ISR. ISR flags can be cleared to 0 by software. The detection of IRQ15 to IRQ0 interrupts does not depend on whether the relevant pin has been set for input or output. However, when a pin is used as an external interrupt input pin, clear the corresponding port DDR to 0 so that it is not used as an I/O pin for another function. A block diagram of interrupts IRQ15 to IRQ0 is shown in figure 5.2.
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Section 5 Interrupt Controller
IRQnE IRQnSCA, IRQnSCB IRQnF Edge/level detection circuit IRQn input or ExIRQn* input Clear signal n = 15 to 0 S R Q IRQn interrupt request
Figure 5.2 Block Diagram of Interrupts IRQ15 to IRQ0 5.4.2 Internal Interrupts
Internal interrupts issued from the on-chip peripheral modules have the following features: * For each on-chip peripheral module there are flags that indicate the interrupt request status, and enable bits that individually select enabling or disabling of these interrupts. When the enable bit for a particular interrupt source is set to 1, an interrupt request is sent to the interrupt controller. * The control level for each interrupt can be set by ICR. * The DTC can be activated by an interrupt request from an on-chip peripheral module. * An interrupt request that activates the DTC is not affected by the interrupt control mode or the status of the CPU interrupt mask bits.
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Section 5 Interrupt Controller
5.5
Interrupt Exception Handling Vector Table
Table 5.3 lists interrupt exception handling sources, vector addresses, and interrupt priorities. For default priorities, the lower the vector number, the higher the priority. Modules set at the same priority will conform to their default priorities. Priorities within a module are fixed. An interrupt control level can be specified for a module to which an ICR bit is assigned. Interrupt requests from modules that are set to interrupt control level 1 (priority) by the ICR bit setting are given priority and processed before interrupt requests from modules that are set to interrupt control level 0 (no priority). Table 5.3
Origin of Interrupt Source External pin
Interrupt Sources, Vector Addresses, and Interrupt Priorities
Vector Address Vector Number Advanced Mode 7 16 17 18 19 20 21 22 23 24 25 26 27 28 29 44 45 46 52 53 54 H'00001C H'000040 H'000044 H'000048 H'00004C H'000050 H'000054 H'000058 H'00005C H'000060 H'000064 H'000068 H'00006C H'000070 H'000074 H'0000B0 H'0000B4 H'0000B8 H'0000D0 H'0000D4 H'0000D8
Name NMI IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7
ICR
Priority High
ICRA7 ICRA6 ICRA5 ICRA4 ICRA3 ICRA2 ICRA1 ICRA0
DTC WDT_0 WDT_1
SWDTEND (Software activation data transfer end) WOVI0 (Interval timer) WOVI1 (Interval timer) Address break
EVC TMR_X
ICRB7
A/D converter ADI (A/D conversion end) EVENTI CMIAX (Compare match A) CMIBX (Compare match B) OVIX (Overflow) OCIA (Output compare A) OCIB (Output compare B) FOVI (Overflow)
ICRB4
FRT
ICRB6 Low
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Section 5 Interrupt Controller Origin of Interrupt Source External pin Vector Address Vector Number Advanced Mode 56 57 58 59 60 61 62 63 64 65 66 68 69 70 72 73 74 76 78 80 81 82 83 84 85 86 87 H'0000E0 H'0000E4 H'0000E8 H'0000EC H'0000F0 H'0000F4 H'0000F8 H'0000FC H'000100 H'000104 H'000108 H'000110 H'000114 H'000118 H'000120 H'000124 H'000128 H'000130 H'000138 H'000140 H'000144 H'000148 H'00014C H'000150 H'000154 H'000158 H'00015C H'000160 H'000164 H'000168 H'000170 H'000178 H'000188 H'000190 H'000198 H'0001A0 H'0001A4 H'0001A8 H0001AC ICRC7
Name IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15
ICR ICRD7
Priority High
ICRD6
TMR_0
CMIA0 (Compare match A) CMIB0 (Compare match B) OVI0 (Overflow) CMIA1 (Compare match A) CMIB1 (Compare match B) OVI1 (Overflow) CMIAY (Compare match A) CMIBY (Compare match B) OVIY (Overflow) IICI2 IICI3 ERI3 (Reception error 3) RXI3 (Reception completion 3) TXI3 (Transmission data empty 3) TEI3 (Transmission end 3) ERI1 (Reception error 1) RXI1 (Reception completion 1) TXI1 (Transmission data empty 1) TEI1 (Transmission end 1)
ICRB3
TMR_1
ICRB2
TMR_Y
ICRB1
IIC_2 IIC_3 SCI_3
ICRC2
SCI_1
ICRC6
SSU
ERIS (Reception error S) 88 RXIS (Reception completion S) 89 TXIS (Transmission data empty S) 90 SCIFI IICI0 IICI1 IICI4 IICI5 ERR1(transfer error, etc.) IBFI1 (IDR1 reception completion) IBFI2 (IDR2 reception completion) IBFI3 (IDR3 reception completion) 92 94 98 100 102 104 105 106 107
ICRC5
SCIF IIC_0 IIC_1 IIC_4 IIC_5 LPC
ICRD1 ICRC4 ICRC3 ICRB0 ICRB0 ICRC1
Low
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Section 5 Interrupt Controller Origin of Interrupt Source PECI*
2
Name PEWFCSEI PERFCSEI PETEI
Vector Address Vector Number Advanced Mode 108 109 110 114 115 116 117 118 119 H'0001B0 H'0001B4 H'0001B8 H'0001C8 H'0001CC H'0001D0 H'0001D4 H'0001D8 H'0001DC
ICR ICRD2
Priority High
USB*1 (only in RESUME the H8S/2472) USBINT0 USBINT2 USBINT3 USBINT1 EtherC EINT
ICRC0
ICRD5
Low
Notes: 1. Supported only by the H8S/2472 Group. 2. Supported only by the H8S/2472 Group and the H8S/2462 Group.
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Section 5 Interrupt Controller
5.6
Interrupt Control Modes and Interrupt Operation
The interrupt controller has two modes: Interrupt control mode 0 and interrupt control mode 1. Interrupt operations differ depending on the interrupt control mode. NMI interrupts and address break interrupts are always accepted except for in reset state or in hardware standby mode. The interrupt control mode is selected by SYSCR. Table 5.4 shows the interrupt control modes. Table 5.4 Interrupt Control Modes
Priority Setting Registers ICR Interrupt Mask Bits I
SYSCR Interrupt Control Mode INTM1 INTM0 0 0 0
Description Interrupt mask control is performed by the I bit. Priority levels can be set with ICR. 3-level interrupt mask control is performed by the I and UI bits. Priority levels can be set with ICR.
1
1
ICR
I, UI
Figure 5.3 shows a block diagram of the priority decision circuit.
I ICR UI
Interrupt source
Interrupt acceptance control and 3-level mask control
Default priority determination
Vector number
Interrupt control modes 0 and 1
Figure 5.3 Block Diagram of Interrupt Control Operation
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Section 5 Interrupt Controller
Interrupt Acceptance Control and 3-Level Control: In interrupt control modes 0 and 1, interrupt acceptance control and 3-level mask control is performed by means of the I and UI bits in CCR and ICR (control level). Table 5.5 shows the interrupts selected in each interrupt control mode. Table 5.5 Interrupts Selected in Each Interrupt Control Mode
Interrupt Mask Bits Interrupt Control Mode I 0 0 1 1 0 1 UI * * * 0 1 [Legend] * Don't care Selected Interrupts All interrupts (interrupt control level 1 has priority) NMI and address break interrupts All interrupts (interrupt control level 1 has priority) NMI, address break, and interrupt control level 1 interrupts NMI and address break interrupts
Default Priority Determination: The priority is determined for the selected interrupt, and a vector number is generated. If the same value is set for ICR, acceptance of multiple interrupts is enabled, and so only the interrupt source with the highest priority according to the preset default priorities is selected and has a vector number generated. Interrupt sources with a lower priority than the accepted interrupt source are held pending. Table 5.6 shows operations and control signal functions in each interrupt control mode.
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Section 5 Interrupt Controller
Table 5.6
Operations and Control Signal Functions in Each Interrupt Control Mode
Setting INTM1 INTM0 Interrupt Acceptance Control 3-Level Control I UI ICR
Interrupt Control Mode
Default Priority Determination
T (Trace)
0 1
0
0 1
O O
IM IM
IM
PR PR
O O

[Legend] O: Interrupt operation control performed IM: Used as an interrupt mask bit PR: Sets priority : Not used
5.6.1
Interrupt Control Mode 0
In interrupt control mode 0, interrupts other than NMI are masked by ICR and the I bit of the CCR in the CPU. Figure 5.4 shows a flowchart of the interrupt acceptance operation. 1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. 2. According to the interrupt control level specified in ICR, the interrupt controller accepts an interrupt request with interrupt control level 1 (priority), and holds pending an interrupt request with interrupt control level 0 (no priority). If several interrupt requests are issued, an interrupt request with the highest priority is accepted according to the priority order, an interrupt handling is requested to the CPU, and other interrupt requests are held pending. 3. If the I bit in CCR is set to 1, only NMI and address break interrupt requests are accepted by the interrupt controller, and other interrupt requests are held pending. If the I bit is cleared to 0, any interrupt request is accepted. KIN, WUE, and EVENTI interrupts are enabled or disabled by the I bit. 4. When the CPU accepts an interrupt request, it starts interrupt exception handling after execution of the current instruction has been completed. 5. The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. 6. Next, the I bit in CCR is set to 1. This masks all interrupts except for NMI and address break interrupts.
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Section 5 Interrupt Controller
7. The CPU generates a vector address for the accepted interrupt and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table.
Program execution state
Interrupt generated? Yes Yes
No
NMI No
An interrupt with interrupt control level 1?
No
Pending
Yes No IRQ0 Yes No IRQ1 Yes IRQ0 Yes IRQ1 EINT Yes Yes EINT Yes No No
I=0 Yes
No
Save PC and CCR
I
1
Read vector address
Branch to interrupt handling routine
Figure 5.4 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 0
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Section 5 Interrupt Controller
5.6.2
Interrupt Control Mode 1
In interrupt control mode 1, mask control is applied to three levels for IRQ and on-chip peripheral module interrupt requests by comparing the I and UI bits in CCR in the CPU, and the ICR setting. * An interrupt request with interrupt control level 0 is accepted when the I bit in CCR is cleared to 0. When the I bit is set to 1, the interrupt request is held pending. EVENTI, KIN, and WUE interrupts are enabled or disabled by the I bit. * An interrupt request with interrupt control level 1 is accepted when the I bit or UI bit in CCR is cleared to 0. When both I and UI bits are set to 1, the interrupt request is held pending. For instance, the state when the interrupt enable bit corresponding to each interrupt is set to 1, and ICRA to ICRD are set to H'20, H'00, H'00, and H'00, respectively (IRQ2 and IRQ3 interrupts are set to interrupt control level 1, and other interrupts are set to interrupt control level 0) is shown below. Figure 5.6 shows a state transition diagram. * All interrupt requests are accepted when I = 0. (Priority order: NMI > IRQ2 > IRQ3 > IRQ0 > IRQ1 > address break ...) * Only NMI, IRQ2, IRQ3, and address break interrupt requests are accepted when I = 1 and UI = 0. * Only NMI and address break interrupt requests are accepted when I = 1 and UI = 1.
I All interrupt requests are accepted I
0 0
1, UI
Only NMI, address break, and interrupt control level 1 interrupt requests are accepted
I Exception handling execution or I 1, UI 1
0
UI
0 Exception handling execution or UI 1
Only NMI and address break interrupt requests are accepted
Figure 5.5 State Transition in Interrupt Control Mode 1
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Section 5 Interrupt Controller
Figure 5.6 shows a flowchart of the interrupt acceptance operation. 1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. 2. According to the interrupt control level specified in ICR, the interrupt controller only accepts an interrupt request with interrupt control level 1 (priority), and holds pending an interrupt request with interrupt control level 0 (no priority). If several interrupt requests are issued, an interrupt request with the highest priority is accepted according to the priority order, an interrupt handling is requested to the CPU, and other interrupt requests are held pending. 3. An interrupt request with interrupt control level 1 is accepted when the I bit is cleared to 0, or when the I bit is set to 1 while the UI bit is cleared to 0. An interrupt request with interrupt control level 0 is accepted when the I bit is cleared to 0. When both the I and UI bits are set to 1, only NMI and address break interrupt requests are accepted, and other interrupts are held pending. When the I bit is cleared to 0, the UI bit is not affected. 4. When the CPU accepts an interrupt request, it starts interrupt exception handling after execution of the current instruction has been completed. 5. The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. 6. The I and UI bits in CCR are set to 1. This masks all interrupts except for NMI and address break interrupts. 7. The CPU generates a vector address for the accepted interrupt and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table.
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Section 5 Interrupt Controller
Program execution state No
Interrupt generated? Yes Yes
NMI No
An interrupt with interrupt control level 1?
No
Pending
Yes No No IRQ1 Yes EINT Yes No IRQ0 Yes IRQ1 Yes EINT Yes No
IRQ0 Yes
I=0 Yes
No
I=0 No Yes
No
UI = 0 Yes Save PC and CCR
I
1, UI
1
Read vector address Branch to interrupt handling routine
Figure 5.6 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 1
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5.6.3
REJ09B0403-0200
Interrupt is accepted Instruction prefetch Stack access Vector fetch Internal processing Internal processing Prefetch of instruction in interrupt-handling routine
Section 5 Interrupt Controller
Interrupt level decision and wait for end of instruction
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Interrupt request signal
Interrupt Exception Handling Sequence
Internal address bus
(1) (3) (5) (7) (9) (11)
(13)
Internal read signal
Internal write signal
Figure 5.7 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack area are in on-chip memory.
Figure 5.7 Interrupt Exception Handling
(2) (4) (6) (8) (10) (12) (14) (6) (8) (9) (11) (10) (12) (13) (14) Saved PC and CCR Vector address Starting address of interrupt-handling routine (contents of vector address) Starting address of interrupt-handling routine ((13) = (10) (12)) First instruction in interrupt-handling routine
Internal data bus
(1)
(2) (4) (3) (5) (7)
Instruction prefetch address (Instruction is not executed. Address is saved as PC contents, becoming return address.) Instruction code (not executed) Instruction prefetch address (Instruction is not executed.) SP - 2 SP - 4
Section 5 Interrupt Controller
5.6.4
Interrupt Response Times
Table 5.7 shows interrupt response times - the intervals between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The execution status symbols used in table 5.7 are explained in table 5.8. Table 5.7
No. 1 2 3 4 5 6
Interrupt Response Times
Advanced Mode
1 2
Execution Status Interrupt priority determination*
3 1 to (19 + 2*SI) 2*SK 2*SI
Number of wait states until executing instruction ends* PC, CCR stack save Vector fetch Instruction fetch*
3 4
2*SI 2 12 to 32
Internal processing*
Total (using on-chip memory) Notes: 1. 2. 3. 4.
Two states in case of internal interrupt. Refers to MULXS and DIVXS instructions. Prefetch after interrupt acceptance and prefetch of interrupt handling routine. Internal processing after interrupt acceptance and internal processing after vector fetch.
Table 5.8
Number of States in Interrupt Handling Routine Execution Status
Object of Access External Device 8-Bit Bus 16-Bit Bus 2-State Access 2 3-State Access 3+m
Symbol Instruction fetch SI Branch address read SJ Stack manipulation SK
Internal Memory 1
2-State Access 4
3-State Access 6 + 2m
[Legend] m: Number of wait states in external device access.
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Section 5 Interrupt Controller
5.6.5
DTC Activation by Interrupt
The DTC can be activated by an interrupt. In this case, the following options are available: * Interrupt request to CPU * Activation request to DTC * Both of the above For details of interrupt requests that can be used to activate the DTC, see section 7, Data Transfer Controller (DTC). Figure 5.8 shows a block diagram of the DTC and interrupt controller.
Interrupt request IRQ interrupt Interrupt source clear signal
Selection circuit Select signal Clear signal DTCER
DTC activation request vector number
Control logic Clear signal
DTC
On-chip peripheral module
DTVECR SWDTE clear signal Determination of priority CPU interrupt request vector number CPU I, UI
Interrupt controller
Figure 5.8 Interrupt Control for DTC The interrupt controller has three main functions in DTC control. (1) Selection of Interrupt Source
It is possible to select DTC activation request or CPU interrupt request with the DTCE bit of DTCERA to DTCERF in the DTC. After a DTC data transfer, the DTCE bit can be cleared to 0 and an interrupt request sent to the CPU in accordance with the specification of the DISEL bit of MRB in the DTC. When the DTC performs the specified number of data transfers and the transfer counter reaches 0, following the DTC data transfer the DTCE bit is cleared to 0 and an interrupt request is sent to the CPU.
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Section 5 Interrupt Controller
(2)
Determination of Priority
The DTC activation source is selected in accordance with the default priority order, and is not affected by mask or priority levels. See section 7.5, Location of Register Information and DTC Vector Table, for the respective priorities. (3) Operation Order
If the same interrupt is selected as a DTC activation source and a CPU interrupt source, the DTC data transfer is performed first, followed by CPU interrupt exception handling. Table 5.9 summarizes interrupt source selection and interrupt source clearing control according to the settings of the DTCE bit of DTCERA to DTCERF in the DTC and the DISEL bit of MRB in the DTC. Table 5.9 Interrupt Source Selection and Clearing Control
Settings DTC DTCE 0 1 DISEL X 0 1 x Interrupt Source Selection/Clearing Control DTC CPU x
[Legend] : The relevant interrupt is used. Interrupt source clearing is performed. (The CPU should clear the source flag in the interrupt handling routine.) : The relevant interrupt is used. The interrupt source is not cleared. x: The relevant interrupt cannot be used. X: Don't care
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Section 5 Interrupt Controller
5.7
5.7.1
Usage Notes
Conflict between Interrupt Generation and Disabling
When an interrupt enable bit is cleared to 0 to disable interrupt requests, the disabling becomes effective after execution of the instruction. When an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, and if an interrupt is generated during execution of the instruction, the interrupt concerned will still be enabled on completion of the instruction, so interrupt exception handling for that interrupt will be executed on completion of the instruction. However, if there is an interrupt request of higher priority than that interrupt, interrupt exception handling will be executed for the higher-priority interrupt, and the lower-priority interrupt will be ignored. The same rule is also applied when an interrupt source flag is cleared to 0. Figure 5.9 shows an example in which the CMIEA bit in the TMR's TCR register is cleared to 0. The above conflict will not occur if an enable bit or interrupt source flag is cleared to 0 while the interrupt is masked.
TCR write cycle by CPU
CMIA exception handling
Internal address bus
TCR address
Internal write signal
CMIEA
CMFA
CMIA interrupt signal
Figure 5.9 Conflict between Interrupt Generation and Disabling
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Section 5 Interrupt Controller
5.7.2
Instructions that Disable Interrupts
The instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions are executed, all interrupts including NMI are disabled and the next instruction is always executed. When the I bit or UI bit is set by one of these instructions, the new value becomes valid two states after execution of the instruction ends. 5.7.3 Interrupts during Execution of EEPMOV Instruction
Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction. With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer is not accepted until the move is completed. With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt exception handling starts at a break in the transfer cycle. The PC value saved on the stack in this case is the address of the next instruction. Therefore, if an interrupt is generated during execution of an EEPMOV.W instruction, the following coding should be used.
L1: EEPMOV.W MOV.W BNE R4,R4 L1
5.7.4
IRQ Status Registers (ISR16, ISR)
Since IRQnF may be set to 1 according to the pin status after a reset, the ISR16 and the ISR should be read after a reset, and then write 0 in IRQnF (n = 15 to 0).
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Section 5 Interrupt Controller
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Section 6 Bus Controller (BSC)
Section 6 Bus Controller (BSC)
This LSI has an on-chip bus controller (BSC) that manages the bus width and the number of access states of the external address space. The BSC also has a bus arbitration function, and controls the operation of the internal bus masters - CPU, data transfer controller (DTC), and Ethernet controller direct memory access controller (E-DMAC).
6.1
Features
* Extended modes Two modes for external extension Normal extended mode: Normal extension (when ADMXE = 0 in SYSCR2 and OBE = 0 in PTCNT0) Glueless extension (when ADMXE = 0 in SYSCR2 and OBE = 1 in PTCNT0) Address-data multiplex extended mode: Multiplex extension (when ADMXE = 1 in SYSCR2) * Extended area division Possible in normal extended mode The external address space can be accessed as basic extended areas. A 256-Kbyte extended area can be set and controlled independently of basic extended areas. * Address pin reduction In normal extended mode: A 256-Kbyte extended area from H'F80000 to H'FBFFFF can be selected using 18 address pins and the CS256 signal. A 2-Kbyte area from H'FFF000 to H'FFF7FF can be selected using six to eleven address pins and the IOS signal. In address-data multiplex extended mode: The external address space can be accessed as the following two extended areas. H'F80000 to H'F8FFFF H'FFF000 to H'FFF7FF 64 Kbytes 2 Kbytes 256-Kbyte extended area IOS extended area
These areas can be selected using 8 pins or 16 pins, which is a total of address pins and data input/output pins. * Control address hold signal and area select signal polarity The output polarity of IOS, CS256, and AH can be inverted by the PNCCS and PNCAH bits in LPWRCR
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Section 6 Bus Controller (BSC)
* Multiplex bus interface
No Wait Inserted Address 256-Kbyte extended area Note: * 2 states* Data 2 states 2 states Address 2 states* 2 states* Wait Inserted Data (3 + wait) states (3 + wait) states
IOS extended area 2 states*
A wait cycle is inserted by the setting of the WC22 bit.
* Basic bus interface 2-state access or 3-state access can be selected for each area. Program wait states can be inserted for each area. * Burst ROM interface In normal extended mode A burst ROM interface can be set for basic extended areas. 1-state access or 2-state access can be selected for burst access. * Idle cycle insertion In normal extended mode An idle cycle can be inserted for external write cycles immediately after external read cycles. * Bus arbitration function Includes a bus arbiter that arbitrates bus mastership between the CPU, DTC, and E-DMAC.
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Section 6 Bus Controller (BSC)
External bus control signals
Bus controller
Internal control signals
Bus mode signal
BCR WSCR
BCR2
WAIT
Wait controller
Bus arbiter
CPU bus request signal DTC bus request signal E-DMAC bus request signal CPU bus acknowledge signal DTC bus acknowledge signal E-DMAC bus acknowledge signal
[Legend] BCR: BCR2: WSCR: WSCR2: Bus control register Bus control register 2 Wait state control register Wait state control register 2
Figure 6.1 Block Diagram of Bus Controller
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Internal data bus
WSCR2
Section 6 Bus Controller (BSC)
6.2
Input/Output Pins
Table 6.1 summarizes the pin configuration of the bus controller. Table 6.1
Symbol AS
Pin Configuration
I/O Output Function Strobe signal indicating that address output on the address bus is enabled (when the IOSE bit in SYSCR is cleared to 0). Note that this signal is not output when the 256-Kbyte extended area is accessed (the CS256E bit in SYSCR is 1). Chip select signal indicating that the IOS extended area is being accessed (when the IOSE bit in SYSCR is 1). Chip select signal indicating that the 256-Kbyte extended area is being accessed (when the CS256E bit in SYSCR is 1). Strobe signal indicating that the external address space is being read. Strobe signal indicating that the external address space is being written to, and the upper half (D15 to D8, AD15 to AD8) of the data bus is valid. Strobe signal indicating that the external address space is being written to, and the lower half (D7 to D0, AD7 to AD0) of the data bus is valid. Wait request signal when accessing the external space. Strobe signal indicating that the external address space is being written to. Strobe signal indicating that the external address space is being accessed, and the upper half (D15 to D8) of the data bus is valid. Strobe signal indicating that the external address space is being accessed, and the lower half (D7 to D0) of the data bus is valid. Signal indicating address fetch timing when the bus is in address-data multiplex bus state. Address output and data input/output pins for address-data multiplex extension.
IOS CS256
Output Output
RD HWR
Output Output
LWR
Output
WAIT WR HBE
Input Output Output
LBE
Output
AH AD15 to AD0
Output Input/Output
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Section 6 Bus Controller (BSC)
6.3
Register Descriptions
The following registers are provided for the bus controller. For the system control register (SYSCR), see section 3.2.2, System Control Register (SYSCR). For port control register 0 (PTCNT0), see section 8.3.2, Port Control Register 0 (PTCNT0). * Bus control register (BCR) * Bus control register 2 (BCR2) * Wait state control register (WSCR) * Wait state control register 2 (WSCR2) * System control register 2 (SYSCR2) 6.3.1 Bus Control Register (BCR)
BCR is used to specify the access mode for the external address space and the I/O area range when the AS/IOS pin is specified as an I/O strobe pin.
Bit 7 6 Bit Name ICIS Initial Value 1 1 R/W R/W R/W Description Reserved The initial value should not be changed. Idle Cycle Insertion Selects whether or not to insert 1-state of the idle cycle between successive external read and external write cycles. 0: Idle cycle not inserted 1: 1-state idle cycle inserted 5 BRSTRM 0 R/W Valid only in the normal extended mode. Burst ROM Enable Selects the bus interface for the external address space. 0: Basic bus interface 1: Burst ROM interface When the CS256E bit in SYSCR is set to 1, burst ROM interface cannot be selected for the 256-Kbyte extended area.
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Section 6 Bus Controller (BSC)
Bit 4
Bit Name BRSTS1
Initial Value 1
R/W R/W
Description Valid only in the normal extended mode. Burst Cycle Select 1 Selects the number of states in the burst cycle of the burst ROM interface. 0: 1 state 1: 2 states
3
BRSTS0
0
R/W
Valid only in the normal extended mode. Burst Cycle Select 0 Selects the number of words that can be accessed by burst access via the burst ROM interface. 0: Max, 4 words 1: Max, 8 words
2 1 0
IOS1 IOS0
0 1 1
R/W R/W R/W
Reserved The initial value should not be changed. IOS Select 1 and 0 Select the address range where the IOS signal is output. See table 6.12.
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Section 6 Bus Controller (BSC)
6.3.2
Bus Control Register 2 (BCR2)
BCR2 is used to specify the access mode for the extended area.
Bit 7, 6 5, 4 3 Bit Name ADFULLE Initial Value All 0 All 1 0 R/W R/W R/W R/W Description Reserved The initial value should not be changed. Reserved The initial value should not be changed. Address Output Full Enable Controls the address output, A23 to A21, in access to the extended area. See section 8, I/O Ports. This is not supported while ADMXE = 1. 2 EXCKS 0 R/W External Extension Clock Select Selects the operating clock used in external extended area access. 0: Medium-speed clock is selected as the operating clock 1: System clock () is selected as the operating clock. The operating clock is switched in the bus cycle prior to external extended area access. 1 0 1 0 R/W R/W Reserved The initial value should not be changed. Reserved The initial value should not be changed.
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Section 6 Bus Controller (BSC)
6.3.3
Wait State Control Register (WSCR)
WSCR is used to specify the data bus width, the number of access states, the wait mode, and the number of wait states for access to external address spaces (basic extended area and 256-Kbyte extended area). The bus width and the number of access states for internal memory and internal I/O registers are fixed regardless of the WSCR settings.
Bit 7 Bit Name ABW256 Initial Value 1 R/W R/W Description 256-Kbyte Extended Area Bus Width Control Selects the bus width for access to the 256-Kbyte extended area when the CS256E bit in SYSCR is set to 1. 0: 16-bit bus 1: 8-bit bus 6 AST256 1 R/W 256-Kbyte Extended Area Access State Control Selects the number of states for access to the 256-Kbyte extended area when the CS256E bit in SYSCR is set to 1. This bit also enables or disables wait-state insertion. [ADMXE = 0] Normal extension 0: 2-state access space. Wait state insertion disabled 1: 3-state access space. Wait state insertion enabled [ADMXE = 1] Address-data multiplex extension 0: 2-state data access space. Wait state insertion disabled 1: 3-state data access space. Wait state insertion enabled 5 ABW 1 R/W Basic Extended Area Bus Width Control Selects the bus width for access to the basic extended area. 0: 16-bit bus 1: 8-bit bus When the CS256E bit in SYSCR is set to 1, this bit setting is ignored in access to the 256-Kbyte extended area.
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Section 6 Bus Controller (BSC)
Bit 4
Bit Name AST
Initial Value 1
R/W R/W
Description Basic Extended Area Access State Control Selects the number of states for access to the basic extended area. This bit also enables or disables wait-state insertion. [ADMXE = 0] Normal extension 0: 2-state access space. Wait state insertion disabled 1: 3-state access space. Wait state insertion enabled [ADMXE = 1] Address-data multiplex extension 0: 2-state data access space. Wait state insertion disabled 1: 3-state data access space. Wait state insertion enabled When the CS256E bit in SYSCR is set to 1, this bit setting is ignored in access to the 256-Kbyte extended area.
3 2
WMS1 WMS0
0 0
R/W R/W
Basic Extended Area Wait Mode Select 1 and 0 Selects the wait mode for access to the basic extended area when the AST bit is set to 1. 00: Program wait mode 01: Wait disabled mode 10: Pin wait mode 11: Pin auto-wait mode When the CS256E bit in SYSCR is set to 1, this bit setting is ignored in access to the 256-Kbyte extended area.
1 0
WC1 WC0
1 1
R/W R/W
Basic Extended Area Wait Count 1 and 0 Selects the number of program wait states to be inserted when the basic extended area is accessed when the AST bit is set to 1. The program wait state is only inserted into data cycles. 00: Program wait state is not inserted 01: 1 program wait state is inserted 10: 2 program wait states are inserted 11: 3 program wait states are inserted When the CS256E bit in SYSCR is set to 1, this bit setting is ignored in access to the 256-Kbyte extended area.
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Section 6 Bus Controller (BSC)
6.3.4
Wait State Control Register 2 (WSCR2)
WSCR2 is used to specify the wait mode and number of wait states in access to the 256-Kbyte extended area.
Bit 7 Bit Name WMS10 Initial Value 0 R/W R/W Description 256-Kbyte Extended Area Wait Mode Select 0 Selects the wait mode for access to the 256-Kbyte extended area when the CS256E bit in SYSCR and the AST256 bit in WSCR are set to 1. 0: Program wait mode 1: Wait disabled mode 6 5 WC11 WC10 1 1 R/W R/W 256-Kbyte Extended Area Wait Count 1 and 0 Selects the number of program wait states to be inserted into the data cycle for access to the 256-Kbyte extended area when the CS256E bit in SYSCR and the AST256 bit in WSCR are set to 1. 00: Program wait state is not inserted 01: 1 program wait state is inserted 10: 2 program wait states are inserted 11: 3 program wait states are inserted 4 3 All 0 R/W Reserved
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Section 6 Bus Controller (BSC)
* When ADMXE = 0
Bit 2 to 0 Bit Name Initial Value All 1 R/W R/W Description Reserved
* When ADMXE = 1
Bit 2 Bit Name WC22 Initial Value 1 R/W R/W Description Address-Data Multiplex Extended Area Address Cycle Wait Count 2 Selects the number of program wait states to be inserted into the address cycle for access to the address-data multiplex extended area. 0: Program wait state is not inserted 1: 1 program wait state is inserted in the address cycle 1, 0 All 1 R/W Reserved
6.3.5
System Control Register 2 (SYSCR2)
SYSCR2 controls the address-data multiplex operation.
Bit Bit Name Initial Value All 0 0 R/W R/W R/W Description Reserved The initial value should not be changed. 3 ADMXE Address-Data Multiplex Bus Interface Enable 0: Normal extended bus interface 1: Address data multiplex extended bus interface 2 to 0 All 0 R/W Reserved The initial value should not be changed.
7 to 4
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Section 6 Bus Controller (BSC)
6.4
6.4.1
Bus Control
Bus Specifications
The external address space bus specifications consist of three elements: bus width, the number of access states, and the wait mode and the number of program wait states. The bus width and the number of access states for on-chip memory and internal I/O registers are fixed, and are not affected by the bus controller settings. (1) (a) In Normal Extended Mode Bus Width
A bus width of 8 or 16 bits can be selected via the ABW and ABW256 bits in WSCR. (b) Number of Access States
Two or three access states can be selected via the AST and AST256 bits in WSCR. When the 2state access space is designated, wait-state insertion is disabled. In the burst ROM interface, the number of access states for the basic extended area is determined regardless of the AST bit setting. (c) Wait Mode and Number of Program Wait States
When the basic extended area is specified as a 3-state access space by the AST bit in WSCR, the wait mode and the number of program wait states to be inserted automatically is selected by the WMS1, WMS0, WC1, and WC0 bits in WSCR. From 0 to 3 program wait states can be selected. When the 256-Kbyte extended area is specified as a 3-state access space by the AST256 bit in WSCR, the wait mode and the number of program wait states to be inserted automatically is selected by the WMS10, WC11, and WC10 bits in WSCR2. From 0 to 3 program wait states can be selected. The wait function for external extension is effective for connecting low-speed devices to the external address space. However, this wait function may cause some problems when the operation of bus masters other than the CPU, such as the DTC are to be delayed. Tables 6.2 to 6.5 show each bit setting and external address space division in the address ranges of the external address space, and the bus specifications for the basic bus interface of each area.
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Section 6 Bus Controller (BSC)
(d)
Glueless Extension
Setting the OBE bit in PTCNT0 selects glueless extension, which uses the RD, WR, HBE, and LBE signals to allow connection to the external space without adding an external circuit. Table 6.2 Address Ranges and External Address Spaces
Area Address Range H'080000 to H'F7FFFF (15 Mbytes) H'F80000 to H'FBFFFF (256 Kbytes) 256-Kbyte extended area H'FC0000 to H'FEFFFF (192 Kbytes) H'FF0800 to H'FFBFFF (46 Kbytes) H'FFC000 to H'FFDFFF (8 Kbytes) H'FFE000 to H'FFE07F (128 bytes) H'FFE080 to H'FFEFFF (3968 bytes) H'FFF000 to H'FFF7FF (2 Kbytes) : No condition : When RAME = 0, used as basic extended area. : No condition : No condition. : When RAME = 0, used as basic extended area. Basic Extended Area : No condition : When CS256E = 0, used as basic extended area. 256-Kbyte Extended Area When WAIT pin function is not selected while CS256E = 1, CS256 is output and address pins A17 to A0 are used.
No condition When IOSE = 1, IOS is output and address pins A10 to A0 are used. When RAME = 0, used as basic extended area.
H'FFFF00 to H'FFFF7F (128 bytes)
[Legend] : This address range is unconditionally accessed as the basic extended area. : Condition for making this address range accessed as the basic extended area. : This address range cannot be used as part of a 256-Kbyte extended area.
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Section 6 Bus Controller (BSC)
Table 6.3
BRSTRM
Bit Settings and Bus Specifications of Basic Bus Interface
Areas
CS256E
Basic Extended Area Basic extended area ABW, AST, WMS1, WMS0, WC1, WC0 Burst ROM interface*
256-Kbyte Extended Area Used as basic extended area ABW256, AST256, WMS10, WC11, WC10 Used as burst ROM interface
0
0 1
1
0 1
ABW, AST, WMS0, WC1, WC0, ABW256, AST256, WMS10, BRSTS1, BRSTS0 WC11, WC10
Note:
*
In the burst ROM interface, the bus width is specified by the ABW bit in WSCR, the number of full access states (wait can be inserted) is specified by the AST bit in WSCR, and the number of access cycles in burst access is specified regardless of the AST bit setting.
Table 6.4
Bus Specifications for Basic Extended Area/Basic Bus Interface
Bus Specifications Number of Access States 2 3 3 Number of Program Wait States 0 0 0 1 2 3 8 8 2 3 3 0 0 0 1 2 3
ABW 0
AST 0 1
WMS1 X 0
WMS0 X 1
WC1 X X 0
WC0 X X 0 1
Bus Width 16 16
Other than WMS1 = 0 and WMS0 = 1
1
0 1
1
0 1
X 0
X 1
X X 0
X X 0 1
Other than WMS1 = 0 and WMS0 = 1
1 [Legend] X: Don't care
0 1
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Section 6 Bus Controller (BSC)
Table 6.5
Bus Specifications for 256-Kbyte Extended Area/Basic Bus Interface
Bus Specifications Number of Access States 2 3 3 Number of Program Wait States 0 0 0 1 2 3 8 8 2 3 3 0 0 0 1 2 3
ABW256
AST256
WMS10
WC11
WC10
Bus Width 16 16
0
0 1
X 1 0
X X 0
X X 0 1
1
0 1
1
0 1
X 1 0
X X 0
X X 0 1
1 [Legend] X: Don't care
0 1
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Section 6 Bus Controller (BSC)
(2) (a)
In Address-Data Multiplex Extended Mode Bus Width
A bus width of 8 or 16 bits can be selected via the ABW and ABW256 bits in WSCR. (b) Number of Access States
Two or three states can be selected for data access via the AST and AST256 bits in WSCR. When the 2-state access space is designated, wait-state insertion is disabled. (c) Wait Mode and Number of Program Wait States
* IOS Extended Area When the IOS extended area is specified as a 3-state access space by the AST bit in WSCR, the wait mode and the number of program wait states to be inserted automatically is selected by the WMS1, WMS0, WC1, and WC0 bits in WSCR. Zero or one program wait state can be inserted into address cycle. From zero to three program wait states can be selected for data cycle. * 256-Kbyte Extended Area When the 256-Kbyte extended area is specified as a 3-state access space by the AST256 bit in WSCR, the wait mode and the number of program wait states to be inserted automatically is selected by the WMS10, WC11, and WC10 bits in WSCR2. Zero or one program wait state can be inserted into address cycle. From zero to three program wait states can be selected for data cycle. The wait function for external extension is effective for connecting low-speed devices to the external address space. However, this wait function may cause some problems when the operation of bus masters other than the CPU, such as the DTC, are to be delayed. Tables 6.6 to 6.11 show address-data multiplex address space and the bus specifications for the basic bus interface of each area.
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Section 6 Bus Controller (BSC)
Table 6.6
Address-Data Multiplex Address Spaces
Address-Data Multiplex Area O No condition When the WAIT pin function is not selected and CS256E = 1, CS256 is output and address AD15 to AD0 or AD7 to AD0 are used. No condition
Address Range H'080000 to H'F7FFFF (15 Mbytes) 256-Kbyte extended area H'F80000 to H'F8FFFF (64 Kbytes) 256-Kbyte extended area H'F90000 to H'F9FFFF (64 Kbytes) 256-Kbyte extended area H'FA0000 to H'FAFFFF (64 Kbytes) 256-Kbyte extended area H'FB0000 to H'FBFFFF (64 Kbytes) H'FC0000 to H'FFBFFF (240 Kbytes) H'FFC000 to H'FFDFFF (8 Kbytes) H'FFE000 to H'FFEFFF (4 Kbytes) IOS extended area H'FFF000 to H'FFF7FF (2 Kbytes) H'FFFF00 to H'FFFF7F (128 bytes)
No condition
No condition
O
No condition No condition No condition When IOSE = 1, IOS is output and address pins AD15 to AD0 or AD7 to AD0 are used. No condition
[Legend] : This address range cannot be used as the address-data multiplex address space. O: Condition for making this address range accessed as the address-data multiplex address space.
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Section 6 Bus Controller (BSC)
Table 6.7
Bit Settings and Bus Specifications of Basic Bus Interface
Area
IOSE 1
CS256E 0 1
IOS Extended Area ABW, AST, WMS1, WMS0, WC1, WC0
256-Kbyte Extended Area ABW256, AST256, WMS10, WC11, WC10 ABW256, AST256, WMS10, WC11, WC10
0
0 1
Table 6.8
Bus Specifications for IOS Extended Area/Multiplex Bus Interface (Address Cycle)
Number of Access States 2 Number of Program Wait States 0 1
AST
WMS1
WMS0
WC22 0 1
WC1
WC0
Table 6.9
Bus Specifications for IOS Extended Area/Multiplex Bus Interface (Data Cycle)
Number of Access States 2 3 3 Number of Program Wait States 0 0 0 1 2 3
AST 0 1
WMS1 0
WMS0 1
WC1
WC0 0 1 0 1
Other than WMS1 = 0 and 0 WMS0 = 1 1
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Section 6 Bus Controller (BSC)
Table 6.10 Bus Specifications for 256-Kbyte Extended Area/Multiplex Bus Interface (Address Cycle)
Number of Access States 2 Number of Program Wait States 0 1
AST256
WMS10
WC22 0 1
WC11
WC10
Table 6.11 Bus Specifications for 256-Kbyte Extended Area/Multiplex Bus Interface (Data Cycle)
Number of Program Wait Number of Access States States 2 3 3 0 0 0 1 2 3
AST256 0 1
WMS1 1 0
WC1 0
WC0 0 1
1
0 1
6.4.2
Advanced Mode
The external address space (H'FFF000 to H'FFF7FF) can be accessed by specifying the AS/IOS pin as an I/O strobe pin. The 256-Kbyte extended area (H'F80000 to H'FBFFFF) can be accessed by the CS256 pin function. The external address space is initialized as the basic bus interface and a 3-state access space. In mode 2, the address space other than on-chip ROM, on-chip RAM, internal I/O registers, and their reserved areas is specified as the external address space. The on-chip RAM and its reserved area are enabled when the RAME bit in SYSCR is set to 1, and disabled when the RAME bit is cleared to 0. Addresses H'FF0800 to H'FFBFFF, H'FFE080 to H'FFEFFF, and H'FFFF00 to H'FFFF7F in the on-chip RAM area and its reserved area are always specified as the external address space.
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Section 6 Bus Controller (BSC)
6.4.3
I/O Select Signals
The LSI can output I/O select signals (IOS); the signal is driven low when the corresponding external address space is accessed. Figure 6.2 shows an example of IOS signal output timing.
Bus cycle T1
T2
T3
Address bus
External addresses selected by IOS
IOS
Figure 6.2 IOS Signal Output Timing Enabling or disabling IOS signal output is performed by the IOSE bit in SYSCR. In the extended mode, the IOS pin functions as an AS pin by a reset. To use this pin as an IOS pin, set the IOSE bit to 1. For details, see section 8, I/O Ports. The address ranges of the IOS signal output can be specified by the IOS1 and IOS0 bits in BCR, as shown in table 6.12. Table 6.12 Address Range for IOS Signal Output
IOS1 0 IOS0 0 1 1 0 1 IOS Signal Output Range H'FFF000 to H'FFF03F H'FFF000 to H'FFF0FF H'FFF000 to H'FFF3FF H'FFF000 to H'FFF7FF (Initial value)
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Section 6 Bus Controller (BSC)
6.5
Bus Interface
The normal extended bus interface enables direct connection to ROM and SRAM. For details on selection of the bus specifications for the basic extended area and 256-Kbyte extended area, see table 6.5. The address-data multiplex extended bus interface enables direct connection to products that supports this bus interface. For details on selection of the bus specifications for the IOS extended area and 256-Kbyte extended area, see tables 6.8 to 6.11. 6.5.1 Data Size and Data Alignment
Data sizes for the CPU and other internal bus masters are byte, word, and longword. The BSC has a data alignment function, and controls whether the upper data bus (D15 to D8/AD15 to AD8) or lower data bus (D7 to D0/AD7 to AD0) is used when the external address space is accessed, according to the bus specifications for the area being accessed (8-bit access space or 16-bit access space) and the data size. (1) 8-Bit Access Space
Figure 6.3 illustrates data alignment control for the 8-bit access space. With the 8-bit access space, the upper data bus (D15 to D8) is always used for accesses. The amount of data that can be accessed at one time is one byte: a word access is performed as two byte accesses, and a longword access, as four byte accesses. The lower data bus (AD7 to AD0) is used in address-data multiplex extended mode.
Upper data bus Lower data bus D15 D8 D7 D0 Byte size 1st bus cycle 2nd bus cycle 1st bus cycle Longword size 2nd bus cycle 3rd bus cycle 4th bus cycle 7 15 7 31 23 15 7 0 8 0 24 16 8 0
Word size
Figure 6.3 Access Sizes and Data Alignment Control (8-bit Access Space)
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Section 6 Bus Controller (BSC)
(2)
16-Bit Access Space
Figure 6.4 illustrates data alignment control for the 16-bit access space. With the 16-bit access space, the upper data bus (D15 to D8/AD15 to AD8) and lower data bus (D7 to D0/AD7 to AD0) are used for accesses. The amount of data that can be accessed at one time is one byte or one word, and a longword access is executed as two word accesses. In byte access, whether the upper or lower data bus is used is determined by whether the address is even or odd. The upper data bus is used for even addresses, and the lower data bus for odd addresses.
Upper data bus Lower data bus D15 D8 D7 D0 Byte size Byte size Word size Longword size 1st bus cycle 2nd bus cycle * Even address * Odd address 15 31 15 15 8 7 87 24 23 87 0 0 16 0
Figure 6.4 Access Sizes and Data Alignment Control (16-bit Access Space)
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Section 6 Bus Controller (BSC)
6.5.2
Valid Strobes
Table 6.13 shows the data buses used and valid strobes for each access space. In a read, the RD signal is valid for both the upper and lower halves of the data bus. In a write, the HWR signal is valid for the upper half of the data bus, and the LWR signal for the lower half. Table 6.13 Data Buses Used and Valid Strobes
Lower Data Upper Data Bus Bus (D7 to D0/AD7 to (D15 to D8/ AD15 to AD8) AD0) Valid Ports or others
Area 8-bit access space
Access Size Byte
Read/ Write Read Write Read Write
Address
Valid Strobe RD HWR RD HWR
8-bit access Byte space (in addressdata multiplex extended mode) 16-bit access space Byte
Ports or others
Valid
Read
Even Odd
RD HWR LWR RD HWR, LWR
Valid Invalid Valid Undefined Valid
Invalid Valid Undefined Valid Valid
Write
Even Odd
Word
Read Write
[Legend] Undefined: Undefined data is output. Invalid: Input state with the input value ignored. Ports or others: Used as ports or I/O pins for on-chip peripheral modules, and are not used as the data bus.
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Section 6 Bus Controller (BSC)
6.5.3
Valid Strobes (in Glueless Extension)
Table 6.14 shows the data buses used and valid strobes for each access space. The RD and WR signals are valid for both the upper and lower halves of the data bus. In a write, the HBE signal is valid for the upper half of the data bus, and the LBE signal for the lower half. Table 6.14 Data Buses Used and Valid Strobes (Gluless Extension)
Area 8-bit access space 16-bit access space Access Size Byte Read/ Write Read Write Byte Read Address Even Odd Write Even Odd Word Read Write Valid Strobe RD WR RD, HBE RD, LBE WR, HBE WR, LBE RD, HBE, LBE WR, HBE, LBE Valid Invalid Valid Undefined Valid Invalid Valid Undefined Valid Valid Upper Data Bus Lower Data (D15 to D8) Bus (D7 to D0) Valid Ports or others
[Legend] Undefined: Undefined data is output. Invalid: Input state with the input value ignored. Ports or others: Used as ports or I/O pins for on-chip peripheral modules, and are not used as the data bus.
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Section 6 Bus Controller (BSC)
6.5.4 (1)
Basic Operation Timing in Normal Extended Mode 8-Bit, 2-State Access Space
Figure 6.5 shows the bus timing for an 8-bit, 2-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. Wait states cannot be inserted.
Bus cycle T1
T2
Address bus
IOS (IOSE = 1) CS256 (CS256E = 1)
AS * (IOSE = 0)
RD
Read
D15 to D8
Valid
D7 to D0
Invalid
HWR Write D15 to D8 Valid
Note: * For external address space access, this signal is not output when the 256-Kbyte extended area is accessed with CS256E = 1.
Figure 6.5 Bus Timing for 8-Bit, 2-State Access Space
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Section 6 Bus Controller (BSC)
(2)
8-Bit, 3-State Access Space
Figure 6.6 shows the bus timing for an 8-bit, 3-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. Wait states can be inserted.
Bus cycle T1
T2
T3
Address bus
IOS (IOSE = 1) CS256 (CS256E = 1) AS * (IOSE = 0)
RD
Read
D15 to D8
Valid
D7 to D0
Invalid
HWR Write D15 to D8 Valid
Note: * For external address space access, this signal is not output when the 256-Kbyte extended area is accessed with CS256E = 1.
Figure 6.6 Bus Timing for 8-Bit, 3-State Access Space
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Section 6 Bus Controller (BSC)
(3)
16-Bit, 2-State Access Space
Figures 6.7 to 6.9 show bus timings for a 16-bit, 2-state access space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used for even addresses, and the lower half (D7 to D0) for odd addresses. Wait states cannot be inserted.
Bus cycle T1
T2
Address bus
IOS (IOSE = 1) CS256 (CS256E = 1)
AS * (IOSE = 0)
RD
Read
D15 to D8
Valid
D7 to D0
Invalid
HWR
LWR Write D15 to D8
High level
Valid
D7 to D0
Undefined
Note: * For external address space access, this signal is not output when the 256-Kbyte extended area is accessed with CS256E = 1.
Figure 6.7 Bus Timing for 16-Bit, 2-State Access Space (Even Byte Access)
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Section 6 Bus Controller (BSC)
Bus cycle T1
T2
Address bus
IOS (IOSE = 1) CS256 (CS256E = 1)
AS* (IOSE = 0)
RD
Read
D15 to D8
Invalid
D7 to D0
Valid
HWR
High level
LWR Write D15 to D8 Undefined
D7 to D0
Valid
Note: * For external address space access, this signal is not output when the 256-Kbyte extended area is accessed with CS256E = 1.
Figure 6.8 Bus Timing for 16-Bit, 2-State Access Space (Odd Byte Access)
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Section 6 Bus Controller (BSC)
Bus cycle T1
T2
Address bus
IOS (IOSE = 1) CS256 (CS256E = 1)
AS * (IOSE = 0)
RD
Read
D15 to D8
Valid
D7 to D0
Valid
HWR
LWR Write D15 to D8 Valid
D7 to D0
Valid
Note: * For external address space access, this signal is not output when the 256-Kbyte extended area is accessed with CS256E = 1.
Figure 6.9 Bus Timing for 16-Bit, 2-State Access Space (Word Access)
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Section 6 Bus Controller (BSC)
(4)
16-Bit, 3-State Access Space
Figures 6.10 to 6.12 show bus timings for a 16-bit, 3-state access space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used for even addresses, and the lower half (D7 to D0) for odd addresses. Wait states can be inserted.
Bus cycle T1
T2
T3
Address bus
IOS (IOSE = 1) CS256 (CS256E = 1) AS* (IOSE = 0)
RD
Read
D15 to D8
Valid
D7 to D0
Invalid
HWR High level
LWR Write D15 to D8
Valid
D7 to D0
Undefined
Note: * For external address space access, this signal is not output when the 256-Kbyte extended area is accessed with CS256E = 1.
Figure 6.10 Bus Timing for 16-Bit, 3-State Access Space (Even Byte Access)
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Section 6 Bus Controller (BSC)
Bus cycle T1
T2
T3
Address bus
IOS (IOSE = 1) CS256 (CS256E = 1) AS* (IOSE = 0)
RD
Read
D15 to D8
Invalid
D7 to D0
Valid
HWR
High level
LWR Write D15 to D8 Undefined
D7 to D0
Valid
Note: * For external address space access, this signal is not output when the 256-Kbyte extended area is accessed with CS256E = 1.
Figure 6.11 Bus Timing for 16-Bit, 3-State Access Space (Odd Byte Access)
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Section 6 Bus Controller (BSC)
Bus cycle T1
T2
T3
Address bus
IOS (IOSE = 1) CS256 (CS256E = 1) AS* (IOSE = 0)
RD
Read
D15 to D8
Valid
D7 to D0
Valid
HWR
LWR Write D15 to D8 Valid
D7 to D0
Valid
Note: * For external address space access, this signal is not output when the 256-Kbyte extended area is accessed with CS256E = 1.
Figure 6.12 Bus Timing for 16-Bit, 3-State Access Space (Word Access)
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Section 6 Bus Controller (BSC)
Bus cycle
Address bus (A23 to A0)
CS IOS (IOSE = 1) CS256 (CS256E = 1)
AS* HBE LBE RD
Even
High level
Read
D15 to D8
Valid
D7 to D0 WR
Invalid
Write
D15 to D8
Valid
D7 to D0
Undefined
Note: * For external address space access, this signal is not output when the 256-Kbyte extended area is accessed with CS256E = 1.
Figure 6.13 Glueless Extension Even Byte Access (ADMXE = 0)
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Section 6 Bus Controller (BSC)
Bus cycle
Address bus (A23 to A0)
CS IOS (IOSE = 1) CS256 (CS256E = 1)
AS* HBE LBE RD
Odd
High level
Read
D15 to D8
Invalid
D7 to D0 WR
Valid
Write
D15 to D8
Undefined
D7 to D0
Valid
Note: * For external address space access, this signal is not output when the 256-Kbyte extended area is accessed with CS256E = 1.
Figure 6.14 Glueless Extension Odd Byte Access (ADMXE = 0)
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Section 6 Bus Controller (BSC)
Bus cycle
Address bus (A23 to A0)
CS IOS (IOSE = 1) CS256 (CS256E = 1)
AS* HBE
Even
LBE RD
Read
D15 to D8
valid
D7 to D0 WR
valid
Write
D15 to D8
Valid
D7 to D0
Valid
Note:
* For external address space access, this signal is not output when the 256-Kbyte extended area is accessed with CS256E = 1.
Figure 6.15 Glueless Extension Word Access (ADMXE = 0)
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Section 6 Bus Controller (BSC)
6.5.5 (1)
Basic Operation Timing in Address-Data Multiplex Extended Mode 8-Bit, 2-State Data Access Space
Figures 6.16 and 6.17 show the bus timing for an 8-bit, 2-state access space. When an 8-bit access space is accessed, the lower half (AD7 to AD0) of the data bus is used. Wait states cannot be inserted.
Read Cycle Address T1 TAW T2 T3 Data T4 T1 Write Cycle Address TAW T2 T3 Data T4
CS256 IOS AH
RD HWR
AD7 to AD0
Address
Data
Address
Data
Figure 6.16 Bus Timing for 8-Bit, 2-State Access Space
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Section 6 Bus Controller (BSC)
Read Cycle Address T1 T2 T3 Data T4
Write Cycle Address T1 T2 T3 Data T4
CS256 IOS AH
RD HWR
AD7 to AD0
Address
Data
Address
Data
Figure 6.17 Bus Timing for 8-Bit, 2-State Access Space (2) 8-Bit, 3-State Data Access Space
Figure 6.18 shows the bus timing for an 8-bit, 3-state access space. When an 8-bit access space is accessed, the lower half (AD7 to AD0) of the data bus is used. Wait states can be inserted.
Read Cycle Address T1 TAW T2 T3 T4 Data TDSW T5 T1 Address TAW T2 T3 T4 Write Cycle Data TDSW T5
CS256 IOS AH
RD HWR AD7 to AD0 Address Data Address Data
Figure 6.18 Bus Timing for 8-Bit, 3-State Access Space
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Section 6 Bus Controller (BSC)
(3)
16-Bit, 2-State Data Access Space
Figures 6.19 to 6.24 show bus timings for a 16-bit, 2-state access space. When a 16-bit access space is accessed, the upper half (AD15 to AD8) of the data bus is used for even addresses, and the lower half (AD7 to AD0) for odd addresses. Wait states cannot be inserted.
Read Cycle Address T1 CS256 IOS AH TAW T2 T3 Data T4 T1 Write Cycle Address TAW T2 T3 Data T4
RD HWR LWR AD15 to AD8 Address Data Address Data
AD7 to AD0
Address
Address
Figure 6.19 Bus Timing for 16-Bit, 2-State Access Space (1) (Even Byte Access)
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Section 6 Bus Controller (BSC)
Read Cycle Address T1 T2 T3 Data T4
Write Cycle Address T1 T2 T3 Data T4
CS256 IOS AH
RD HWR LWR AD15 to AD8 Address Data Address Data
AD7 to AD0
Address
Address
Figure 6.20 Bus Timing for 16-Bit, 2-State Access Space (2) (Even Byte Access)
Read Cycle Address T1 TAW T2 T3 Data T4 T1 Write Cycle Address TAW T2 T3 Data T4
CS256 IOS AH
RD HWR LWR
AD15 to AD8
Address
Address
AD7 to AD0
Address
Data
Address
Data
Figure 6.21 Bus Timing for 16-Bit, 2-State Access Space (3) (Odd Byte Access)
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Section 6 Bus Controller (BSC)
Read Cycle Address T1 T2 T3 Data T4
Write Cycle Address T1 T2 T3 Data T4
CK2S CS256 IOS AH RD HWR LWR AD15 to AD8 Address Address
AD7 to AD0
Address
Data
Address
Data
Figure 6.22 Bus Timing for 16-Bit, 2-State Access Space (4) (Odd Byte Access)
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Section 6 Bus Controller (BSC)
Read Cycle Address T1 TAW T2 T3 Data T4 T1
Write Cycle Address TAW T2 T3 Data T4
CS256 IOS AH
RD HWR LWR
AD15 to AD8
Address
Data
Address
Data
AD7 to AD0
Address
Data
Address
Data
Figure 6.23 Bus Timing for 16-Bit, 2-State Access Space (5) (Word Access)
Read Cycle Address T1 CP256 IOS T2 T3 Data T4 Write Cycle Address T1 T2 T3 Data T4
AH
RD HWR LWR AD15 to AD8 Address Data Address Data
AD7 to AD0
Address
Data
Address
Data
Figure 6.24 Bus Timing for 16-Bit, 2-State Access Space (6) (Word Access)
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Section 6 Bus Controller (BSC)
(4)
16-Bit, 3-State Data Access Space
Figures 6.25 to 6.27 show bus timings for a 16-bit, 3-state access space. When a 16-bit access space is accessed, the upper half (AD15 to AD8) of the data bus is used for even addresses, and the lower half (AD7 to AD0) for odd addresses. Wait states can be inserted.
Read Cycle Address T1 CS256 IOS AH TAW T2 T3 T4 Data TDSW T5 T1 Address TAW T2 T3 T4 Write Cycle Data TDSW T5
RD HWR LWR AD15 to AD8 Address Data Address Data
AD7 to AD0
Address
Address
Figure 6.25 Bus Timing for 16-Bit, 3-State Access Space (1) (Even Byte Access)
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Section 6 Bus Controller (BSC)
Read Cycle Address T1 CS256 IOS AH TAW T2 T3 T4 Data TDSW T5 T1 Address TAW T2
Write Cycle Data T3 T4 TDSW T5
RD HWR LWR AD15 to AD8 Address Address
AD7 to AD0
Address
Data
Address
Data
Figure 6.26 Bus Timing for 16-Bit, 3-State Access Space (2) (Odd Byte Access)
Read Cycle Address T1 CS256 IOS AH TAW T2 T3 T4 Data TDSW T5 T1 Address TAW T2 T3 T4 Write Cycle Data TDSW T5
RD HWR LWR
AD15 to AD8
Address
Data
Address
Data
AD7 to AD0
Address
Data
Address
Data
Figure 6.27 Bus Timing for 16-Bit, 3-State Access Space (3) (Word Access)
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Section 6 Bus Controller (BSC)
6.5.6
Wait Control
When accessing the external address space, this LSI can extend the bus cycle by inserting one or more wait states (TW). There are three ways of inserting wait states: Program wait insertion, pin wait insertion using the WAIT pin, and the combination of program wait and the WAIT pin. (1) (a) In Normal Extended Mode Program Wait Mode
A specified number of wait states TW are always inserted between the T2 state and T3 state when accessing the external address space. The number of wait states TW is specified by the settings of the WC1 and WC0 bits in WSCR (the WC11 and WC10 bits in WSCR2 for the 256-Kbyte extended area). (b) Pin Wait Mode
A specified number of wait states TW are always inserted between the T2 state and T3 state when accessing the external address space. The number of wait states TW is specified by the settings of the WC1 and WC0 bits. If the WAIT pin is low at the falling edge of in the last T2 or TW state, another TW state is inserted. If the WAIT pin is held low, TW states are inserted until it goes high. Pin wait mode is useful when inserting four or more TW states, or when changing the number of TW states to be inserted for each external device. (c) Pin Auto-Wait Mode
A specified number of wait states TW are inserted between the T2 state and T3 state when accessing the external address space if the WAIT pin is low at the falling edge of in the last T2 state. The number of wait states TW is specified by the settings of the WC1 and WC0 bits. Even if the WAIT pin is held low, TW states are inserted only up to the specified number of states. Pin auto-wait mode enables the low-speed memory interface only by inputting the chip select signal to the WAIT pin. Figure 6.28 shows an example of wait state insertion timing in pin wait mode. The settings after a reset are: 3-state access, 3 program wait insertion, and WAIT pin input disabled.
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Section 6 Bus Controller (BSC)
By program wait T1 T2 TW
By WAIT pin TW TW T3
WAIT
Address bus
IOS (IOSE = 1)
AS * (IOSE = 0)
RD Read Data bus Read data
WR Write Data bus Write data
Note: shown in clock indicates the WAIT pin sampling timing. * For external address space access, this signal is not output when the 256-kbyte extended area is accessed with CS256E = 1.
Figure 6.28 Example of Wait State Insertion Timing (Pin Wait Mode)
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Section 6 Bus Controller (BSC)
(2) (a)
In Address-Data Multiplex Extended Mode Program Wait Mode
Program wait mode includes address wait and data wait. * 256-Kbyte extended area and IOS extended area Zero or one state of address wait TAW is inserted between T1 and T2 states. Zero to three states of data wait TDSW is inserted between T4 and T5 states. (b) Pin Wait Mode
When accessing the external address space, a specified number of wait states TDSW can be inserted between the T4 state and T5 state of data state. The number of wait states TDSW is specified by the settings of the WC1 and WC0 bits. If the WAIT pin is low at the falling edge of in the last T4, TDSW, or TDOW state, another TDOW state is inserted. If the WAIT pin is held low, TDOW states are inserted until it goes high. Pin wait mode is useful when inserting four or more TDOW states, or when changing the number of TDOW states to be inserted for each external device. (c) Pin Auto-Wait Mode
A specified number of wait states TDOW are inserted between the T4 state and T5 state when accessing the external address space if the WAIT pin is low at the falling edge of in the last T4 state. The number of wait states TDOW is specified by the settings of the WC1 and WC0 bits. Even if the WAIT pin is held low, TDOW states are inserted only up to the specified number of states. Pin auto-wait mode enables the low-speed memory interface only by inputting the chip select signal to the WAIT pin. Figure 6.29 shows an example of wait state insertion timing in pin wait mode.
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Section 6 Bus Controller (BSC)
Read Cycle Data T3 T4 TDSW TDOW TDOW T5 T3 T4
Write Cycle Data TDSW TDOW TDOW T5
CS256 IOS WAIT AH
RD
HWR LWR
AD15 to AD8
Data
Data
AD7 to AD0
Data
Data
Figure 6.29 Example of Wait State Insertion Timing
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Section 6 Bus Controller (BSC)
6.6
Burst ROM Interface
In this LSI, the external address space can be designated as the burst ROM space by the BRSTRM bit in BCR, and the burst ROM interface enabled. Consecutive burst accesses of a maximum four or eight words can be performed only during CPU instruction fetch. 1 or 2 states can be selected for burst ROM access. 6.6.1 Basic Operation Timing
The number of access states in the initial cycle (full access) of the burst ROM interface is determined by the AST bit in WSCR. When the AST bit is set to 1, wait states can be inserted. 1 or 2 states can be selected for burst access according to the setting of the BRSTS1 bit in BCR. Wait states cannot be inserted in a burst cycle. Burst accesses of a maximum four words is performed when the BRSTS0 bit in BCR is cleared to 0, and burst accesses of a maximum eight words is performed when the BRSTS0 bit in BCR is set to 1. The basic access timing for the burst ROM space is shown in figures 6.30 and 6.31.
Full access T1 T2 T3 T1 Burst access T2 T1 T2
Address bus
Only lower address changes
AS/IOS (IOSE = 0) RD
Data bus
Read data
Read data
Read data
Figure 6.30 Access Timing Example in Burst ROM Space (AST = BRSTS1 = 1)
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Section 6 Bus Controller (BSC)
Full access T1 T2
Burst access T1 T1
Address bus
Only lower address changes
AS/IOS (IOSE = 0)
RD
Data bus
Read data
Read data Read data
Figure 6.31 Access Timing Example in Burst ROM Space (AST = BRSTS1 = 0) 6.6.2 Wait Control
As with the basic bus interface, program wait insertion or pin wait insertion using the WAIT pin is possible in the initial cycle (full access) of the burst ROM interface. For details, see section 6.5.6, Wait Control. Wait states cannot be inserted in a burst cycle.
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Section 6 Bus Controller (BSC)
6.7
Idle Cycle
When this LSI accesses the external address space, it can insert a 1-state idle cycle (TI) between bus cycles when a write cycle occurs immediately after a read cycle. By inserting an idle cycle it is possible, for example, to avoid data collisions between ROM with a long output floating time, and high-speed memory and I/O interfaces. If an external write occurs after an external read while the ICIS bit is set to 1 in BCR, an idle cycle is inserted at the start of the write cycle. Figure 6.32 shows examples of idle cycle operation. In these examples, bus cycle A is a read cycle for ROM with a long output floating time, and bus cycle B is a CPU write cycle. In figure 6.32 (a), with no idle cycle inserted, a collision occurs in bus cycle B between the read data from ROM and the CPU write data. In figure 6.32 (b), an idle cycle is inserted, thus preventing data collision.
Bus cycle A T1 Address bus RD WR Data bus T2 T3 Bus cycle B T1 T2 Address bus RD WR Data bus Data collision Long output floating time (a) No idle cycle insertion (b) Idle cycle insertion Bus cycle A T1 T2 T3 Bus cycle B TI T1 T2
Figure 6.32 Examples of Idle Cycle Operation
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Section 6 Bus Controller (BSC)
Table 6.15 shows the pin states in an idle cycle. Table 6.15 Pin States in Idle Cycle
Pins A23 to A0 D15 to D0 AS, IOS, CS256 RD HWR, LWR Pin State Contents of immediately following bus cycle High impedance High High High
6.8
6.8.1
Bus Arbitration
Overview
The BSC has a bus arbiter that arbitrates bus master operations. There are three bus masters - the CPU, DTC, and E-DMAC - that perform read/write operations while they have bus mastership. 6.8.2 Operation
Each bus master requests the bus mastership by means of a bus mastership request signal. The bus arbiter detects the bus mastership request signal from the bus masters, and if a bus request occurs, it sends a bus mastership request acknowledge signal to the bus master that made the request at the designated timing. If there are bus requests from more than one bus master, the bus mastership request acknowledge signal is sent to the one with the highest priority. When a bus master receives the bus mastership request acknowledge signal, it takes the bus mastership until that signal is canceled. The order of bus master priority is as follows: (High) E-DMAC > DTC > CPU (Low)
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Section 6 Bus Controller (BSC)
6.8.3
Bus Mastership Transfer Timing
When a bus request is received from a bus master with a higher priority than that of the bus master that has acquired the bus mastership and is currently operating, the bus mastership is not necessarily transferred immediately. Each bus master can relinquish the bus mastership at the timings given below. (1) CPU
The CPU is the lowest-priority bus master, and if a bus mastership request is received from the DTC or E-DMAC, the bus arbiter transfers the bus mastership to the DTC or E-DMAC. The timing for transferring the bus mastership is as follows: * Timing for transferring the bus mastership to the DTC 1. Bus mastership is transferred at a break between bus cycles. However, if bus cycle is executed in discrete operations, as in the case of a longword size access, the bus is not transferred at a break between the operations. For details, see section 2.7, Bus States During Instruction Execution in the H8S/2600 Series, H8S/2000 Series Software Manual. 2. If the CPU is in sleep mode, it transfers the bus mastership immediately. * Timing for transferring the bus mastership to the E-DMAC 1. Bus mastership is transferred at a break between bus cycles. Even if bus cycle is executed in discrete operations, as in the case of a longword size access, the bus can be transferred at a break between bus cycles. For details, see section 21, Ethernet Controller Direct Memory Access Controller (E-DMAC). 2. If the CPU is in sleep mode, it transfers the bus mastership immediately.
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Section 6 Bus Controller (BSC)
(2)
DTC
The DTC sends the bus arbiter a request for the bus mastership when a request for DTC activation occurs. The DTC releases the bus mastership after a series of processes has completed. The DTC is the lower-priority bus master than the E-DMAC, and if a bus mastership request is received from the E-DMAC, the bus arbiter transfers the bus mastership to the E-DMAC. The timing for transferring the bus mastership is as follows: * Timing for transferring the bus mastership to the E-DMAC 1. Bus mastership is transferred at a break between bus cycles. However, if bus cycle is executed in discrete operations, as in the case of a longword size access, the bus is not transferred at a break between the operations. In addition, in the case of a 32-bit access by the DTC, the bus is not transferred at a break between the operations. For details, see section 21, Ethernet Controller Direct Memory Access Controller (E-DMAC). 2. If the CPU is in sleep mode, it transfers the bus mastership immediately. (3) E-DMAC
The E-DMAC is the highest-priority bus master, and sends the bus arbiter a request for the bus when an activation request is generated. The E-DMAC does not release the bus until the consecutive transfer cycles have completed. For details, see section 21, Ethernet Controller Direct Memory Access Controller (E-DMAC).
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Section 6 Bus Controller (BSC)
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Section 7 Data Transfer Controller (DTC)
Section 7 Data Transfer Controller (DTC)
This LSI includes a data transfer controller (DTC). The DTC can be activated by an interrupt or software, to transfer data. Figure 7.1 shows a block diagram of the DTC. The DTC's register information is stored in the onchip RAM. When the DTC is used, the RAME bit in SYSCR must be set to 1. A 32-bit bus connects the DTC to addresses H'FFEC00 to H'FFEFFF in on-chip RAM (1 kbyte), enabling 32bit/1-state reading and writing of the DTC register information.
7.1
* * * * * * * * *
Features
Transfer is possible over any number of channels Three transfer modes
Normal, repeat, and block transfer modes are available One activation source can trigger a number of data transfers (chain transfer) Direct specification of 16 Mbytes address space is possible Activation by software is possible Transfer can be set in byte or word units A CPU interrupt can be requested for the interrupt that activated the DTC Module stop mode can be set DTC operates in high-speed mode even when the LSI is in medium-speed mode
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Section 7 Data Transfer Controller (DTC)
Internal address bus
Interrupt controller
DTC
On-chip RAM
CPU interrupt request
DTC activation request
[Legend] MRA, MRB: CRA, CRB: SAR: DAR: DTCERA to DTCERF: DTVECR:
DTC mode register A, B DTC transfer count register A, B DTC source address register DTC destination address register DTC enable registers A to F DTC vector register
Figure 7.1 Block Diagram of DTC
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MRA MRB CRA CRB DAR SAR
Interrupt request
Internal data bus
Register information
Control logic
DTCERA to DTCERF
DTVECR
Section 7 Data Transfer Controller (DTC)
7.2
Register Descriptions
The DTC has the following registers. * * * * * * DTC mode register A (MRA) DTC mode register B (MRB) DTC source address register (SAR) DTC destination address register (DAR) DTC transfer count register A (CRA) DTC transfer count register B (CRB)
These six registers cannot be directly accessed from the CPU. When a DTC activation interrupt source occurs, the DTC reads a set of register information that is stored in on-chip RAM to the corresponding DTC registers and transfers data. After the data transfer, it writes a set of updated register information back to on-chip RAM. * * * * * DTC enable registers (DTCER) DTC vector register (DTVECR) Keyboard comparator control register (KBCOMP) Event counter control register (ECCR) Event counter status register (ECS)
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Section 7 Data Transfer Controller (DTC)
7.2.1
DTC Mode Register A (MRA)
MRA selects the DTC operating mode.
Bit 7 6 Bit Name SM1 SM0 Initial Value Undefined R/W Description Source Address Mode 1 and 0 These bits specify an SAR operation after a data transfer. 0*: SAR is fixed 10: SAR is incremented after a transfer (by +1 when Sz = 0, by +2 when Sz = 1) 11: SAR is decremented after a transfer (by -1 when Sz = 0, by -2 when Sz = 1) 5 4 DM1 DM0 Undefined Destination Address Mode 1 and 0 These bits specify a DAR operation after a data transfer. 0*: DAR is fixed 10: DAR is incremented after a transfer (by +1 when Sz = 0, by +2 when Sz = 1) 11: DAR is decremented after a transfer (by -1 when Sz = 0, by -2 when Sz = 1) 3 2 MD1 MD0 Undefined DTC Mode These bits specify the DTC transfer mode. 00: Normal mode 01: Repeat mode 10: Block transfer mode 11: Setting prohibited 1 DTS Undefined DTC Transfer Mode Select Specifies whether the source side or the destination side is set to be a repeat area or block area in repeat mode or block transfer mode. 0: Destination side is repeat area or block area 1: Source side is repeat area or block area 0 Sz Undefined DTC Data Transfer Size Specifies the size of data to be transferred. 0: Byte-size transfer 1: Word-size transfer Note: * Don't care
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Section 7 Data Transfer Controller (DTC)
7.2.2
DTC Mode Register B (MRB)
MRB selects the DTC operating mode.
Bit 7 Bit Name CHNE Initial Value Undefined R/W Description DTC Chain Transfer Enable When this bit is set to 1, a chain transfer will be performed. For details, see section 7.6.4, Chain Transfer. In data transfer with CHNE set to 1, determination of the end of the specified number of data transfers, clearing of the interrupt source flag, and clearing of DTCER are not performed. 6 DISEL Undefined DTC Interrupt Select When this bit is set to 1, a CPU interrupt request is generated every time data transfer ends. When this bit is cleared to 0, a CPU interrupt request is generated only when the specified number of data transfer ends. 5 to 0 Undefined Reserved These bits have no effect on DTC operation. The write value should always be 0.
7.2.3
DTC Source Address Register (SAR)
SAR is a 24-bit register that designates the source address of data to be transferred by the DTC. For word-size transfer, specify an even source address. 7.2.4 DTC Destination Address Register (DAR)
DAR is a 24-bit register that designates the destination address of data to be transferred by the DTC. For word-size transfer, specify an even destination address.
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Section 7 Data Transfer Controller (DTC)
7.2.5
DTC Transfer Count Register A (CRA)
CRA is a 16-bit register that designates the number of times data is to be transferred by the DTC. In normal mode, the entire CRA functions as a 16-bit transfer counter (1 to 65536). It is decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000. In repeat mode or block transfer mode, the CRA is divided into two parts; the upper eight bits (CRAH) and the lower 8 bits (CRAL). CRAH holds the number of transfers while CRAL functions as an 8-bit transfer counter (1 to 256). CRAL is decremented by 1 every time data is transferred, and the contents of CRAH are sent when the count reaches H'00. 7.2.6 DTC Transfer Count Register B (CRB)
CRB is a 16-bit register that designates the number of times data is to be transferred by the DTC in block transfer mode. It functions as a 16-bit transfer counter (1 to 65536) that is decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000. 7.2.7 DTC Enable Registers (DTCER)
DTCER specifies DTC activation interrupt sources. DTCER is comprised of five registers: DTCERA to DTCERF. The correspondence between interrupt sources and DTCE bits is shown in tables 7.1 and 7.4. For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR. Multiple DTC activation sources can be set at one time (only at the initial setting) by masking all interrupts and writing data after executing a dummy read on the relevant register.
Bit 7 to 0 Bit Name DTCE7 to DTCE0 Initial Value All 0 R/W R/W Description DTC Activation Enable Setting this bit to 1 specifies a relevant interrupt source as a DTC activation source. [Clearing conditions] * * When data transfer has ended with the DISEL bit in MRB set to 1 When the specified number of transfers have ended
These bits are not cleared when the DISEL bit is 0 and the specified number of transfers have not been completed
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Section 7 Data Transfer Controller (DTC)
Table 7.1
Correspondence between Interrupt Sources and DTCER
Register
Bit 7 6 5 4 3 2 1 0
Bit Name DTCEn7 DTCEn6 DTCEn5 DTCEn4 DTCEn3 DTCEn2 DTCEn1 DTCEn0
DTCERA (16)IRQ0 (17)IRQ1 (18)IRQ2 (19)IRQ3 (28)ADI
DTCERB (76)IICI2 (94)IICI0
DTCERC (81)RXI3 (82)TXI3 (85)RXI1
DTCERD (86)TXI1 (89)RXIS (90)TXIS
DTCERE
DTCERF* (115)USBINT0 (118)USBINT1
(29)EVENTI (78)IICI3 (98)IICI1
(104)ERR1 (105)IBFI1 (106)IBFI2 (107)IBFI3
[Legend] n: A to F ( ): Vector number : Reserved. The write value should always be 0. *: Only in the H8S/2472
7.2.8
DTC Vector Register (DTVECR)
DTVECR enables or disables DTC activation by software, and sets a vector number for the software activation interrupt.
Bit 7 Bit Name SWDTE Initial Value 0 R/W R/W Description DTC Software Activation Enable Setting this bit to 1 activates DTC. Only 1 can be written to this bit. [Clearing conditions] * * When the DISEL bit is 0 and the specified number of transfers have not ended When 0 is written to the DISEL bit after a softwareactivated data transfer end interrupt (SWDTEND) request has been sent to the CPU.
This bit will not be cleared when the DISEL bit is 1 and data transfer has ended or when the specified number of transfers has ended.
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Section 7 Data Transfer Controller (DTC)
Bit 6 to 0
Bit Name
Initial Value
R/W R/W
Description DTC Software Activation Vectors 6 to 0 These bits specify a vector number for DTC software activation. The vector address is expressed as H'0400 + (vector number x 2). For example, when DTVEC6 to DTVEC0 = H'10, the vector address is H'0420. When the SWDTE bit is 0, these bits can be written to.
DTVEC6 to All 0 DTVEC0
7.2.9
Keyboard Comparator Control Register (KBCOMP)
KBCOMP enables or disables the comparator scan function of event counter.
Bit 7 Bit Name EVENTE Initial Value 0 R/W R/W Description Event Count Enable 0: Disables event count function 1: Enables event count function 6, 5 4 to 0 All 0 All 0 R R/W Reserved These bits are always read as 0 and cannot be modified. Reserved The initial value should not be changed.
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Section 7 Data Transfer Controller (DTC)
7.2.10
Event Counter Control Register (ECCR)
ECCR selects the event counter channels for use and the detection edge.
Bit 7 Bit Name EDSB Initial Value 0 R/W R/W Description Event Counter Edge Select Selects the detection edge for the event counter. 0: Counts the rising edges 1: Counts the falling edges 6 to 4 3 to 0 ECSB3 to ECSB0 All 0 All 0 R R/W Reserved These bits are always read as 0 and cannot be modified. Event Counter Channel Select 3 to 0 These bits select pins for event counter input. A series of pins are selected starting from EVENT0. When PAnDDR is set to 1, inputting events to EVENT0 to EVENT7 is ignored. 0000: EVENT0 is used 0001: EVENT0 to EVENT1 are used 0010: EVENT0 to EVENT2 are used 0011: EVENT0 to EVENT3 are used 0100: EVENT0 to EVENT4 are used 0101: EVENT0 to EVENT5 are used 0110: EVENT0 to EVENT6 are used 0111: EVENT0 to EVENT7 are used 1000: EVENT0 to EVENT8 are used 1001: EVENT0 to EVENT9 are used 1010: EVENT0 to EVENT10 are used 1011: EVENT0 to EVENT11 are used 1100: EVENT0 to EVENT12 are used 1101: EVENT0 to EVENT13 are used 1110: EVENT0 to EVENT14 are used 1111: EVENT0 to EVENT15 are used
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Section 7 Data Transfer Controller (DTC)
7.2.11
Event Counter Status Register (ECS)
ECS is a 16-bit register that holds events temporarily. The DTC decides the counter to be incremented according to the state of this register. Reading this register allows the monitoring of events that are not yet counted by the event counter. Access in 8-bit unit is not allowed.
Bit Bit Name Initial Value 0 R/W R Description Event Monitor 15 to 0 These bits indicate processed/unprocessed states of the events that are input to EVENT15 to EVENT0. 0: The corresponding event is already processed 1: The corresponding event is not yet processed
15 to 0 E15 to E0
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Section 7 Data Transfer Controller (DTC)
7.3
DTC Event Counter
To count events of EVENT 0 to EVENT15 by the DTC event counter function, set DTC as below. Table 7.2
Register MRA
DTC Event Counter Conditions
Bit 7, 6 5, 4 3, 2 1 0 Bit Name Description
SM1, SM0 00: SAR is fixed. DM1, DM0 00: DAR is fixed. MD1, MD0 01: Repeat mode DTS Sz CHNE DISEL 0: Destination is repeat area 1: Word size transfer 0: Chain transfer is disabled 0: Interrupt request is generated when data is transferred by the number of specified times B'000000 Identical optional RAM address. Its lower five bits are B'00000. The start address of 16 words is this address. They are incremented every time an event is detected in EVENT0 to EVENT15. H'FF H'FF H'FF H'FF 1: DTC function of the event counter is enabled 1: Event counter enable (SAR, DAR) : Result of EVENT0 count (SAR, DAR) + 2: Result of EVENT 1 count (SAR, DAR) + 4: Result of EVENT 2 count (SAR, DAR) + 30: Result of EVENT 15 count
MRB
7 6 5 to 0
SAR DAR
23 to 0 23 to 0
CRAH CRAL CRBH CRBL DTCERC KBCOMP RAM
7 to 0 7 to 0 7 to 0 7 to 0 4 7
DTCEC4 EVENTE
The corresponding flag to ECS input pin is set to 1 when the event pins that are specified by the ECSB3 to ECSB0 in ECCR detect the edge events specified by the EDSB in ECCR. For this flag state, status/address codes are generated. An EVENTI interrupt request is generated even if only one bit in ECS is set to 1.
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Section 7 Data Transfer Controller (DTC)
The EVENTI interrupt request activates the DTC and transfers data from RAM to RAM in the same address. Data is incremented in the DTC. The lower five bits of SAR and DAR are replaced with address code that is generated by the ECS flag status. When the DTC transfer is completed, the ECS flag for transfer is cleared. Table 7.3 Flag Status/Address Code
ECS 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Address Code B'00000 B'00010 B'00100 B'00110 B'01000 B'01010 B'01100 B'01110 B'10000 B'10010 B'10100 B'10110 B'11000 B'11010 B'11100 B'11110
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Section 7 Data Transfer Controller (DTC)
7.3.1
Event Counter Handling Priority
EVENT0 to EVENT15 count handling is operated in the priority shown as below. High Low
EVENT0 > EVENT1 EVENT14 > EVENT15 7.3.2 Usage Notes
There are following usage notes for this event counter because it uses the DTC. 1. 2. 3. Continuous events that are input from the same pin and out of DTC handling are ignored because the count up is operated by means of the DTC. If some events are generated in short intervals, the priority of event counter handling is not ordered and events are not handled in order of arrival. If the counter overflows, this event counter counts from H'0000 without generating an interrupt.
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Section 7 Data Transfer Controller (DTC)
7.4
Activation Sources
The DTC is activated by an interrupt request or by a write to DTVECR by software. The interrupt request source to activate the DTC is selected by DTCER. At the end of a data transfer (or the last consecutive transfer in the case of chain transfer), the interrupt flag that became the activation source or the corresponding DTCER bit is cleared. The activation source flag, in the case of RXI0, for example, is the RDRF flag in SCI_0. When an interrupt has been designated as a DTC activation source, the existing CPU mask level and interrupt controller priorities have no effect. If there is more than one activation source at the same time, the DTC operates in accordance with the default priorities. Figure 7.2 shows a block diagram of DTC activation source control. For details on the interrupt controller, see section 5, Interrupt Controller.
Source flag cleared Clear controller Clear DTCER Select Clear request
IRQ interrupt
Interrupt request
Selection circuit
On-chip peripheral module
DTC
DTVECR
Interrupt controller Interrupt mask
CPU
Figure 7.2 Block Diagram of DTC Activation Source Control
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Section 7 Data Transfer Controller (DTC)
7.5
Location of Register Information and DTC Vector Table
Locate the register information in the on-chip RAM (addresses: H'FFEC00 to H'FFEFFF). Register information should be located at an address that is a multiple of four within the range. The method for locating the register information in address space is shown in figure 7.3. Locate MRA, SAR, MRB, DAR, CRA, and CRB, in that order, from the start address of the register information. In the case of chain transfer, register information should be located in consecutive areas as shown in figure 7.3, and the register information start address should be located at the vector address corresponding to the interrupt source in the DTC vector table. The DTC reads the start address of the register information from the vector table set for each activation source, and then reads the register information from that start address. When the DTC is activated by software, the vector address is obtained from: H'0400 + (DTVECR[6:0] x 2). For example, if DTVECR is H'10, the vector address is H'0420. The configuration of the vector address is a 2-byte unit. Specify the lower two bytes of the register information start address.
Lower address 0 Register information start address MRA MRB Chain transfer CRA MRA MRB CRA SAR DAR CRB Register information for 2nd transfer in chain transfer 1 2 SAR DAR CRB Register information 3
4 bytes
Figure 7.3 DTC Register Information Location in Address Space
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Section 7 Data Transfer Controller (DTC)
Table 7.4
Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs
Vector Number DTVECR 16 17 18 19 28 29 76 78 81 82 85 86 89 90 94 98 104 105 106 107 DTC Vector Address
Activation Source Origin Software External pins
Activation Source Write to DTVECR IRQ0 IRQ1 IRQ2 IRQ3
DTCE*
Priority High
H'0400 + (vector number x 2) H'0420 H'0422 H'0424 H'0426 H'0438 H'043A H'0498 H'049C H'04A2 H'04A4 H'04AA H'04AC H'04B2 H'04B4 H'04BC H'04C4 H'04D0 H'04D2 H'04D4 H'04D6 DTCEA7 DTCEA6 DTCEA5 DTCEA4 DTCEA3 DTCEC4 DTCEB6 DTCED4 DTCEC2 DTCEC1 DTCEC0 DTCED7 DTCED6 DTCED5 DTCEB5 DTCED3 DTCEE3 DTCEE2 DTCEE1 DTCEE0
A/D converter EVC IIC_2 IIC_3 SCI_3 SCI_1 SSU IIC_0 IIC_1 LPC
ADI EVENTI IICI2 IICI3 RXI3 TXI3 RXI1 TXI1 RXIS TXIS IICI0 IICI1 ERRI IBFI1 IBFI2 IBFI3
USB (only in the H8S/2472) Note: *
USBINT0 115 H'04E6 DTCEF7 USBINT1 118 H'04EC DTCEF6 Low DTCE bits with no corresponding interrupt are reserved, and the write value should always be 0.
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Section 7 Data Transfer Controller (DTC)
7.6
Operation
The DTC stores register information in on-chip RAM. When activated, the DTC reads register information in on-chip RAM and transfers data. After the data transfer, the DTC writes updated register information back to on-chip RAM. The pre-storage of register information in memory makes it possible to transfer data over any required number of channels. The transfer mode can be specified as normal, repeat, or block transfer mode. Setting the CHNE bit in MRB to 1 makes it possible to perform a number of transfers with a single activation source (chain transfer). The 24-bit SAR designates the DTC transfer source address, and the 24-bit DAR designates the transfer destination address. After each transfer, SAR and DAR are independently incremented, decremented, or left fixed depending on its register information.
Start
Read DTC vector Next transfer
Read register information
Data transfer
Write register information
CHNE = 1 No
Yes
Transfer counter = 0 or DISEL = 1 No Clear an activation flag
Yes
Clear DTCER
End
Interrupt exception handling
Figure 7.4 DTC Operation Flowchart
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Section 7 Data Transfer Controller (DTC)
7.6.1
Normal Mode
In normal mode, one activation source transfers one byte or one word of data. Table 7.5 lists the register functions in normal mode. From 1 to 65,536 transfers can be specified. Once the specified number of transfers has been completed, a CPU interrupt can be requested. Table 7.5
Name DTC source address register DTC destination address register DTC transfer count register A DTC transfer count register B
Register Functions in Normal Mode
Abbreviation SAR DAR CRA CRB Function Transfer source address Transfer destination address Transfer counter Not used
SAR Transfer
DAR
Figure 7.5 Memory Mapping in Normal Mode
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Section 7 Data Transfer Controller (DTC)
7.6.2
Repeat Mode
In repeat mode, one activation source transfers one byte or one word of data. Table 7.6 lists the register functions in repeat mode. From 1 to 256 transfers can be specified. Once the specified number of transfers has been completed, the initial states of the transfer counter and the address register that is specified as the repeat area is restored, and transfer is repeated. In repeat mode, the transfer counter value does not reach H'00, and therefore CPU interrupts cannot be requested when the DISEL bit in MRB is cleared to 0. Table 7.6
Name DTC source address register DTC destination address register DTC transfer count register AH DTC transfer count register AL DTC transfer count register B
Register Functions in Repeat Mode
Abbreviation SAR DAR CRAH CRAL CRB Function Transfer source address Transfer destination address Holds number of transfers Transfer Count Not used
SAR or DAR
Repeat area Transfer
DAR or SAR
Figure 7.6 Memory Mapping in Repeat Mode
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Section 7 Data Transfer Controller (DTC)
7.6.3
Block Transfer Mode
In block transfer mode, one activation source transfers one block of data. Either the transfer source or the transfer destination is designated as a block area. Table 7.7 lists the register functions in block transfer mode. The block size can be between 1 and 256. When the transfer of one block ends, the initial state of the block size counter and the address register that is specified as the block area is restored. The other address register is then incremented, decremented, or left fixed according to the register information. From 1 to 65,536 transfers can be specified. Once the specified number of transfers has been completed, a CPU interrupt is requested. Table 7.7
Name DTC source address register DTC destination address register DTC transfer count register AH DTC transfer count register AL DTC transfer count register B
Register Functions in Block Transfer Mode
Abbreviation SAR DAR CRAH CRAL CRB Function Transfer source address Transfer destination address Holds block size Block size counter Transfer counter
1st block
SAR or DAR
* * *
Block area Transfer
DAR or SAR
N th block
Figure 7.7 Memory Mapping in Block Transfer Mode
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Section 7 Data Transfer Controller (DTC)
7.6.4
Chain Transfer
Setting the CHNE bit in MRB to 1 enables a number of data transfers to be performed consecutively in response to a single transfer request. SAR, DAR, CRA, CRB, MRA, and MRB, which define data transfers, can be set independently. Figure 7.8 shows the overview of chain transfer operation. When activated, the DTC reads the register information start address stored at the DTC vector address, and then reads the first register information at that start address. After the data transfer, the CHNE bit will be tested. When it has been set to 1, DTC reads the next register information located in a consecutive area and performs the data transfer. These sequences are repeated until the CHNE bit is cleared to 0. In the case of transfer with the CHNE bit set to 1, an interrupt request to the CPU is not generated at the end of the specified number of transfers or by setting of the DISEL bit to 1, and the interrupt source flag for the activation source is not affected.
Source
DTC vector address
Register information start address
Register information CHNE = 1 Register information CHNE = 0
Destination
Source
Destination
Figure 7.8 Chain Transfer Operation
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Section 7 Data Transfer Controller (DTC)
7.6.5
Interrupt Sources
An interrupt request is issued to the CPU when the DTC has completed the specified number of data transfers, or a data transfer for which the DISEL bit was set to 1. In the case of interrupt activation, the interrupt set as the activation source is generated. These interrupts to the CPU are subject to CPU mask level and priority level control by the interrupt controller. In the case of software activation, a software-activated data transfer end interrupt (SWDTEND) is generated. When the DISEL bit is 1 and one data transfer has been completed, or the specified number of transfers have been completed, after data transfer ends, the SWDTE bit is held at 1 and an SWDTEND interrupt is generated. The interrupt handling routine will then clear the SWDTE bit to 0. When the DTC is activated by software, an SWDTEND interrupt is not generated during a data transfer wait or during data transfer even if the SWDTE bit is set to 1. 7.6.6
Operation Timing
DTC activation request DTC request Data transfer Vector read Address
Read Write
Transfer information read
Transfer information write
Figure 7.9 DTC Operation Timing (Example in Normal Mode or Repeat Mode)
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Section 7 Data Transfer Controller (DTC)
DTC activation request DTC request Data transfer
Read Write Read Write
Vector read Address
Transfer information read
Transfer information write
Figure 7.10 DTC Operation Timing (Example of Block Transfer Mode, with Block Size of 2)
DTC activation request DTC request Data transfer Vector read Address
Read Write Read Write
Data transfer
Transfer information read
Transfer information write
Transfer information read
Transfer information write
Figure 7.11 DTC Operation Timing (Example of Chain Transfer)
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Section 7 Data Transfer Controller (DTC)
7.6.7
Number of DTC Execution States
Table 7.8 lists the execution status for a single DTC data transfer, and table 7.9 shows the number of states required for each execution status. Table 7.8 DTC Execution Status
Register Information Vector Read Read/Write I J 1 1 1 6 6 6 Internal Operations M 3 3 3
Mode Normal Repeat Block transfer
Data Read K 1 1 N
Data Write L 1 1 N
[Legend] N: Block size (initial setting of CRAH and CRAL)
Table 7.9
Number of States Required for Each Execution Status
On-Chip RAM On-Chip RAM (On-chip RAM area
(H'FFEC00 to
OnROM 16 1 1 --
On-Chip I/O Registers 8 2 -- -- 16 2 -- -- External Devices 8 2 4 -- 8 3 6 + 2m -- 16 2 2 -- 16 3 3+m --
other than H'FFEC00 to Chip H'FFEFFF)
Object to be Accessed Bus width Access states Execution Vector read status Register information read/write SJ
H'FFEFFF)
32 1 SI -- 1
16 1 -- --
Byte data read SK 1 Word data read SK Byte data write SL 1 Word data write SL Internal operation 1 SM 1 1
1 1
1 1
2 4
2 2
2 4
3+m 6 + 2m
2 2
3+m 3+m
1 1
1 1
2 4
2 2
2 4
3+m 6 + 2m
2 2
3+m 3+m
1
1
1
1
1
1
1
1
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Section 7 Data Transfer Controller (DTC)
The number of execution states is calculated from using the formula below. Note that is the sum of all transfers activated by one activation source (the number in which the CHNE bit is set to 1, plus 1). Number of execution states = I * SI + (J * SJ + K * SK + L * SL) + M * SM For example, when the DTC vector address table is located in on-chip ROM, normal mode is set, and data is transferred from on-chip ROM to an internal I/O register, then the time required for the DTC operation is 13 states. The time from activation to the end of data write is 10 states.
7.7
7.7.1
Procedures for Using DTC
Activation by Interrupt
The procedure for using the DTC with interrupt activation is as follows: 1. Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in on-chip RAM. 2. Set the start address of the register information in the DTC vector address. 3. Set the corresponding bit in DTCER to 1. 4. Set the enable bits for the interrupt sources to be used as the activation sources to 1. The DTC is activated when an interrupt used as an activation source is generated. 5. After one data transfer has been completed, or after the specified number of data transfers have been completed, the DTCE bit is cleared to 0 and a CPU interrupt is requested. If the DTC is to continue transferring data, set the DTCE bit to 1. 7.7.2 Activation by Software
The procedure for using the DTC with software activation is as follows: 1. Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in on-chip RAM. 2. Set the start address of the register information in the DTC vector address. 3. Check that the SWDTE bit is 0. 4. Write 1 to the SWDTE bit and the vector number to DTVECR. 5. Check the vector number written to DTVECR. 6. After one data transfer has been completed, if the DISEL bit is 0 and a CPU interrupt is not requested, the SWDTE bit is cleared to 0. If the DTC is to continue transferring data, set the SWDTE bit to 1. When the DISEL bit is 1 or after the specified number of data transfers have been completed, the SWDTE bit is held at 1 and a CPU interrupt is requested.
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Section 7 Data Transfer Controller (DTC)
7.8
7.8.1
Examples of Use of the DTC
Normal Mode
An example is shown in which the DTC is used to receive 128 bytes of data via the SCI. 1. Set MRA to a fixed source address (SM1 = SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), normal mode (MD1 = MD0 = 0), and byte size (Sz = 0). The DTS bit can have any value. Set MRB for one data transfer by one interrupt (CHNE = 0, DISEL = 0). Set the SCI, RDR address in SAR, the start address of the RAM area where the data will be received in DAR, and 128 (H0080) in CRA. CRB can be set to any value. 2. Set the start address of the register information at the DTC vector address. 3. Set the corresponding bit in DTCER to 1. 4. Set the SCI to the appropriate receive mode. Set the RIE bit in SCR to 1 to enable the reception complete (RXI) interrupt. Since the generation of a receive error during the SCI reception operation will disable subsequent reception, the CPU should be enabled to accept receive error interrupts. 5. Each time the reception of one byte of data has been completed on the SCI, the RDRF flag in SSR is set to 1, an RXI interrupt is generated, and the DTC is activated. The receive data is transferred from RDR to RAM by the DTC. DAR is incremented and CRA is decremented. The RDRF flag is automatically cleared to 0. 6. When CRA becomes 0 after 128 data transfers have been completed, the RDRF flag is held at 1, the DTCE bit is cleared to 0, and an RXI interrupt request is sent to the CPU. The interrupt handling routine will perform wrap-up processing.
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Section 7 Data Transfer Controller (DTC)
7.8.2
Software Activation
An example is shown in which the DTC is used to transfer a block of 128 bytes of data by means of software activation. The transfer source address is H'1000 and the transfer destination address is H'2000. The vector number is H'60, so the vector address is H'04C0. 1. Set MRA to incrementing source address (SM1 = 1, SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), block transfer mode (MD1 = 1, MD0 = 0), and byte size (Sz = 0). The DTS bit can have any value. Set MRB for one block transfer by one interrupt (CHNE = 0). Set the transfer source address (H'1000) in SAR, the transfer destination address (H'2000) in DAR, and 128 (H'8080) in CRA. Set 1 (H'0001) in CRB. 2. Set the start address of the register information at the DTC vector address (H'04C0). 3. Check that the SWDTE bit in DTVECR is 0. Check that there is currently no transfer activated by software. 4. Write 1 to the SWDTE bit and the vector number (H'60) to DTVECR. The write data is H'E0. 5. Read DTVECR again and check that it is set to the vector number (H'60). If it is not, this indicates that the write failed. This is presumably because an interrupt occurred between steps 3 and 4 and led to a different software activation. To activate this transfer, go back to step 3. 6. If the write was successful, the DTC is activated and a block of 128 bytes of data is transferred. 7. After the transfer, an SWDTEND interrupt occurs. The interrupt handling routine should clear the SWDTE bit to 0 and perform wrap-up processing.
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Section 7 Data Transfer Controller (DTC)
7.9
7.9.1
Usage Notes
Module Stop Mode Setting
DTC operation can be enabled or disabled by the module stop control register (MSTPCR). In the initial state, DTC operation is enabled. Access to DTC registers is disabled when module stop mode is set. Note that when the DTC is being activated, module stop mode cannot be specified. For details, refer to section 28, Power-Down Modes. 7.9.2 On-Chip RAM
MRA, MRB, SAR, DAR, CRA, and CRB are all located in on-chip RAM. When the DTC is used, the RAME bit in SYSCR should not be cleared to 0. 7.9.3 DTCE Bit Setting
For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR, for reading and writing. Multiple DTC activation sources can be set at one time (only at the initial setting) by masking all interrupts and writing data after executing a dummy read on the relevant register. 7.9.4 DTC Activation by Interrupt Sources of SCI, IIC, or A/D Converter
Interrupt sources of the SCI, IIC, or A/D converter which activate the DTC are cleared when DTC reads from or writes to the respective registers, and they cannot be cleared by the DISEL bit.
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Section 8 I/O Ports
Section 8 I/O Ports
8.1 I/O Ports for the H8S/2472 Group
Table 8.1 is a summary of the port functions. The pins of each port also function as input/output pins of peripheral modules and interrupt input pins. Each input/output port includes a data direction register (DDR) that controls input/output and a data register (DR) that stores output data. DDR and DR are not provided for input-only ports. Pins of ports 1 to 4, 6, and A and pins D0 to D5 of port D have built-in input pull-up MOSs. For port A pins and D0 to D5 pins, the on/off status of the input pull-up MOS is controlled by their respective DDR and the output data register (ODR). Ports 1 to 4, and 6 have an input pull-up MOS control register (PCR), in addition to DDR and DR, to control the on/off status of the input pull-up MOSs. Port 3 pins and pins 47 to 44 and B3 to B0 have built-in de-bouncers (DBn) that eliminate noises in the input signals. Ports 4 and F are designed for retain state outputs (RSn), which retain the output values on the pins even if a reset is generated when the watchdog timer has overflowed. Ports 1 to 6, and 8 to E can drive a single TTL load and 30 pF capacitive load. All the I/O ports can drive a Darlington transistor in output mode. Port pins 80 to 83, C0 to C5, D6, and D7 are NMOS push-pull output.
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Section 8 I/O Ports
Table 8.1
Port Port 1
Port Functions
Single-Chip Mode (EXPE = 0) P17 P16 P15 P14 P13 P12 P11 P10 Extended Mode (EXPE = 1) P17/A7/AD7 P16/A6/AD6 P15/A5/AD5 P14/A4/AD4 P13/A3/AD3 P12/A2/AD2 P11/A1/AD1 P10/A0/AD0 Same as left Feature of I/O Built-in input pull-up MOS
Description General I/O port multiplexed with address output and address-data multiplex I/O
Port 2
General I/O port P27/DTR multiplexed with SCIF P26/DSR control I/O P25/RI P24/DCD General I/O port multiplexed with address output and address-data multiplex I/O P23 P22 P21 P20 P37/ExDB7 P36/ExDB6 P35/ExDB5 P34/ExDB4 P33/ExDB3 P32/ExDB2 P31/ExDB1 P30/ExDB0 P47/IRQ7/RS7/DB7/HC7 P46/IRQ6/RS6/DB6/HC6 P45/IRQ5/RS5/DB5/HC5 P44/IRQ4/RS4/DB4/HC4
Built-in input pull-up MOS
P23/A11/AD11 P22/A10/AD10 P21/A9/AD9 P20/A8/AD8 P37/ExDB7/D15 P36/ExDB6/D14 P35/ExDB5/D13 P34/ExDB4/D12 P33/ExDB3/D11 P32/ExDB2/D10 P31/ExDB1/D9 P30/ExDB0/D8 P47/A15/AD15 P46/A14/AD14 P45/A13/AD13 P44/A12/AD12 Built-in input pull-up MOS
Port 3
General I/O port multiplexed with debounced input and bidirectional data bus I/O
Port 4
General I/O port multiplexed with interrupt input, debounced input, address output, and address-data multiplex I/O General I/O port multiplexed with interrupt input and bidirectional data bus* I/O
Built-in input pull-up MOS LED driving capability (sink current 12 mA)
P43/IRQ3/RS3/HC3 P42/IRQ2/RS2/HC2 P41/IRQ1/RS1/HC1 P40/IRQ0/RS0/HC0
P43/IRQ3/RS3/HC3/D7* P42/IRQ2/RS2/HC2/D6* P41/IRQ1/RS1/HC1/D5* P40/IRQ0/RS0/HC0/D4*
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Section 8 I/O Ports
Port Port 5
Description General I/O port multiplexed with interrupt input, bus control output, system clock output, SSU I/O, and external subclock input General I/O port multiplexed with interrupt input, SCIF and SCI_1 I/O
Single-Chip Mode (EXPE = 0) P57 P56/EXCL/ P55/IRQ13/SSI P54/IRQ12/SSO
Extended Mode (EXPE = 1) WR/HWR Same as left
Feature of I/O
P53/IRQ11/RxD1 P52/IRQ10/TxD1 P51/IRQ9/RxDF P50/IRQ8/TxDF P67/ExIRQ8/SSCK P66/ExIRQ9/SCS P65/ExIRQ10/RTS P64/ExIRQ11/CTS P63/PWX3 P62/PWX2 P61/IRQ15/PWX1 P60/IRQ14/PWX0
Same as left
Port 6
General I/O port multiplexed with interrupt input, SCIF control I/O and SSU control I/O General I/O port multiplexed with interrupt input, PWMX output, and bidirectional data bus* I/O
Same as left
Built-in input pull-up MOS
P63/PWX3/D3* P62/PWX2/D2* P61/IRQ15/PWX1/D1* P60/IRQ14/PWX0/D0*
Port 7
P77/AN7 General input port multiplexed with A/D P76/AN6 converter analog input P75/AN5 P74/AN4 P73/AN3 P72/AN2 P71/AN1 P70/AN0 General I/O port multiplexed with interrupt input, A/D converter external trigger input, and SCI_1 and SCI_3 I/O P87/ExIRQ15/TxD3/ ADTRG P86/ExIRQ14/RxD3 P85/ExIRQ13/SCK1 P84/ExIRQ12/SCK3
Same as left
Port 8
Same as left
General I/O port P83/SDA1 multiplexed with IIC_0 P82/SCL1 and IIC_1 I/O P81/SDA0 P80/SCL0
Same as left
NMOS push-pull output
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Section 8 I/O Ports
Port Port 9
Description General I/O port multiplexed with PWMX output and bus control I/O
Single-Chip Mode (EXPE = 0) P97 P96 P95 P94/ExPWX1 P93/ExPWX0 P92 P91 P90
Extended Mode (EXPE = 1) P97/WAIT/CS256 Same as left AS/IOS Same as left P92/HBE P91/AH P90/LBE
PA7/ExIRQ7/EVENT7/A23 PA6/ExIRQ6/EVENT6/A22/LNKSTA PA5/ExIRQ5/EVENT5/A21/WOL PA4/ExIRQ4/EVENT4/A20 PA3/ExIRQ3/EVENT3/A19 PA2/ExIRQ2/EVENT2/A18 PA1/ExIRQ1/EVENT1/A17 PA0/ExIRQ0/EVENT0/A16
Feature of I/O
Port A
General I/O port multiplexed with interrupt input, DTC event counter input, EtherC control I/O, and address output
PA7/ExIRQ7/EVENT7/EXOUT PA6/ExIRQ6/EVENT6/LNKSTA PA5/ExIRQ5/EVENT5/WOL PA4/ExIRQ4/EVENT4 PA3/ExIRQ3/EVENT3 PA2/ExIRQ2/EVENT2 PA1/ExIRQ1/EVENT1 PA0/ExIRQ0/EVENT0
Built-in input pull-up MOS
Port B
General I/O port multiplexed with DTC event counter input and EtherC control I/O General I/O port multiplexed with debounced input, DTC event counter input, and EtherC control I/O
PB7/EVENT15/RM_RX-ER PB6/EVENT14/RM_CRS-DV PB5/EVENT13/ RM_REF-CLK PB4/EVENT12/RM_TX-EN
Same as left
PB3/DB3/EVENT11/RM_RXD1 PB2/DB2/EVENT10/RM_RXD0 PB1/DB1/EVENT9/RM_TXD1 PB0/DB0/EVENT8/RM_TXD0
Same as left
Port C
General I/O port multiplexed with bus control output
PC7 PC6
RD PC6/LWR Same as left NMOS push-pull output
PC5/SDA4 General I/O port multiplexed with IIC_2 PC4/SCL4 PC3/SDA3 to IIC_4 I/O PC2/SCL3 PC1/SDA2 PC0/SCL2
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Section 8 I/O Ports
Port Port D
Description
Single-Chip Mode (EXPE = 0)
Extended Mode (EXPE = 1) Same as left
Feature of I/O NMOS push-pull output Built-in input pull-up MOS
General I/O port PD7/SDA5 multiplexed with IIC_5 PD6/SCL5 I/O PD5/LPCPD General I/O port multiplexed with LPC PD4/CLKRUN PD3/GA20 I/O PD2/PME PD1/LSMI PD0/LSCI
Same as left
Port E
General I/O port PE7/SERIRQ multiplexed with LPC PE6/LCLK I/O PE5/LRESET PE4/LFRAME PE3/LAD3 PE2/LAD2 PE1/LAD1 PE0/LAD0 General I/O port multiplexed with PWMX output and EtherC control I/O PF6/ExPWX2/RS14 PF5/RS13 PF4/RS12 PF3/ExPWX3/RS11 PF2/RS10 PF1/RS9/MDC PF0/RS8/MDIO
Same as left
Port F
Same as left
Note:
*
Available when configured for 16-bit data bus.
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Section 8 I/O Ports
8.1.1
Port 1
Port 1 is an 8-bit I/O port. Port 1 pins can also function as the address bus and address-data multiplex bus pins. The pin functions change according to the operating mode. Port 1 has the following registers. * Port 1 data direction register (P1DDR) * Port 1 data register (P1DR) * Port 1 pull-up MOS control register (P1PCR) (1) Port 1 Data Direction Register (P1DDR)
The individual bits of P1DDR specify input or output for the pins of port 1.
Bit 7 6 5 4 3 2 1 0 Bit Name P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W * * Description * Normal extended mode (ADMXE = 0) When set to 1, the corresponding pins function as address output pins; when cleared to 0, function as input port pins. Address-data multiplex extended mode (ADMXE = 1) These bits correspond to the AD7 to AD0 pins of the address-data multiplex bus. Single-chip mode When set to 1, the corresponding pins function as output port pins; when cleared to 0, function as input port pins.
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(2)
Port 1 Data Register (P1DR)
P1DR stores output data for the port 1 pins.
Bit 7 6 5 4 3 2 1 0 Bit Name P17DR P16DR P15DR P14DR P13DR P12DR P11DR P10DR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description P1DR stores output data for the port 1 pins that are used as the general output port. If this register is read, the P1DR values are read for the bits with the corresponding P1DDR bits set to 1. For the bits with the corresponding P1DDR bits cleared to 0, the pin states are read.
(3)
Port 1 Pull-Up MOS Control Register (P1PCR)
P1PCR controls the port 1 built-in input pull-up MOSs.
Bit 7 6 5 4 3 2 1 0 Bit Name P17PCR P16PCR P15PCR P14PCR P13PCR P12PCR P11PCR P10PCR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description When the pins are in the input state, the corresponding input pull-up MOS is turned on when a P1PCR bit is set to 1. Do not change the initial value when using the address-data multiplex extended bus mode.
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(4)
Pin Functions
The relationship between the register settings and the pin function is shown below. (a) Extended Mode (EXPE = 1)
The pin function is switched as shown below according to the P1nDDR bit.
P1nDDR ADMXE ABW, ABW256 Pin function 0 X Either bit is 0 (8/16-bit bus) ADn input/output pin 0 1 Both bits are 1 (8-bit bus) P1n input pin 0 X 1 1 Either bit is 0 (8/16-bit bus) Setting prohibited Both bits are 1 (8-bit bus) P1n output pin
P1n input pin
An output pin
[Legend] n = 7 to 0, X: Don't care.
(b)
Single-Chip Mode (EXPE = 0)
The pin function is switched as shown below according to the P1nDDR bit.
P1nDDR Pin function [Legend] n = 7 to 0 0 P1n input pin 1 P1n output pin
(5)
Port 1 Input Pull-Up MOS
Port 1 has built-in input pull-up MOSs that can be controlled by software. The input pull-up MOS can be used regardless of the operating mode. Table 8.2 summarizes the input pull-up MOS states. Table 8.2
Reset Off
Port 1 Input Pull-Up MOS States
Hardware Standby Software Standby Mode Mode Off On/Off In Other Operations On/Off
[Legend] Off: Always off. On/Off: On when P1DDR = 0 and P1PCR = 1; otherwise off.
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Section 8 I/O Ports
8.1.2
Port 2
Port 2 is an 8-bit I/O port. Port 2 pins can also function as the SCIF modem control signal, address bus, and address-data multiplex bus pins. The pin functions change according to the operating mode. Port 2 has the following registers. * Port 2 data direction register (P2DDR) * Port 2 data register (P2DR) * Port 2 pull-up MOS control register (P2PCR) (1) Port 2 Data Direction Register (P2DDR)
The individual bits of P2DDR specify input or output for the pins of port 2.
Bit 7 6 5 4 3 2 1 0 Bit Name P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W * Normal extended mode (ADMXE = 0) When set to 1, the corresponding pins function as address output pins; when cleared to 0, function as input port pins. The address output pins used are in accord with the settings of the IOSE and CS256E bits of SYSCR. * Address-data multiplex extended mode (ADMXE = 1) These bits correspond to the AD11 to AD8 pins of the address-data multiplex bus. * Single-chip mode When set to 1, the corresponding pins function as output port pins; when cleared to 0, function as input port pins. Description When set to 1, the corresponding pins function as output port pins; when cleared to 0, function as input port pins.
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Section 8 I/O Ports
(2)
Port 2 Data Register (P2DR)
P2DR stores output data for the port 2 pins.
Bit 7 6 5 4 3 2 1 0 Bit Name P27DR P26DR P25DR P24DR P23DR P22DR P21DR P20DR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description P2DR stores output data for the port 2 pins that are used as the general output port. If this register is read, the P2DR values are read for the bits with the corresponding P2DDR bits set to 1. For the bits with the corresponding P2DDR bits cleared to 0, the pin states are read.
(3)
Port 2 Pull-Up MOS Control Register (P2PCR)
P2PCR controls the port 2 built-in input pull-up MOSs.
Bit 7 6 5 4 3 2 1 0 Bit Name P27PCR P26PCR P25PCR P24PCR P23PCR P22PCR P21PCR P20PCR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W When the pins are in the input state, the corresponding input pull-up MOS is turned on when a P2PCR bit is set to 1. Do not change the initial value when using the address-data multiplex extended bus mode. Description When the pins are in the input state, the corresponding input pull-up MOS is turned on when a P2PCR bit is set to 1.
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(4)
Pin Functions
The relationship between the register settings and the pin function is shown below. (a) Extended Mode (EXPE = 1)
* P27 to P24 The pin function is the same as that in single-chip mode. * P23 The pin function is switched as shown below according to the combination of the CS256E and IOSE bits in SYSCR, the ADFULLE bit in BCR2 of the BSC, and the P23DDR bit. Address 11 in the table below is expressed by the following logical expression. Address 11 = 1: ADFULLE * CS256E * IOSE
P23DDR ADMXE Address 11 Pin function 0 X 0 1 X 0 0 1 1 1 X
P23 input pin AD11 input/output A11 output pin P23 output pin AD11 input/output pin pin
* P22 to P20
P2nDDR ADMXE Pin function [Legend] 0 P2n input pin 0 1 ADm input/output pin 0 Am output pin 1 1 ADm input/output pin
m = 10 to 8, n = 2 to 0, X: Don't care.
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(b)
Single-Chip Mode (EXPE = 0)
* P27/DTR The pin function is switched as shown below according to the combination of the SCIFE bit in HICR5 of the LPC, the SCIFOE1 and SCIFOE0 bits in SCIFCR of the SCIF, and the P27DDR bit.
SCIFE SCIFOE1, SCIFOE0 P27DDR Pin function 0 Other than 10 0 P27 input pin 1 P27 output pin 10 X 0 X1 1 P27 output pin 1 X0 X DTR output pin
DTR output P27 input pin pin
[Legend] X: Don't care.
* P26/DSR, P25/RI, P24/DCD The pin function is switched as shown below according to the P2nDDR bit.
P2nDDR Pin function [Legend] n = 6 to 4 0 P2n input pin DSR/RI/DCD input pin 1 P2n output pin
* P23 to P20 The pin function is switched as shown below according to the P2nDDR bit.
P2nDDR Pin function [Legend] n = 3 to 0 0 P2n input pin 1 P2n output pin
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(5)
Port 2 Input Pull-Up MOS
Port 2 has built-in input pull-up MOSs that can be controlled by software. The input pull-up MOS can be used regardless of the operating mode. Table 8.3 summarizes the input pull-up MOS states. Table 8.3
Reset Off
Port 2 Input Pull-Up MOS States
Hardware Standby Software Standby Mode Mode In Other Operations Off On/Off On/Off
[Legend] Off: Always off. On/Off: On when P2DDR = 0 and P2PCR = 1; otherwise off.
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Section 8 I/O Ports
8.1.3
Port 3
Port 3 is an 8-bit I/O port. Port 3 pins can also function as the bidirectional data bus and debounced input pins. The pin functions change according to the operating mode. Port 3 has the following registers. * Port 3 data direction register (P3DDR) * Port 3 data register (P3DR) * Port 3 pull-up MOS control register (P3PCR) * Noise canceler enable register (P3NCE) * Noise canceler mode control register (P3NCMC) * Noise cancel cycle setting register (NCCS) (1) Port 3 Data Direction Register (P3DDR)
The individual bits of P3DDR specify input or output for the port 3 pins.
Bit 7 6 5 4 3 2 1 0 Bit Name P37DDR P36DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR Initial Value 0 0 0 0 0 0 0 0 R/W Description W W W W W W W W * * Normal extended mode (ADMXE = 0) The pins function as bidirectional data bus pins. Other modes When set to 1, the corresponding pins function as output port pins; when cleared to 0, function as input port pins.
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Section 8 I/O Ports
(2)
Port 3 Data Register (P3DR)
P3DR stores output data for the port 3 pins.
Bit 7 6 5 4 3 2 1 0 Bit Name P37DR P36DR P35DR P34DR P33DR P32DR P31DR P30DR Initial Value 0 0 0 0 0 0 0 0 R/W Description R/W * R/W R/W R/W R/W R/W R/W * R/W Normal extended mode (ADMXE = 0) Since the port 3 pins function as bidirectional data bus pins, the value of this register has no effect on operation. If this register is read, the P3DR values are read for the bits with the corresponding P3DDR bits set to 1. For the bits with the corresponding P3DDR bits cleared to 0, 1 is read. Other modes P3DR stores output data for the port 3 pins that are used as the general output port. If this register is read, the P3DR values are read for the bits with the corresponding P3DDR bits set to 1. For the bits with the corresponding P3DDR bits cleared to 0, the pin states are read.
(3)
Port 3 Pull-Up MOS Control Register (P3PCR)
P3PCR controls the port 3 built-in input pull-up MOSs.
Bit 7 6 5 4 3 2 1 0 Bit Name P37PCR P36PCR P35PCR P34PCR P33PCR P32PCR P31PCR P30PCR Initial Value 0 0 0 0 0 0 0 0 R/W Description R/W * R/W R/W * R/W R/W R/W R/W R/W Normal extended mode (ADMXE = 0) This register has no effect on operation. Other modes When the pins are in the input state, the corresponding input pull-up MOS is turned on when a P3PCR bit is set to 1.
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(4)
Noise Canceler Enable Register (P3NCE)
P3NCE enables or disables the noise canceler circuit at port 3.
Bit 7 6 5 4 3 2 1 0 Bit Name P37NCE P36NCE P35NCE P34NCE P33NCE P32NCE P31NCE P30NCE Initial Value 0 0 0 0 0 0 0 0 R/W Description R/W * R/W R/W R/W R/W R/W R/W R/W * Normal extended mode (ADMXE = 0) The pins function as bidirectional data bus pins. Set this register to 0. Other modes Enables the noise canceler circuit for the corresponding pin and the pin state is fetched into P3DR at the sampling cycle set by NCCS. The operation changes according to the other control bits.
(5)
Noise Canceler Mode Control Register (P3NCMC)
When the noise canceler is enabled, P3NCMC controls whether 1 or 0 is expected for the input signal to port 3 in bit units.
Bit 7 6 5 4 3 2 1 0 Bit Name P37NCMC P36NCMC P35NCMC P34NCMC P33NCMC P32NCMC P31NCMC P30NCMC Initial Value 1 1 1 1 1 1 1 1 R/W Description R/W * R/W R/W * R/W R/W R/W R/W R/W Normal extended mode (ADMXE = 0) This register has no effect on operation. Other modes 1 expected: 1 is stored in the port data register while 1 is input stably. 0 expected: 0 is stored in the port data register while 0 is input stably.
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Section 8 I/O Ports
(6)
Noise Canceler Cycle Setting Register (NCCS)
NCCS controls the sampling cycle of the noise cancelers.
Bit Bit Name Initial Value R/W Undefined 0 0 0 R/W Description Reserved Undefined value is read from these bits. 2 1 0 NCCK2 NCCK1 NCCK0 R/W These bits set the sampling cycle of the noise cancelers. R/W * R/W When = 34 MHz 000: 0.06 s 001: 0.94 s 010: 15.1 s /2 /32 /512 100: 963.8 s /32768 101: 1.9 ms 110: 3.9 ms 111: 7.7 ms /65536 /131072 /262144
7 to 3
011: 240.9 s /8192
/2, /32, /512, /8192, /32768, /65536, /131072, /262144 Sampling clock selection t
Pin input
Latch
Latch
Latch
Match detection circuit
Port data register
t
Sampling clock
Figure 8.1 Noise Canceler Circuit
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Section 8 I/O Ports
P3n input
1 expected P3nDR
0 expected P3nDR
(n = 7 to 0)
Figure 8.2 Noise Canceler Operation (7) (a) Pin Functions Normal Extended Mode
Port 3 pins are automatically set to function as bidirectional data bus pins. (b) Address-Data Multiplex Extended Mode
The operation is the same as that in single-chip mode. (c) Single-Chip Mode
The pin function is switched as shown below according to the combination of the P3nDDR bit and the P3nNCE bit.
P3nDDR P3nNCE Pin function 0 P3n input pin 0 1 ExDBn input 1 X P3n output pin
[Legend] n = 7 to 0, X: Don't care.
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(8)
Port 3 Input Pull-Up MOS
Port 3 has built-in input pull-up MOSs that can be controlled by software. The input pull-up MOS can be used in single-chip mode and address-data multiplex extended mode. Table 8.4 summarizes the input pull-up MOS states. Table 8.4
Mode Normal extended mode (EXPE = 1, ADMXE = 0) Address-data multiplex extended mode (EXPE = 1, ADMXE = 1) [Legend] Off: Always off. On/Off: On when input state and P3PCR = 1; otherwise off.
Port 3 Input Pull-Up MOS States
Reset Off Hardware Standby Mode Off Off Software Standby In Other Mode Operations Off On/Off Off On/Off
Single-chip mode (EXPE = 0) Off
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Section 8 I/O Ports
8.1.4
Port 4
Port 4 is an 8-bit I/O port. Port 4 pins can also function as the external interrupt input, de-bounced input, bidirectional data bus, address bus, and address-data multiplex bus pins. Port 4 has the following registers. * Port 4 data direction register (P4DDR) * Port 4 data register (P4DR) * Port 4 pull-up MOS control register (P4PCR) * Noise canceler enable register (P4BNCE) * Noise canceler mode control register (P4BNCMC) * Noise cancel cycle setting register (NCCS) (1) Port 4 Data Direction Register (P4DDR)
The individual bits of P4DDR specify input or output for the port 4 pins. P4DDR is initialized only by a system reset, and retains the value even if an internal reset signal of the WDT is generated.
Bit 7 6 5 4 Bit Name P47DDR P46DDR P45DDR P44DDR Initial Value 0 0 0 0 R/W Description W W W W * * Normal extended mode (ADMXE = 0) When set to 1, the corresponding pins function as address output pins; when cleared to 0, function as input port pins. The address output pins used are in accord with the settings of the IOSE and CS256E bits of SYSCR. Address-data multiplex extended mode (ADMXE = 1) These bits correspond to the AD15 to AD12 pins of the address-data multiplex bus. * Single-chip mode When set to 1, the corresponding pins function as output port pins; when cleared to 0, function as input port pins.
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Section 8 I/O Ports
Bit 3 2 1 0
Bit Name P43DDR P42DDR P41DDR P40DDR
Initial Value 0 0 0 0
R/W Description W W W W * * Normal extended mode (16-bit bus) These bits have no effect on operation. Other modes If port 4 pins are specified for use as the general I/O port, the corresponding pins function as output port when the P4DDR bits are set to 1, and as input port when cleared to 0.
(2)
Port 4 Data Register (P4DR)
P4DR stores output data for the port 4 pins. P4DR is initialized only by a system reset, and retains the value even if an internal reset signal of the WDT is generated.
Bit 7 6 5 4 3 2 1 0 Bit Name P47DR P46DR P45DR P44DR P43DR P42DR P41DR P40DR Initial Value 0 0 0 0 0 0 0 0 R/W Description R/W These bits store output data for the port 4 pins that are used as the general output port. R/W If this register is read, the P4DR values are read for the R/W bits with the corresponding P4DDR bits set to 1. For the R/W bits with the corresponding P4DDR bits cleared to 0, the pin states are read. R/W * R/W R/W R/W Normal extended mode (16-bit data bus) Since the corresponding pins function as bidirectional data bus pins, the value in these bits has no effect on operation. If this register is read, the P4DR values are read for the bits with the corresponding P4DDR bits set to 1. For the bits with the corresponding P4DDR bits cleared to 0, 1 is read. * Other modes These bits store output data for the port 4 pins that are used as the general output port. If this register is read, the P4DR values are read for the bits with the corresponding P4DDR bits set to 1. For the bits with the corresponding P4DDR bits cleared to 0, the pin states are read.
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Section 8 I/O Ports
(3)
Port 4 Pull-Up MOS Control Register (P4PCR)
P4PCR controls the port 4 built-in input pull-up MOSs.
Bit 7 6 5 4 3 2 1 0 Bit Name P47PCR P46PCR P45PCR P44PCR P43PCR P42PCR P41PCR P40PCR Initial Value 0 0 0 0 0 0 0 0 R/W Description R/W * R/W R/W * R/W R/W R/W R/W R/W Normal extended mode (ADMXE = 0) This register has no effect on operation. Other modes When the pins are in the input state, the corresponding input pull-up MOS is turned on when a P4PCR bit is set to 1.
(4)
Noise Canceler Enable Register (P4BNCE)
The individual bits of P4BNCE enable or disable the noise canceler circuits for ports 4 and B.
Bit 7 6 5 4 Bit Name P47NCE P46NCE P45NCE P44NCE Initial Value 0 0 0 0 R/W Description R/W Enables the noise canceler circuit for the corresponding pin and the pin state is fetched into P4DR at the R/W sampling cycle set by NCCS. R/W The operation changes according to the other control R/W bits. R/W Bits for port B setting
3 to 0 PB3NCE to All 0 PB0NCE
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Section 8 I/O Ports
(5)
Noise Canceler Mode Control Register (P4BNCMC)
P4BNCMC controls whether 1 or 0 is expected for the input signal to port 4 in bit units.
Bit 7 6 5 4 Bit Name P47NCMC P46NCMC P45NCMC P44NCMC Initial Value 1 1 1 1 All 1 R/W Description R/W Expected value setting R/W 1 expected: 1 is stored in the port data register while 1 is input stably R/W 0 expected: 0 is stored in the port data register while 0 R/W is input stably R/W Bits for port B setting
3 to 0 PB3NCMC to PB0NCMC
(6)
Noise Canceler Cycle Setting Register (NCCS)
NCCS controls the sampling cycle of the noise cancelers.
Bit Bit Name Initial Value Undefined 0 0 0 R/W R/W R/W R/W R/W Description Reserved Undefined value is read from these bits. 2 1 0 NCCK2 NCCK1 NCCK0 These bits set the sampling cycle of the noise cancelers. * When = 34 MHz 000: 0.06 s 001: 0.94 s 010: 15.1 s /2 /32 /512 100: 963.8 s /32768 101: 1.9 ms 110: 3.9 ms 111: 7.7 ms /65536 /131072 /262144
7 to 3
011: 240.9 s /8192
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Section 8 I/O Ports
/2, /32, /512, /8192, /32768, /65536, /131072, /262144 Sampling clock selection t
Pin input
Latch
Latch
Latch
Match detection circuit
Port data register
Sampling clock
Figure 8.3 Noise Canceler Circuit
P4n input
1 expected P4nDR
0 expected P4nDR (n = 7 to 4)
Figure 8.4 Noise Canceler Operation
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Section 8 I/O Ports
(7)
Pin Functions
The relationship between the register settings and the pin function is shown below. (a) Normal Extended Mode
* P47 to P44 The pin function is switched as shown below according to the combination of the CS256E and IOSE bits in SYSCR, the ADFULLE bit in BCR2 of the BSC, and the P4nDDR bit. Address 13 in the table below is expressed by the following logical expression. Address 13 = 1: ADFULLE * CS256E * IOSE
P4nDDR Address 13 Pin function 0 X P4n input pin 0 Am output pin 1 1 P4n output pin
[Legend] m = 15 to 12, n = 7 to 4 X: Don't care.
* P43 to P40 Port pins 43 to 40 function as bidirectional data bus pins in 16-bit bus extension, and can be used as general I/O port in 8-bit bus extension. (b) Address-Data Multiplex Extended Mode
Port pins 47 to 44 are automatically set to function as address bus pins. Port pins 43 to 40 can be used as general I/O port pins.
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(c)
Single-Chip Mode
The relationship between register setting values and pin functions are as follows. * P47 to P44 The pin function is switched as shown below according to the P4nDDR bit and the P4nNCE bit. When the ISSn bit in ISSR is cleared to 0 and the IRQnE bit in IER of the interrupt controller is set to 1, the pin can be used as the IRQn input pin. To use as the IRQn input pin, clear the P4nDDR bit to 0.
P4nDDR P4nNCE Pin function 0 P4n input IRQn input [Legend] n = 7 to 4 X: Don't care. 0 1 DBn input IRQn input (with the noise canceler) 1 X P4n output
The pin function is switched as shown below according to the P4nDDR bit. When the ISSn bit in ISSR is cleared to 0 and the IRQnE bit in IER of the interrupt controller is set to 1, the pin can be used as the IRQn input pin. To use as the IRQn input pin, clear the P4nDDR bit to 0. * P43 to P40
P4nDDR Pin function [Legend] n = 3 to 0 0 P4n input pin IRQn input pin 1 P4n output pin
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(8)
Port 4 Input Pull-Up MOS
Port 4 has built-in input pull-up MOSs that can be controlled by software. The input pull-up MOS can be used in single-chip mode and address-data multiplex extended mode. Table 8.5 summarizes the input pull-up MOS states. Table 8.5
Mode Normal extended mode (EXPE = 1, ADMXE = 0) Address-data multiplex extended mode (EXPE = 1, ADMXE = 1) [Legend] Off: Always off. On/Off: On when input state and P4PCR = 1; otherwise off.
Port 4 Input Pull-Up MOS States
Reset Off Hardware Standby Mode Off Off Software Standby In Other Mode Operations Off On/Off Off On/Off
Single-chip mode (EXPE = 0) Off
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Section 8 I/O Ports
8.1.5
Port 5
Port 5 is an 8-bit I/O port. Port 5 pins can also function as the SCIF, SCI_1, and SSU input/output, bus control output, system clock output, external subclock input, and interrupt input pins. Port 5 has the following registers. * Port 5 data direction register (P5DDR) * Port 5 data register (P5DR) (1) Port 5 Data Direction Register (P5DDR)
The individual bits of P5DDR specify input or output for the port 5 pins.
Bit 7 Bit Name P57DDR Initial Value 0 R/W W Description If port 5 pins are specified for use as the general I/O port, the corresponding pins function as output port when the P5DDR bits are set to 1, and as input port when cleared to 0. The corresponding port 5 pin functions as the system clock output pin () when this bit is set to 1, and as the general I/O port when cleared to 0. If port 5 pins are specified for use as the general I/O port, the corresponding pins function as output port when the P5DDR bits are set to 1, and as input port when cleared to 0.
6
P56DDR
0
W
5 4 3 2 1 0
P55DDR P54DDR P53DDR P52DDR P51DDR P50DDR
0 0 0 0 0 0
W W W W W W
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(2)
Port 5 Data Register (P5DR)
P5DR stores output data for the port 5 pins.
Bit 7 6 5 4 3 2 1 0 Note: Bit Name P57DR P56DR P55DR P54DR P53DR P52DR P51DR P50DR * Initial Value 0 Undefined* 0 0 0 0 0 0 R/W R/W R R/W R/W R/W R/W R/W R/W Description P5DR stores output data for the port 5 pins that are used as the general output port. If this register is read, the P5DR values are read for the bits with the corresponding P5DDR bits set to 1. For the bits with the corresponding P5DDR bits cleared to 0, the pin states are read.
The initial value is determined in accordance with the pin state of P56.
(3) (a)
Pin Functions Normal Extended Mode and Address-Data Multiplex Extended Mode
Port pin 57 is automatically set to function as a bus control output pin. The functions of port pins 56 to 50 are the same as those in single-chip mode. (b) Single-Chip Mode
Port 5 pins can operate as the SCIF, SCI_1, and SSU input/output, noise canceler input, or general I/O port pins. The relationship between register setting values and pin functions are as follows. * P57 The pin function is switched as shown below according to the P57DDR bit.
P57DDR Pin function 0 P57 input pin 1 P57 output pin
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* P56/EXCL/ The pin function is switched as shown below according to the combination of the EXCLE bit in LPWRCR and the P56DDR bit.
P56DDR EXCLE Pin function [Legend] X: Don't care. 0 P56 input pin 0 1 EXCL input pin 1 X output pin
* P55/IRQ13/SSI The pin function is switched as shown below according to the RE bit in SSER of the SSU and the P55DDR bit. When the ISS13 bit in ISSR16 is cleared to 0 and the IRQ13E bit in IER16 of the interrupt controller is set to 1, this pin can be used as the IRQ13 input pin. To use as the IRQ13 input pin, clear the P55DDR bit to 0.
RE P55DDR Pin function 0 P55 input pin IRQ13 input pin [Legend] X: Don't care. 0 1 P55 output pin 1 X SSI input pin
* P54/IRQ12/SSO The pin function is switched as shown below according to the TE bit in SSER of the SSU and the P54DDR bit. When the ISS12 bit in ISSR16 is cleared to 0 and the IRQ12E bit in IER16 of the interrupt controller is set to 1, this pin can be used as the IRQ12 input pin. To use as the IRQ12 input pin, clear the P54DDR bit to 0.
TE P54DDR Pin function 0 P54 input pin IRQ12 input pin [Legend] X: Don't care. 0 1 P54 output pin 1 X SSO output pin
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* P53/IRQ11/RxD1 The pin function is switched as shown below according to the combination of the RE bit in SCR of SCI_1 and the P53DDR bit. When the ISS11 bit in ISSR16 is cleared to 0 and the IRQ11E bit in IER16 of the interrupt controller is set to 1, this pin can be used as the IRQ11 input pin. To use as the IRQ11 input pin, clear the P53DDR bit to 0.
RE P53DDR Pin function 0 P53 input pin IRQ11 input pin [Legend] X: Don't care. 0 1 P53 output pin 1 X RxD1 input pin
* P52/IRQ10/TxD1 The pin function is switched as shown below according to the combination of the TE bit in SCR of SCI_1 and the P52DDR bit. When the ISS10 bit in ISSR16 is cleared to 0 and the IRQ10E bit in IER16 of the interrupt controller is set to 1, this pin can be used as the IRQ10 input pin. To use as the IRQ10 input pin, clear the P52DDR bit to 0.
TE P52DDR Pin function 0 P52 input pin IRQ10 input pin [Legend] X: Don't care. 0 1 P52 output pin 1 X TxD1 output pin
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* P51/IRQ9/RxDF The pin function is switched as shown below according to the combination of the enable/disable setting of the SCIF and the P51DDR bit. When the ISS9 bit in ISSR16 is cleared to 0 and the IRQ9E bit in IER16 of the interrupt controller is set to 1, this pin can be used as the IRQ9 input pin. To use as the IRQ9 input pin, clear the P51DDR bit to 0.
SCIF P51DDR Pin function 0 P51 input pin IRQ9 input pin [Legend] X: Don't care. Disabled 1 P51 output pin Enabled X RxDF input pin
* P50/IRQ8/TxDF The pin function is switched as shown below according to the combination of the enable/disable setting of the SCIF and the P50DDR bit. When the ISS8 bit in ISSR16 is cleared to 0 and the IRQ8E bit in IER16 of the interrupt controller is set to 1, this pin can be used as the IRQ8 input pin. To use as the IRQ8 input pin, clear the P50DDR bit to 0.
SCIF P50DDR Pin function 0 P50 input pin IRQ8 input pin [Legend] X: Don't care. Disabled 1 P50 output pin Enabled X TxDF output pin
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Section 8 I/O Ports
8.1.6
Port 6
Port 6 is an 8-bit I/O port. Port 6 pins can also function as the bidirectional data bus, PWMX output, SCIF and SSU control input/output, and interrupt input pins. The pin functions change according to the operating mode. In addition, port 6 pins can also be used as the extended data bus pins (D0 to D0). Port 6 has the following registers. * Port 6 data direction register (P6DDR) * Port 6 data register (P6DR) * Port 6 pull-up MOS control register (P6PCR) (1) Port 6 Data Direction Register (P6DDR)
The individual bits of P6DDR specify input or output for the pins of port 6.
Bit 7 6 5 4 3 2 1 0 Bit Name P67DDR P66DDR P65DDR P64DDR P63DDR P62DDR P61DDR P60DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W * * Normal extended mode (16-bit bus) These bits have no effect on operation. Other modes If port 6 pins are specified for use as the general I/O port, the corresponding pins function as output port when the P6DDR bits are set to 1, and as input port when cleared to 0. Description If port 6 pins are specified for use as the general I/O port, the corresponding pins function as output port when the P6DDR bits are set to 1, and as input ports when cleared to 0.
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(2)
Port 6 Data Register (P6DR)
P6DR stores output data for the port 6 pins.
Bit 7 6 5 4 3 2 1 0 Bit Name P67DR P66DR P65DR P64DR P63DR P62DR P61DR P60DR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description These bits store output data for the port 6 pins that are used as the general output port. If this register is read, the P6DR values are read for the bits with the corresponding P6DDR bits set to 1. For the bits with the corresponding P6DDR bits cleared to 0, the pin states are read. * Normal extended mode (16-bit data bus) Since the corresponding pins function as bidirectional data bus pins, the value in these bits has no effect on operation. If this register is read, the P6DR values are read for the bits with the corresponding P6DDR bits set to 1. For the bits with the corresponding P6DDR bits cleared to 0, 1 is read. * Other modes These bits store output data for the port 6 pins that are used as the general output port. If this register is read, the P6DR values are read for the bits with the corresponding P6DDR bits set to 1. For the bits with the corresponding P6DDR bits cleared to 0, the pin states are read.
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(3)
Port 6 Pull-Up MOS Control Register (P6PCR)
P6PCR controls the port 6 built-in input pull-up MOSs.
Bit 7 6 5 4 3 2 1 0 Bit Name P67PCR P66PCR P65PCR P64PCR P23PCR P62PCR P61PCR P60PCR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W * Description * Normal extended mode (16-bit bus) This register has no effect on operation. Other modes When the pins are in the input state, the corresponding input pull-up MOS is turned on when a P6PCR bit is set to 1.
(4) (a)
Pin Functions Normal Extended Mode
* 16-bit bus mode Port pins 63 to 60 are automatically set to function as bidirectional data bus pins. * 8-bit bus mode The operation is the same as that in single-chip mode. (b) Address-Data Multiplex Extended Mode
The operation is the same as that in single-chip mode. (c) Single-Chip Mode
Port 6 pins can operate as the PWMX output, SCIF and SSU control input/output, interrupt input, or general I/O port pins. The relationship between register setting values and pin functions are as follows.
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* P67/ExIRQ8/SSCK The pin function is switched as shown below according to the SCKS bit in SSCRH of the SSU and the P67DDR bit. When the ISS8 bit in ISSR16 is set to 1, this pin can be used as the ExIRQ8 input pin. To use as the ExIRQ8 input pin, clear the P67DDR bit to 0.
SCKS P67DDR Pin function 0 P67 input pin ExIRQ8 input pin [Legend] X: Don't care. 0 1 P67 output pin 1 X SSCK I/O pin
* P66/ExIRQ9/SCS The pin function is switched as shown below according to the CSS1 and CSS0 bits in SSCRH of the SSU and the P66DDR bit. When the ISS9 bit in ISSR16 is set to 1, this pin can be used as the ExIRQ9 input pin. To use as the ExIRQ9 input pin, clear the P66DDR bit to 0.
CSS1, CSS0 P66DDR Pin function 0 P66 input pin ExIRQ9 input pin [Legend] X: Don't care. 00 1 P66 output pin 01 or 1X X SCS I/O pin
* P65/ExIRQ10/RTS The pin function is switched as shown below according to the combination of the enable/disable setting of the SCIF and the P65DDR bit. When the ISS10 bit in ISSR16 is set to 1, this pin can be used as the ExIRQ10 input pin. To use as the ExIRQ10 input pin, clear the P65DDR bit to 0.
SCIF P65DDR Pin function 0 P65 input pin IRQ10 input pin [Legend] X: Don't care. Disabled 1 P65 output pin Enabled X RTS output pin
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* P64/ExIRQ11/CTS The pin function is switched as shown below according to the combination of the enable/disable setting of the SCIF and the P64DDR bit. When the ISS10 bit in ISSR16 is set to 1, this pin can be used as the ExIRQ11 input pin. To use as the ExIRQ11 input pin, clear the P64DDR bit to 0.
SCIF P64DDR Pin function 0 P64 input pin IRQ11 input pin [Legend] X: Don't care. Disabled 1 P64 output pin Enabled X CTS input pin
* P63/PWX3 The pin function is switched as shown below according to the combination of the OEB bit in DACR and the PWMXS bit in PTCNT0 of PWMX_1 and the P63DDR bit.
P63DDR PWMXS OEB Pin function 0 0 0 1 X 0 0 1 1 X X 0 1 PWX3 output pin
P63 input pin
P63 output pin
[Legend] X: Don't care.
* P62/PWX2 The pin function is switched as shown below according to the combination of the OEA bit in DACR and the PWMXS bit in PTCNT0 of PWMX_1 and the P62DDR bit.
P62DDR PWMXS OEA Pin function 0 0 0 1 X 0 0 1 1 X X 0 1 PWX2 output pin
P62 input pin
P62 output pin
[Legend] X: Don't care.
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* P61/IRQ15/PWX1 The pin function is switched as shown below according to the combination of the OEB bit in DACR and the PWMXS bit in PTCNT0 of PWMX_0 and the P61DDR bit. To use this pin as the IRQ15 input pin, clear the P61DDR bit to 0.
P61DDR PWMXS OEB Pin function 0 0 0 1 X 0 0 1 1 X X 0 1 PWX1 output pin
P61 input pin IRQ15 input pin
P61 output pin
[Legend] X: Don't care.
* P60/IRQ14/PWX1 The pin function is switched as shown below according to the combination of the OEA bit in DACR and the PWMXS bit in PTCNT0 of PWMX_0 and the P60DDR bit. To use this pin as the IRQ14 input pin, clear the P60DDR bit to 0.
P60DDR PWMXS OEA Pin function 0 0 0 1 X 0 0 1 1 X X 0 1 PWX0 output pin
P60 input pin IRQ14 input pin
P60 output pin
[Legend] X: Don't care.
(5)
Port 6 Input Pull-Up MOS
Port 6 has built-in input pull-up MOSs that can be controlled by software. Table 8.6 summarizes the input pull-up MOS states. Table 8.6
Reset Off
Port 6 Input Pull-Up MOS States
Hardware Standby Mode Off Software Standby Mode On/Off In Other Operations On/Off
[Legend] Off: Always off. On/Off: On when input state, P6DDR = 0, and P6PCR = 1; otherwise off.
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8.1.7
Port 7
Port 7 is an 8-bit input port. Port 7 pins can also function as the A/D converter analog input pins. Port 7 has the following register. * Port 7 input data register (P7PIN) (1) Port 7 Input Data Register (P7PIN)
P7PIN indicates the states of the port 7 pins.
Bit 7 6 5 4 3 2 1 0 Note: Bit Name P77PIN P76PIN P75PIN P74PIN P73PIN P72PIN P71PIN P70PIN * Initial Value Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* R/W R R R R R R R R Description When this register is read, the pin states are read. Since this register is allocated to the same address as PBDDR, writing to this register writes data to PBDDR and the port B setting is changed.
The initial values are determined in accordance with the pin states of P77 to P70.
(2)
Pin Functions
Each pin of port 7 can also be used as the analog input pins of the A/D converter (AN0 to AN7). * P77/AN7 The pin function is switched as shown below according to the CH2 to CH0 bits in ADCSR of the A/D converter. Do not set these bits to other values than those shown in the following table.
CH2 to CH0 Pin function B'111 AN7 input pin Other than B'111 P77 input pin
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* P76/AN6 The pin function is switched as shown below according to the combination of the SCANE bit in ADCR and the CH2 to CH0 bits in ADCSR of the A/D converter. Do not set these bits to other values than those shown in the following table.
SCANE CH2 to CH0 Pin function B'110 AN6 input pin 0 Other than B'110 P76 input pin B'110 to B'111 AN6 input pin 1 B'000 to B'101 P76 input pin
* P75/AN5 The pin function is switched as shown below according to the combination of the SCANE bit in ADCR and the CH2 to CH0 bits in ADCSR of the A/D converter. Do not set these bits to other values than those shown in the following table.
SCANE CH2 to CH0 Pin function B'101 AN5 input pin 0 Other than B'101 P75 input pin B'101 to B'111 AN5 input pin 1 B'000 to B'100 P75 input pin
* P74/AN4 The pin function is switched as shown below according to the combination of the SCANE bit in ADCR and the CH2 to CH0 bits in ADCSR of the A/D converter. Do not set these bits to other values than those shown in the following table.
SCANE CH2 to CH0 Pin function B'100 AN4 input pin 0 Other than B'100 P74 input pin B'100 to B'111 AN4 input pin 1 B'000 to B'011 P74 input pin
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* P73/AN3 The pin function is switched as shown below according to the combination of the SCANE and SCANE bits in ADCR and the CH2 to CH0 bits in ADCSR of the A/D converter. Do not set these bits to other values than those shown in the following table.
SCANE SCANS CH2 to CH0 Pin function
B'011 AN3 input pin
0 X
Other than B'011 P73 input pin B'011 AN3 input pin
1 0
Other than B'011 P73 input pin
1
B'011 to B'111 B'000 to B'010 AN3 input pin P73 input pin
[Legend] X: Don't care.
* P72/AN2 The pin function is switched as shown below according to the combination of the SCANE and SCANE bits in ADCR and the CH2 to CH0 bits in ADCSR of the A/D converter. Do not set these bits to other values than those shown in the following table.
SCANE SCANS CH2 to CH0 Pin function
B'010
0 X
Other than B'010
1 0
B'010 to B'011
1
B'000 to B'001 P72 input pin
Other than B'010 to B'111 B'010 to B'011 P72 input pin AN2 input pin
AN2 input pin P72 input pin AN2 input pin
[Legend] X: Don't care.
* P71/AN1 The pin function is switched as shown below according to the combination of the SCANE and SCANS bits in ADCR and the CH2 to CH0 bits in ADCSR of the A/D converter. Do not set these bits to other values than those shown in the following table.
SCANE SCANS CH2 to CH0
B'001
0 X
Other than B'001 B'001 to B'011
1 0
Other than B'001 to B'011 B'001 to B'111
1
B'000
Pin function
AN1 input pin P71 input pin AN1 input pin P71 input pin AN1 input pin P71 input pin
[Legend] X: Don't care.
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* P70/AN0 The pin function is switched as shown below according to the combination of the SCANE and SCANS bits in ADCR and the CH2 to CH0 bits in ADCSR of the A/D converter. Do not set these bits to other values than those shown in the following table.
SCANE SCANS CH2 to CH0 Pin function
B'000 AN0 input pin
0 X
Other than B'000 P70 input pin B'000 to B'011 AN0 input pin
1 0
Other than B'000 to B'011 P70 input pin
1
B'000 to B'111 AN0 input pin
[Legend] X: Don't care.
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Section 8 I/O Ports
8.1.8
Port 8
Port 8 is an 8-bit I/O port. Port 8 pins can also function as the A/D converter external trigger input, SCI_1 and SCI_3 input/output, IIC_0 and IIC_1 input/output, and interrupt input pins. Pins 83 to 80 perform the NMOS push-pull output. Port 8 has the following registers. * Port 8 data direction register (P8DDR) * Port 8 data register (P8DR) (1) Port 8 Data Direction Register (P8DDR)
The individual bits of P8DDR specify input or output for the port 8 pins.
Bit 7 6 5 4 3 2 1 0 Bit Name P87DDR P86DDR P85DDR P84DDR P83DDR P82DDR P81DDR P80DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description If port 8 pins are specified for use as the general I/O port, the corresponding pins function as output port when the P8DDR bits are set to 1, and as input port when cleared to 0. Since this register is allocated to the same address as PBPIN, states of the port 8 pins are when this register is read.
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(2)
Port 8 Data Register (P8DR)
P8DR stores output data for the port 8 pins.
Bit 7 6 5 4 3 2 1 0 Bit Name P87DR P86DR P85DR P84DR P83DR P82DR P81DR P80DR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description P8DR stores output data for the port 8 pins that are used as the general output port. If this register is read, the P8DR values are read for the bits with the corresponding P8DDR bits set to 1. For the bits with the corresponding P8DDR bits cleared to 0, the pin states are read.
(3)
Pin Functions
The relationship between register setting values and pin functions are as follows. * P87/ExIRQ15/TxD3/ADTRG The pin function is switched as shown below according to the combination of the TE bit in SCR of SCI_3, the SMIF bit in SCMR, and the P87DDR bit. When the TRGS1 and EXTRGS bits are both set to 1 and the TRGS0 bit is cleared to 0 in ADCR of the A/D converter, this pin can be used as the ADTRG input pin. When the ISS15 bit in ISSR16 is set to 1, this pin can be used as the ExIRQ15 input pin. To use this pin as the ExIRQ15 input pin, clear the P87DDR bit to 0.
P87DDR SMIF TE Pin function 0 0 P87 input pin ExIRQ15 input pin/ ADTRG input pin [Legend] X: Don't care. 0 1 X 0 0 1 X 1 0 1 TxD3 output pin
P87 output pin
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* P86/ExIRQ14/RxD3 The pin function is switched as shown below according to the combination of the RE bit in SCR of SCI_3, the SMIF bit in SCMR, and the P86DDR bit. When the ISS14 bit in ISSR16 is set to 1, this pin can be used as the ExIRQ14 input pin. To use this pin as the ExIRQ14 input pin, clear the P86DDR bit to 0.
P86DDR SMIF RE Pin function 0 P86 input pin ExIRQ14 input pin 0 1 RxD3 input pin RxD3 input/output pin 0 1 1 0 0 P86 output pin
* P85/ExIRQ13/SCK1 The pin function is switched as shown below according to the combination of the C/A bit in SMR of SCI_1, the CKE1 and CKE0 bits in SCR, and the P85DDR bit. When the ISS13 bit in ISSR16 is set to 1, this pin can be used as the ExIRQ13 input pin. To use this pin as the ExIRQ13 input pin, clear the P85DDR bit to 0.
CKE1 C/A CKE0 P85DDR Pin function 0 P85 input pin ExIRQ13 input pin [Legend] X: Don't care. 0 1 P85 output pin 0 1 X SCK1 output pin 0 1 X X SCK1 output pin 1 X X X SCK1 input pin
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* P84/ExIRQ12/SCK3 The pin function is switched as shown below according to the combination of the C/A bit in SMR of SCI_3, the CKE1 and CKE0 bits in SCR, and the P84DDR bit. When the ISS12 bit in ISSR16 is set to 1, this pin can be used as the ExIRQ12 input pin. To use this pin as the ExIRQ12 input pin, clear the P84DDR bit to 0.
CKE1 C/A CKE0 P84DDR Pin function 0 P84 input pin ExIRQ12 input pin [Legend] X: Don't care. 0 1 P84 output pin 0 1 X SCK3 output pin 0 1 X X SCK3 output pin 1 X X X SCK3 input pin
* P83/SDA1 The pin function is switched as shown below according to the combination of the ICE bit in ICCR of IIC_1 and the P83DDR bit. When this pin is used as the P83 output pin, the output format is NMOS push-pull output. The output format for SDA1 is NMOS open-drain output, which allows direct bus drive.
ICE P83DDR Pin function 0 P83 input pin 0 1 P83 output pin 1 X SDA1 input/output pin
[Legend] X: Don't care.
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* P82/SCL1 The pin function is switched as shown below according to the combination of the ICE bit in ICCR of IIC_1 and the P82DDR bit. When this pin is used as the P82 output pin, the output format is NMOS push-pull output. The output format for SCL1 is NMOS open-drain output, which allows direct bus drive.
ICE P82DDR Pin function 0 P82 input pin 0 1 P82 output pin 1 X SCL1 input/output pin
[Legend] X: Don't care.
* P81/SDA0 The pin function is switched as shown below according to the combination of the ICE bit in ICCR of IIC_0 and the P81DDR bit. When this pin is used as the P81 output pin, the output format is NMOS push-pull output. The output format for SDA0 is NMOS open-drain output, which allows direct bus drive.
ICE P81DDR Pin function 0 P81 input pin 0 1 P81 output pin 1 X SDA0 input/output pin
[Legend] X: Don't care.
* P80/SCL0 The pin function is switched as shown below according to the combination of the ICE bit in ICCR of IIC_0 and the P80DDR bit. When this pin is used as the P80 output pin, the output format is NMOS push-pull output. The output format for SCL0 is NMOS open-drain output, which allows direct bus drive.
ICE P80DDR Pin function 0 P80 input pin 0 1 P80 output pin 1 X SCL0 input/output pin
[Legend] X: Don't care.
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Section 8 I/O Ports
8.1.9
Port 9
Port 9 is an 8-bit I/O port. Port 9 pins can function as the bus control input/output pins. The pin functions change according to the operating mode. Port 9 has the following registers. * Port 9 data direction register (P9DDR) * Port 9 data register (P9DR) (1) Port 9 Data Direction Register (P9DDR)
The individual bits of P9DDR specify input or output for the port 9 pins.
Bit 7 6 5 4 3 2 1 0 Bit Name P97DDR P96DDR P95DDR P94DDR P93DDR P92DDR P91DDR P90DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description If port 9 pins are specified for use as the general I/O port, the corresponding pins function as output port when the P9DDR bits are set to 1, and as input port when cleared to 0.
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(2)
Port 9 Data Register (P9DR)
P9DR stores output data for the port 9 pins.
Bit 7 6 5 4 3 2 1 0 Bit Name P97DR P96DR P95DR P94DR P93DR P92DR P91DR P90DR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description P9DR stores output data for the port 9 pins that are used as the general output port. If this register is read, the P9DR values are read for the bits with the corresponding P9DDR bits set to 1. For the bits with the corresponding P9DDR bits cleared to 0, the pin states are read.
(3)
Pin Functions
The relationship between register setting values and pin functions are as follows. * P97/WAIT/CS256 The pin function is switched as shown below according to the operating mode and the combination of the CS256E bit in SYSCR, the WMS1 bit in WSCR and the P97DDR bit.
Operating mode WMS1 CS256E P97DDR Pin function 0 0 1 Extended mode 0 1 X CS256 output pin 1 X X 0 Single-chip mode X X 1
P97 input pin P97 output pin
WAIT input P97 input pin P97 output pin pin
[Legend] X: Don't care.
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* P96 The pin function is switched as shown below according to the P96DDR bit.
P96DDR Pin function 0 P96 input pin 1 P96 output pin
* P95/AS/IOS The pin function is switched as shown below according to the operating mode and the combination of the IOSE bit in SYSCR and the P95DDR bit.
Operating mode P95DDR IOSE Pin function [Legend] X: Don't care. 0 AS output pin Extended mode X 1 IOS output pin 0 X P95 input pin Single-chip mode 1 X P95 output pin
* P94/ExPWX1 The pin function is switched as shown below according to the combination of the OEB bit in DACR and the PWMXS bit in PTCNT0 of the PWMX_0 module and the P94DDR bit.
P94DDR PWMXS OEB Pin function [Legend] X: Don't care. 0 X P94 input pin 0 1 0 0 X P94 output pin 1 1 0 X 1 1 ExPWX1 output pin
* P93/ExPWX0 The pin function is switched as shown below according to the combination of the OEA bit in DACR and the PWMXS bit in PTCNT0 of the PWMX_0 module and the P93DDR bit.
P93DDR PWMXS OEA Pin function [Legend] X: Don't care. 0 X P93 input pin 0 1 0 0 X P93 output pin 1 1 0 X 1 1 ExPWX0 output pin
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* P92/HBE The pin function is switched as shown below according to the operating mode, the OBE bit in PTCNT0, and the P92DDR bit.
Operating mode OBE P92DDR Pin function 0 P92 input pin Extended mode 0 1 1 X 0 P92 input pin P92 output pin HBE output pin Single-chip mode X 1 P92 output pin
[Legend] X: Don't care.
* P91/AH The pin function is switched as shown below according to the operating mode, the ADMXE bit in SYSCR2, and the P91DDR bit.
Operating mode ADMXE P91DDR Pin function [Legend] X: Don't care. 0 P91 input pin Extended mode 0 1 P91 output pin 1 X AH output pin 0 P91 input pin Single-chip mode X 1 P91 output pin
* P90/LBE The pin function is switched as shown below according to the operating mode, the OBE bit in PTCNT0, and the P90DDR bit.
Operating mode OBE P90DDR Pin function [Legend] X: Don't care. 0 P90 input pin Extended mode 0 1 1 X 0 P90 input pin P90 output pin LBE output pin Single-chip mode X 1 P90 output pin
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Section 8 I/O Ports
8.1.10
Port A
Port A is an 8-bit I/O port. Port A pins can also function as the address output, event counter input, EtherC control I/O, and interrupt input pins. Port A has the following registers. PADDR and PAPIN are allocated to the same address. * Port A data direction register (PADDR) * Port A output data register (PAODR) * Port A input data register (PAPIN) (1) Port A Data Direction Register (PADDR)
The individual bits of PADDR specify input or output for the port A pins.
Bit 7 6 5 4 3 2 1 0 Bit Name PA7DDR PA6DDR PA5DDR PA4DDR PA3DDR PA2DDR PA1DDR PA0DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description When set to 1, the corresponding pins function as output port pins; when cleared to 0, function as input port pins. As the address of this register is the same as that of PAPIN, reading from this register indicates the state of port A.
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(2)
Port A Output Data Register (PAODR)
PAODR stores output data for the port A pins.
Bit 7 6 5 4 3 2 1 0 Bit Name PA7ODR PA6ODR PA5ODR PA4ODR PA3ODR PA2ODR PA1ODR PA0ODR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description PAODR stores output data for the port A pins that are used as the general output port.
(3)
Port A Input Data Register (PAPIN)
PAPIN indicates the states of the port A pins.
Bit 7 6 5 4 3 2 1 0 Bit Name PA7PIN PA6PIN PA5PIN PA4PIN PA3PIN PA2PIN PA1PIN PA0PIN Initial Value Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* R/W R R R R R R R R Description Pin states are read from this register. As the address of this register is the same as that of PADDR, writing to this register changes the settings of port A, that have been written to PADDR.
Note: The initial values are determined in accordance with the pin states of PA7 to PA0.
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(4)
Pin Functions
The relationship between the operating mode, register setting values, and pin functions are as follows. (a) Normal Extended Mode
Port A pins can function as address output, interrupt input, event counter input, EtherC control I/O or I/O port pins, and input or output can be specified in bit units. Address 18 and address 13 in the following tables are expressed by the following logical expressions according to the control bits of the bus controller or other module. Address 18 = 1: ADFULLE Address 13 = 1: ADFULLE * CS256E * IOSE * PA7/ExIRQ7/EVENT7/A23/EXOUT The pin function is switched as shown below according to the setting of address 18 and the PA7DDR bit. Setting the ISS7 bit in ISSR makes the pin to function as the ExIRQ7 input pin. When using the pin as the ExIRQ7 input or an EVENT input pin, clear the PA7DDR bit to 0. Though the settings for the EVENT input pin have been made, set the PA7DDR bit to 1 when using the pin as the PA7 or A23 output pin. When the module stop mode is cleared in both the EtherC and E-DMAC, this pin functions as the EXOUT output pin.
PA7DDR Address 18 Pin function [Legend] X: Don't care. 0 X PA7 input pin ExIRQ7 input pin/EVENT7 input pin 1 1 PA7 output pin 1 0 A23 output pin
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* PA6/ExIRQ6/EVENT6/A22/LNKSTA The pin function is switched as shown below according to the setting of address 18 and the PA6DDR bit. Setting the ISS6 bit in ISSR makes the pin to function as the ExIRQ6 input pin. When using the pin as the ExIRQ6 input, or an EVENT input pin, clear the PA6DDR bit to 0. Though the settings for the EVENT input pin have been made, set the PA6DDR bit to 1 when using the pin as the PA6 or A22 output pin. When the module stop mode is cleared in both the EtherC and E-DMAC, this pin functions as the LNKSTA input pin.
PA6DDR Address 18 Pin function PA6 input pin ExIRQ6 input pin/EVENT6 input pin 0 1 PA6 output pin 1 1 0 A22 output pin
* PA5/ExIRQ5/EVENT5/A21/WOL The pin function is switched as shown below according to the setting of the address 18, and the PA5DDR bit. Setting the ISS5 bit in ISSR to 1 makes the pin function as the ExIRQ5 input pin. When using the pin as the ExIRQ5 input, or an EVENT input pin, clear the PA5DDR bit to 0. Though the settings for the EVENT input pin have been made, set the PA5DDR bit to 1 when using the pin as the A21 or PA5 output pin. When the module stop mode is cleared in both the EtherC, and E-DMAC, this pin functions as the WOL output pin.
PA5DDR Address 18 Pin function 0 X PA5 input pin ExIRQ5 input pin/ EVENT5 input pin 1 1 PA5 output pin 1 0 A21 output pin
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* PA4/ExIRQ4/EVENT4/A20, PA3/ExIRQ3/EVENT3/A19, PA2/ExIRQ2/EVENT2/A18 The pin function is switched as shown below according to the setting of address 18 and the PAnDDR bit. Setting the ISSn bit in ISSR makes the pin to function as the ExIRQn input pin. When using the pin as the ExIRQn input or an EVENT input pin, clear the PAnDDR bit to 0. Though the settings for the EVENT input pin have been made, set the PAnDDR bit to 1 when using the pin as the PAn or Am output pin.
PAnDDR Address 18 Pin function [Legend] 0 X PAn input pin ExIRQn input pin/EVENTn input pin n = 4 to 2, m = 20 to 18 X: Don't care 1 1 PAn output pin 1 0 Am output pin
* PA1/ExIRQ1/EVENT1/A17, PA0/ExIRQ0/EVENT0/A16 The pin function is switched as shown below according to the setting of address 13 and the PAnDDR bit. Setting the ISSn bit in ISSR makes the pin to function as the ExIRQn input pin. When using the pin as the ExIRQn input or an EVENT input pin, clear the PAnDDR bit to 0. Though the settings for the EVENT input pin have been made, set the PAnDDR bit to 1 when using the pin as the PAn or Am output pin.
PAnDDR Address 13 Pin function [Legend] 0 X PAn input pin ExIRQn input pin/EVENTn input pin n = 1, 0; m = 17, 16 X: Don't care 1 PAn output pin 1 0 Am output pin
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Section 8 I/O Ports
(b)
Single-Chip Mode and Address-Data Multiplex Extended Mode
Port A pins can also function as interrupt input and event counter input pins. * PA7/ExIRQ7/EVENT7/EXOUT The pin function is switched as shown below according to the PA7DDR bit. Setting the ISS7 bit in ISSR makes the pin to function as the ExIRQ7 input pin. When using this pin as the ExIRQ7 input or EVENT7 input pin, clear the PA7DDR bit to 0. Though the settings for the EVENT input pin have been made, set the PA7DDR bit to 1 to use the pin as the PA7 output pin. When the module stop mode is cleared in both the EtherC and E-DMAC, this pin functions as the EXOUT output pin.
PA7DDR Pin function 0 PA7 input pin ExIRQ7 input pin/EVENT7 input pin 1 PA7 output pin
* PA6/ExIRQ6/EVENT6/LNKSTA The pin function is switched as shown below according to the PA6DDR bit. Setting the ISS6 bit in ISSR makes the pin to function as the ExIRQ6 input pin. When using this pin as the ExIRQ6 input, EVENT6 input, input pin, clear the PA6DDR bit to 0. Though the settings for the EVENT input pin have been made, set the PA6DDR bit to 1 to use the pin as the PA6 output pin. When the module stop mode is cleared in both the EtherC and E-DMAC, this pin functions as the LNKSTA input pin.
PA6DDR Pin function 0 PA6 input pin ExIRQ6 input pin/EVENT6 input pin 1 PA6 output pin
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Section 8 I/O Ports
* PA5/ExIRQ5/EVENT5/WOL The pin function is switched as shown below according to and the PA5DDR bit. Setting the ISS5 bit in ISSR makes the pin to function as the ExIRQ5 input pin. When using this pin as the ExIRQ5 input or EVENT5 input pin, clear the PA5DDR bit to 0. Though the settings for the EVENT input pin have been made, set the PA5DDR bit to 1 to use the pin as the PA5 output pin. When the module stop mode is cleared in both the EtherC, and E-DMAC, this pin functions as the WOL output pin.
PA5DDR Pin function 0 PA5 input pin ExIRQ5 input pin/EVENT5 input pin 1 PA5 output pin
* PA4/ExIRQ4/EVENT4, PA3/ExIRQ3/EVENT3, PA2/ExIRQ2/EVENT2, PA1/ExIRQ1/EVENT1, PA0/ExIRQ0/EVENT0 The pin function is switched as shown below according to the PAnDDR bit. Setting the ISSn bit in ISSR makes the pin to function as the ExIRQn input pin. When using this pin as the ExIRQn input or EVENTn input pin, clear the PAnDDR bit to 0. Though the settings for the EVENT input pin have been made, set the PAnDDR bit to 1 to use the pin as the PAn output pin.
PAnDDR Pin function [Legend] n = 4 to 0 0 PAn input pin ExIRQn input pin/EVENTn input pin 1 PAn output pin
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Section 8 I/O Ports
(5)
Input Pull-Up MOS
Port A has built-in input pull-up MOSs that can be controlled by software. This input pull-up MOS can be used in any operating mode, and can be specified as on or off on a bit-by-bit basis.
PAnDDR PAnODR PAn pull-up MOS [Legend] 1 ON n = 7 to 0, X: Don't care. 0 0 OFF 1 X OFF
The input pull-up MOS is in the off state after a reset and in hardware standby mode. The prior state is retained in software standby mode. Table 8.7 summarizes the input pull-up MOS states. Table 8.7
Reset Off
Input Pull-Up MOS States
Hardware Standby Mode Off Software Standby Mode On/Off In Other Operations On/Off
[Legend] Off: Always off. On/Off: On when PADDR = 0 and PAODR = 1; otherwise off.
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Section 8 I/O Ports
8.1.11
Port B
Port B is an 8-bit I/O port. Port B pins can also function as the bidirectional data bus, de-bounced input, and EtherC control I/O pins. The pin functions change according to the operating mode. Port B has the following registers. * Port B data direction register (PBDDR) * Port B output data register (PBODR) * Port B input data register (PBPIN) * Noise canceler enable register (P4BNCE) * Noise canceler mode control register (P4BNCMC) * Noise cancel cycle setting register (NCCS) (1) Port B Data Direction Register (PBDDR)
The individual bits of PBDDR specify input or output for the pins of port B.
Bit 7 6 5 4 3 2 1 0 Bit Name PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR Initial Value 0 0 0 0 0 0 0 0 R/W Description W W W W W W W W When set to 1, the corresponding pins function as output port pins; when cleared to 0, function as input port pins.
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(2)
Port B Output Data Register (PBODR)
PBDR stores output data for the port B pins.
Bit 7 6 5 4 3 2 1 0 Bit Name PB7DR PB6DR PB5DR PB4DR PB3DR PB2DR PB1DR PB0DR Initial Value 0 0 0 0 0 0 0 0 R/W Description R/W PBODR stores output data for the port B pins that are used as the general output port. R/W R/W R/W R/W R/W R/W R/W
(3)
Port B Input Data Register (PBPIN)
PBPIN indicates the states of the port B pins.
Bit 7 6 5 4 3 2 1 0 Note: Bit Name PB7PIN PB6PIN PB5PIN PB4PIN PB3PIN PB2PIN PB1PIN PB0PIN * Initial Value Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* R/W R R R R R R R R Description When this register is read, the pin states are read. Since this register is allocated to the same address as P8DDR, writing to this register writes data to P8DDR and the port 8 setting is changed.
The initial values are determined in accordance with the pin states of PB7 to PB0.
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(4)
Noise Canceler Enable Register (P4BNCE)
P4BNCE enables or disables the noise canceler circuits of port 4 and port B pins in bit units.
Bit Bit Name Initial Value All 0 0 0 0 0 R/W Description R/W Bits for port 4 setting R/W Enables the noise canceler circuit for the corresponding pin and the pin state is fetched into PBDR at the R/W sampling cycle set by NCCS. R/W The operation changes according to the other control R/W bits. See section 8.1.11 (7), Pin Functions, for details.
7 to 4 P47NCE to P44NCE 3 2 1 0 PB3NCE PB2NCE PB1NCE PB0NCE
(5)
Noise Canceler Mode Control Register (P4BNCMC)
P4BNCMC controls whether 1 or 0 is expected for the input signal to port 4 and port B in bit units.
Bit Bit Name Initial Value All 1 R/W Description R/W Bits for port 4 setting
7 to 4 P47NCMC to P44NCMC 3 2 1 0 PB3NCMC PB2NCMC PB1NCMC PB0NCMC
1 1 1 1
R/W Expected value setting R/W 1 expected: 1 is stored in the port data register while 1 is input stably. R/W 0 expected: 0 is stored in the port data register while 0 R/W is input stably.
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(6)
Noise Canceler Cycle Setting Register (NCCS)
NCCS controls the sampling cycle of the noise cancelers.
Bit Bit Name Initial Value Undefined 0 0 0 R/W Description R/W Reserved Undefined value is read from these bits. 2 1 0 NCCK2 NCCK1 NCCK0 R/W These bits set the sampling cycle of the noise R/W cancelers. R/W * When = 34 MHz 000: 0.06 s 001: 0.94 s 010: 15.1 s /2 /32 /512 100: 963.8 s /32768 101: 1.9 ms 110: 3.9 ms 111: 7.7 ms /65536 /131072 /262144
7 to 3
011: 240.9 s /8192
/2, /32, /512, /8192, /32768, /65536, /131072, /262144 Sampling clock selection t
Pin input
Latch
Latch
Latch
Match detection circuit
Port data register
t
Sampling clock
Figure 8.5 Noise Canceler Circuit
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Section 8 I/O Ports
PBn input
1 expected PBnDR
0 expected PBnDR
(n = 3 to 0)
Figure 8.6 Noise Canceler Operation
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Section 8 I/O Ports
(7)
Pin Functions
* PB7/EVENT15/RM_RX-ER, PB6/EVENT14/RM_CRS-DV, PB5/EVENT13/RM_REF-CLK PB4/EVENT12/RM_TX-EN The pin function is switched as shown below according to the PBnDDR bit. When using this pin as the EVENT input pin, clear the PBnDDR bit to 0. These pins can be used as EtherC I/O pins when the EtherC is enabled.
EtherC, E-DMAC PBnDDR Event counter Pin function [Legend] Note: * Disabled PBn input pin Either of them is stopped 0 Enabled EVENTm input pin 1 X PBn output pin Both of then are stopped X X RM_xxxx EtherC I/O pin
n = 7 to 4, m = 15 to 12, X: Don't care. See section 7.3, DTC Event Counter, for the event counter settings.
* PB3/EVENT11/DB3/RM_RXD1, PB2/EVENT10/DB2/RM_RXD0, PB1/EVENT9/DB1/RM_TXD1, PB0/EVENT8/DB0/RM_TXD0 The pin function is switched as shown below according to the combination of the module stop state in the EtherC, E-DMAC, the PBnDDR bit and the PBnNCE bit.
EtherC, E-DMAC PBnDDR Event counter PBnNCE Pin function [Legend] 0 Disabled 1 Either of them is stopped 0 Enabled X EVENTm input pin 1 X X PBn output pin Both of then are stopped X X X RM_xxxx EtherC I/O pin
PBn input pin
n = 3 to 0, m = 11 to 8, X: Don't care.
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Section 8 I/O Ports
8.1.12
Port C
Port C is an 8-bit I/O port. Port C pins can also function as the bus control output, and IIC_2, IIC_3, and IIC_4 input/output pins. The output format of ports C0 to C5 is NMOS push-pull output. Port C has the following registers. * Port C data direction register (PCDDR) * Port C output data register (PCODR) * Port C input data register (PCPIN) (1) Port C Data Direction Register (PCDDR)
The individual bits of PCDDR specify input or output for the port C pins.
Bit 7 6 5 4 3 2 1 0 Bit Name PC7DDR PC6DDR PC5DDR PC4DDR PC3DDR PC2DDR PC1DDR PC0DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description When set to 1, the corresponding pins function as output port pins; when cleared to 0, function as input port pins. Since this register is allocated to the same address as PCPIN, states of the port C pins are returned when this register is read.
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(2)
Port C Output Data Register (PCODR)
PCODR stores output data for the port C pins.
Bit 7 6 5 4 3 2 1 0 Bit Name PC7ODR PC6ODR PC5ODR PC4ODR PC3ODR PC2ODR PC1ODR PC0ODR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description The PCODR register stores the output data for the pins that are used as the general output port.
(3)
Port C Input Data Register (PCPIN)
PCPIN indicates the pin states of port C.
Bit 7 6 5 4 3 2 1 0 Bit Name PC7PIN PC6 PIN PC5PIN PC4 PIN PC3 PIN PC2 PIN PC1 PIN PC0 PIN Initial Value Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* R/W R R R R R R R R Description When this register is read, the pin states are read. Since this register is allocated to the same address as PCDDR, writing to this register writes data to PCDDR and the port C setting is changed.
Note: The initial values are determined in accordance with the states of PC7 to PC0 pins.
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Section 8 I/O Ports
(4) (a)
Pin Functions Normal Extended Mode and Address-Data Multiplex Extended Mode
Port C pins can also function as the bus control output and IIC_2, IIC_3, and IIC_4 input/output pins. The relationship between register setting values and pin functions are as follows. * PC7 The PC7 pin functions as a bus control output pin. * PC6 When set for 16-bit bus width, the PC7 pin functions as a bus control output pin. When 8-bit bus width, the pin function is the same as that in single-chip mode. * PC5 to PC0 The pin functions are the same as those in single-chip mode. (b) Single-Chip Mode
* PC7, PC6 The pin function is switched as shown below according to the PCnDDR bit.
PCnDDR Pin function [Legend] n = 7, 6 0 PCn input pin 1 PCn output pin
* PC5/SDA4 The pin function is switched as shown below according to the combination of the ICE bit in ICCR of the IIC_4 and the PC5DDR bit.
ICE PC5DDR Pin function [Legend] X: Don't care. 0 PC5 input pin 0 1 PC5 output pin 1 X SDA4 input/output pin
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* PC4/SCL4 The pin function is switched as shown below according to the combination of the ICE bit in ICCR of the IIC_4 and the PC4DDR bit.
ICE PC4DDR Pin function [Legend] X: Don't care. 0 PC4 input pin 0 1 PC4 output pin 1 X SCL4 input/output pin
* PC3/SDA3 The pin function is switched as shown below according to the combination of the ICE bit in ICCR of the IIC_3 and the PC3DDR bit.
ICE PC3DDR Pin function [Legend] X: Don't care. 0 PC3 input pin 0 1 PC3 output pin 1 X SDA3 input/output pin
* PC2/SCL3 The pin function is switched as shown below according to the combination of the ICE bit in ICCR of the IIC_3 and the PC2DDR bit.
ICE PC2DDR Pin function [Legend] X: Don't care. 0 PC2 input pin 0 1 PC2 output pin 1 X SCL3 input/output pin
* PC1/SDA2 The pin function is switched as shown below according to the combination of the ICE bit in ICCR of the IIC_2 and the PC1DDR bit.
ICE PC1DDR Pin function [Legend] X: Don't care. 0 PC1 input pin 0 1 PC1 output pin 1 X SDA2 input/output pin
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* PC0/SCL2 The pin function is switched as shown below according to the combination of the ICE bit in ICCR of the IIC_2 and the PC0DDR bit.
ICE PC0DDR Pin function [Legend] X: Don't care. 0 PC0 input pin 0 1 PC0 output pin 1 X SCL2 input/output pin
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Section 8 I/O Ports
8.1.13
Port D
Port D is an 8-bit I/O port. Port D pins can also function as the IIC_5 input/output and LPC input/output pins. The output format of PD7 and PD6 pins is NMOS push-pull output. Port D has the following registers. * Port D data direction register (PDDDR) * Port D output data register (PDODR) * Port D input data register (PDPIN) (1) Port D Data Direction Register (PDDDR)
The individual bits of PDDDR specify input or output for the port D pins.
Bit 7 6 5 4 3 2 1 0 Bit Name PD7DDR PD6DDR PD5DDR PD4DDR PD3DDR PD2DDR PD1DDR PD0DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description If port D pins are specified for use as the general I/O port, the corresponding pins function as output port when the PDDDR bits are set to 1, and as input port when cleared to 0. Since this register is allocated to the same address as PDPIN, the states of the port D pins are returned when this register is read.
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(2)
Port D Output Data Register (PDODR)
PDODR stores output data for the port D pins.
Bit 7 6 5 4 3 2 1 0 Bit Name PD7ODR PD6ODR PD5ODR PD4ODR PD3ODR PD2ODR PD1ODR PD0ODR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description The PCODR register stores the output data for the pins that are used as the general output port.
(3)
Port D Input Data Register (PDPIN)
PDPIN indicates the pin states of port D.
Bit 7 6 5 4 3 2 1 0 Bit Name PD7PIN PD6 PIN PD5PIN PD4 PIN PD3 PIN PD2 PIN PD1 PIN PD0 PIN Initial Value Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* R/W R R R R R R R R Description When this register is read, the pin states are read. Since this register is allocated to the same address as PDDDR, writing to this register writes data to PDDDR and the port D setting is changed.
Note: The initial values are determined in accordance with the states of PD7 to PD0 pins.
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Section 8 I/O Ports
(4)
Pin Functions
Port D pins can also function as the LPC input/output and IIC_5 input/output pins. The relationship between register setting values and pin functions are as follows. The LPC is disabled when all of the bits LPC1E, LPC2E, and LPC3E in HICR0 and SCIFE in HICR5 are cleared to 0. * PD7/SDA5 The pin function is switched as shown below according to the combination of the ICE bit in ICCR of the IIC_5 and the PD7DDR bit.
ICE PD7DDR Pin function [Legend] X: Don't care. 0 PD7 input pin 0 1 PD7 output pin 1 X SDA5 input/output pin
* PD6/SCL5 The pin function is switched as shown below according to the combination of the ICE bit in ICCR of the IIC_5 and the PD6DDR bit.
ICE PD6DDR Pin function [Legend] X: Don't care. 0 PD6 input pin 0 1 PD6 output pin 1 X SCL5 input/output pin
* PD5/LPCPD The pin function is switched as shown below according to the PD5DDR bit. This pin can be used as the LPCPD input pin when the LPC is enabled.
LPC PD5DDR Pin function 0 PD5 input pin Disabled 1 PD5 output pin Enabled 0 LPCPD input pin
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* PD4/CLKRUN The pin function is switched as shown below according to the PD4DDR bit. This pin can be used as the CLKRUN input pin when the LPC is enabled.
LPC PD4DDR Pin function 0 PD4 input pin Disabled 1 PD4 output pin Enabled 0 CLKRUN input/output pin
* PD3/GA20 The pin function is switched as shown below according to the combination of the FGA20E bit in HICR0 of the LPC and the PD3DDR bit.
FGA20E PD3DDR Pin function 0 PD3 input pin 0 1 PD3 output pin 1 0 GA20 output pin
* PD2/PME The pin function is switched as shown below according to the combination of the PMEE bit in HICR0 of the LPC and the PD2DDR bit.
PMEE PD2DDR Pin function 0 PD2 input pin 0 1 PD2 output pin 1 0 PME output pin
* PD1/LSMI The pin function is switched as shown below according to the combination of the LSMIE bit in HICR0 of the LPC and the PD1DDR bit.
LSMIE PD1DDR Pin function 0 PD1 input pin 0 1 PD1 output pin 1 0 LSMI output pin
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* PD0/LSCI The pin function is switched as shown below according to the combination of the LSCIE bit in HICR0 of the LPC and the PD0DDR bit.
LSCIE PD0DDR Pin function 0 PD0 input pin 0 1 PD0 output pin 1 0 LSCI output pin
(5)
Input Pull-Up MOS
Port pins D5 to D0 have built-in input pull-up MOSs that can be controlled by software. This input pull-up MOS can be used in any operating mode, and can be specified as on or off on a bit-by-bit basis.
PDnDDR PDnODR PDn pull-up MOS [Legend] 1 ON n = 5 to 0, X: Don't care. 0 0 OFF 1 X OFF
The input pull-up MOS is in the off state after a reset and in hardware standby mode. The prior state is retained in software standby mode. Table 8.8 summarizes the input pull-up MOS states. Table 8.8
Reset Off
Port D Input Pull-Up MOS States
Hardware Standby Mode Off Software Standby Mode On/Off In Other Operations On/Off
[Legend] Off: Always off. On/Off: On when PDDDR = 0 and PDODR = 1; otherwise off.
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Section 8 I/O Ports
8.1.14
Port E
Port E is an 8-bit I/O port. Port E pins can also function as the LPC input/output pins. Port E has the following registers. * Port E data direction register (PEDDR) * Port E output data register (PEODR) * Port E input data register (PEPIN) (1) Port E Data Direction Register (PEDDR)
The individual bits of PEDDR specify input or output for the port E pins.
Bit 7 6 5 4 3 2 1 0 Bit Name PE7DDR PE6DDR PE5DDR PE4DDR PE3DDR PE2DDR PE1DDR PE0DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description When set to 1, the corresponding pins function as output port pins; when cleared to 0, function as input port pins. Since this register is allocated to the same address as PEPIN, states of the port E pins are returned when this register is read.
(2)
Port E Output Data Register (PEODR)
PEODR stores output data for the port E pins.
Bit 7 6 5 4 3 2 1 0 Bit Name PE7ODR PE6ODR PE5ODR PE4ODR PE3ODR PE2ODR PE1ODR PE0ODR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description The PEODR register stores the output data for the pins that are used as the general output port.
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Section 8 I/O Ports
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Port E Input Data Register (PEPIN)
PEPIN indicates the pin states of port E.
Bit 7 6 5 4 3 2 1 0 Bit Name PE7PIN PE6PIN PE5PIN PE4PIN PE3PIN PE2PIN PE1PIN PE0PIN Initial Value Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* R/W R R R R R R R R Description When this register is read, the pin states are read. Since this register is allocated to the same address as PEDDR, writing to this register writes data to PEDDR and the port E setting is changed.
Note: The initial value of these pins is determined in accordance with the state of pins PE7 to PE0.
(4)
Pin Functions
Port E pins can also function as LPC input/output pins. The pin function is switched according to whether the LPC module is enabled or disabled. The LPC is disabled when all of the bits LPC1E, LPC2E, and LPC3E in HICR0 and SCIFE in HICR5 are cleared to 0. * PE7/SERIRQ The pin function is switched as shown below according to whether the LPC is enabled or disabled and the PE7DDR bit.
LPC PE7DDR Pin function [Legend] X: Don't care. 0 PE7 input pin Disabled 1 PE7 output pin Enabled X SERIRQ input/output pin
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Section 8 I/O Ports
* PE6/LCLK The pin function is switched as shown below according to whether the LPC is enabled or disabled and the PE6DDR bit.
LPC PE6DDR Pin function [Legend] X: Don't care. 0 PE6 input pin Disabled 1 PE6 output pin Enabled X LCLK input pin
* PE5/LRESET The pin function is switched as shown below according to whether the LPC is enabled or disabled and the PE5DDR bit.
LPC PE5DDR Pin function [Legend] X: Don't care. 0 PE5 input pin Disabled 1 PE5 output pin Enabled X LRESET input pin
* PE4/LFRAME The pin function is switched as shown below according to whether the LPC is enabled or disabled and the PE4DDR bit.
LPC PE4DDR Pin function [Legend] X: Don't care. 0 PE4 input pin Disabled 1 PE4 output pin Enabled X LFRAME input pin
* PE3/LAD3 The pin function is switched as shown below according to whether the LPC is enabled or disabled and the PE3DDR bit.
LPC PE3DDR Pin function [Legend] X: Don't care. 0 PE3 input pin Disabled 1 PE3 output pin Enabled X LAD3 input/output pin
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* PE2/LAD2 The pin function is switched as shown below according to whether the LPC is enabled or disabled and the PE2DDR bit.
LPC PE2DDR Pin function [Legend] X: Don't care. 0 PE2 input pin Disabled 1 PE2 output pin Enabled X LAD2 input/output pin
* PE1/LAD1 The pin function is switched as shown below according to whether the LPC is enabled or disabled and the PE1DDR bit.
LPC PE1DDR Pin function [Legend] X: Don't care. 0 PE1 input pin Disabled 1 PE1 output pin Enabled X LAD1 input/output pin
* PE0/LAD0 The pin function is switched as shown below according to whether the LPC is enabled or disabled and the PE0DDR bit.
LPC PE0DDR Pin function [Legend] X: Don't care. 0 PE0 input pin Disabled 1 PE0 output pin Enabled X LAD0 input/output pin
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Section 8 I/O Ports
8.1.15
Port F
Port F is a 7-bit I/O port. Port F pins can also function as the PWMX output and EtherC control input/output pins. Port F has the following registers. * Port F data direction register (PFDDR) * Port F output data register (PFODR) * Port F input data register (PFPIN) (1) Port F Data Direction Register (PFDDR)
The individual bits of PFDDR specify input or output for the port F pins. PFDDR is initialized only by a system reset, and retains the value even if an internal reset signal of the WDT is generated.
Bit 7 6 5 4 3 2 1 0 Bit Name PF6DDR PF5DDR PF4DDR PF3DDR PF2DDR PF1DDR PF0DDR Initial Value 0 0 0 0 0 0 0 R/W W W W W W W W Description Reserved When set to 1, the corresponding pin functions as an output port pin; when cleared to 0, functions as an input port pin. Since this register is allocated to the same address as PFPIN, states of the port F pins are returned when this register is read.
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Section 8 I/O Ports
(2)
Port F Output Data Register (PFODR)
PFODR stores output data for the port F pins. PEODR is initialized only by a system reset, and retains the value even if an internal reset signal of the WDT is generated.
Bit 7 6 5 4 3 2 1 0 Bit Name PF6ODR PF5ODR PF4ODR PF3ODR PF2ODR PF1ODR PF0ODR Initial Value 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Description Reserved Undefined value is read from this bit. Stores the output data for the pin that is used as the general output port.
(3)
Port F Input Data Register (PFPIN)
PFPIN indicates the pin states of port F.
Bit 7 6 5 4 3 2 1 0 Bit Name PF6PIN PF5PIN PF4PIN PF3PIN PF2PIN PF1PIN PF0PIN Initial Value Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* R/W R R R R R R R Description Reserved Undefined value is read from this bit. When this register is read, the pin states are read. Since this register is allocated to the same address as PFDDR, writing to this register writes data to PFDDR and the port F setting is changed.
Note: The initial value of these pins is determined in accordance with the state of pins PF6 to PF0.
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Section 8 I/O Ports
(4)
Pin Functions
Port F is a 7-bit I/O port. Port F pins can also function as the PWM output and EtherC control input/output pins. The relationship between the register settings and the pin function is shown below. * PF6/ExPWX2/RS14 The pin function is switched as shown below according to the combination of the OEA bit in DACR and the PWMXS bit in PTCNT0 of PWMX_1 and the PF6DDR bit.
PF6DDR PWMXS OEA Pin function [Legend] 0 X X: Don't care. 0 1 0 0 X 1 1 0 X 1 1 ExPWX2 output pin
PF6 input pin
PF6 output pin
* PF5/RS13 The pin function is switched as shown below according to the PF5DDR bit.
PF5DDR Pin function 0 PF5 input pin 1 PF5 output pin
* PF4/RS12 The pin function is switched as shown below according to the PF4DDR bit.
PF4DDR Pin function 0 PF4 input pin 1 PF4 output pin
* PF3/ExPWX3/RS11 The pin function is switched as shown below according to the combination of the OEB bit in DACR and the PWMXS bit in PTCNT0 of PWMX_1 and the PF3DDR bit.
PF3DDR PWMXS OEA Pin function [Legend] 0 X X: Don't care. 0 1 0 0 X 1 1 0 X 1 1 ExPWX3 output pin
PF3 input pin
PF3 output pin
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Section 8 I/O Ports
* PF2/RS10 The pin function is switched as shown below according to the PF2DDR bit.
PF2DDR Pin function 0 PF2 input pin 1 PF2 output pin
* PF1/RS9/MDC, PF0/RS8/MDIO The pin function is switched as shown below according to the combination of the module stop state in the EtherC and E-DMAC and the PFnDDR bit.
EtherC, E-DMAC PFnDDR Pin function [Legend] 0 PFn input pin Ether of them is stopped 1 PFn output pin Both of them are stopped X MDC output pin/ MDIO input/output pin
X: Don't care. n = 1, 0
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Section 8 I/O Ports
8.2
I/O Ports for the H8S/2463 Group and the H8S/2462 Group
Table 8.9 is a summary of the port functions. The pins of each port also function as input/output pins of peripheral modules and interrupt input pins. Each input/output port includes a data direction register (DDR) that controls input/output and a data register (DR) that stores output data. DDR and DR are not provided for input-only ports. Pins of ports 1 to 4, 6, and A and pins D0 to D5 of port D have built-in input pull-up MOSs. For port A pins and D0 to D5 pins, the on/off status of the input pull-up MOS is controlled by their respective DDR and the output data register (ODR). Ports 1 to 4, and 6 have an input pull-up MOS control register (PCR), in addition to DDR and DR, to control the on/off status of the input pull-up MOSs. Port 3 pins and pins 47 to 44 and B3 to B0 have built-in de-bouncers (DBn) that eliminate noises in the input signals. Ports 4 and F are designed for retain state outputs (RSn), which retain the output values on the pins even if a reset is generated when the watchdog timer has overflowed. Ports 1 to 6, and 8 to E can drive a single TTL load and 30 pF capacitive load. All the I/O ports can drive a Darlington transistor in output mode. Port pins 80 to 83, C0 to C5, D6, and D7 are NMOS push-pull output.
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Section 8 I/O Ports
Table 8.9
Port Port 1
Port Functions
Single-Chip Mode (EXPE = 0) P17 P16 P15 P14 P13 P12 P11 P10 Extended Mode (EXPE = 1) P17/A7/AD7 P16/A6/AD6 P15/A5/AD5 P14/A4/AD4 P13/A3/AD3 P12/A2/AD2 P11/A1/AD1 P10/A0/AD0 Same as left Feature of I/O Built-in input pull-up MOS
Description General I/O port multiplexed with address output and address-data multiplex I/O
Port 2
General I/O port P27/DTR multiplexed with SCIF P26/DSR control I/O P25/RI P24/DCD General I/O port multiplexed with address output and address-data multiplex I/O P23 P22 P21 P20 P37/ExDB7 P36/ExDB6 P35/ExDB5 P34/ExDB4 P33/ExDB3 P32/ExDB2 P31/ExDB1 P30/ExDB0 P47/IRQ7/RS7/DB7/HC7 P46/IRQ6/RS6/DB6/HC6 P45/IRQ5/RS5/DB5/HC5 P44/IRQ4/RS4/DB4/HC4
Built-in input pull-up MOS
P23/A11/AD11 P22/A10/AD10 P21/A9/AD9 P20/A8/AD8 P37/ExDB7/D15 P36/ExDB6/D14 P35/ExDB5/D13 P34/ExDB4/D12 P33/ExDB3/D11 P32/ExDB2/D10 P31/ExDB1/D9 P30/ExDB0/D8 P47/A15/AD15 P46/A14/AD14 P45/A13/AD13 P44/A12/AD12 Built-in input pull-up MOS
Port 3
General I/O port multiplexed with debounced input and bidirectional data bus I/O
Port 4
General I/O port multiplexed with interrupt input, debounced input, address output, and address-data multiplex I/O General I/O port multiplexed with interrupt input and bidirectional data bus* I/O
Built-in input pull-up MOS LED driving capability (sink current 12 mA)
P43/IRQ3/RS3/HC3 P42/IRQ2/RS2/HC2 P41/IRQ1/RS1/HC1 P40/IRQ0/RS0/HC0
P43/IRQ3/RS3/HC3/D7* P42/IRQ2/RS2/HC2/D6* P41/IRQ1/RS1/HC1/D5* P40/IRQ0/RS0/HC0/D4*
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Section 8 I/O Ports
Port Port 5
Description General I/O port multiplexed with interrupt input, bus control output, system clock output, external subclock input, and SSU I/O General I/O port multiplexed with interrupt input, SCIF and SCI_1 I/O
Single-Chip Mode (EXPE = 0) P57 P56/EXCL/ P55/IRQ13/SSI P54/IRQ12/SSO
Extended Mode (EXPE = 1) WR/HWR Same as left
Feature of I/O
P53/IRQ11/RxD1 P52/IRQ10/TxD1 P51/IRQ9/RxDF P50/IRQ8/TxDF P67/ExIRQ8/SSCK P66/ExIRQ9/SCS P65/ExIRQ10/RTS P64/ExIRQ11/CTS P63/PWX3 P62/PWX2 P61/IRQ15/PWX1 P60/IRQ14/PWX0
Same as left
Port 6
General I/O port multiplexed with interrupt input, SCIF control I/O, and SSU control I/O General I/O port multiplexed with interrupt input, PWMX output, and bidirectional data bus* I/O
Same as left
Built-in input pull-up MOS
P63/PWX3/D3* P62/PWX2/D2* P61/IRQ15/PWX1/D1* P60/IRQ14/PWX0/D0*
Port 7
General input port P77/AN7 multiplexed with A/D P76/AN6 converter analog input P75/AN5 P74/AN4 P73/AN3 P72/AN2 P71/AN1 P70/AN0 General I/O port multiplexed with interrupt input, A/D converter external trigger input, and SCI_1 and SCI_3 I/O
P87/ExIRQ15/TxD3/ADTRG P86/ExIRQ14/RxD3 P85/ExIRQ13/SCK1 P84/ExIRQ12/SCK3
Same as left
Port 8
Same as left
General I/O port P83/SDA1 multiplexed with IIC_0 P82/SCL1 and IIC_1 I/O P81/SDA0 P80/SCL0
Same as left
NMOS push-pull output
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Section 8 I/O Ports
Port Port 9
Description General I/O port multiplexed with PWMX output and bus control I/O
Single-Chip Mode (EXPE = 0) P97 P96 P95 P94/ExPWX1 P93/ExPWX0 P92 P91 P90
Extended Mode (EXPE = 1) P97/WAIT/CS256 Same as left AS/IOS Same as left P92/HBE P91/AH P90/LBE
PA7/ExIRQ7/EVENT7/A23 PA6/ExIRQ6/EVENT6/LNKSTA/A22 PA5/ExIRQ5/EVENT5/WOL/A21 PA4/ExIRQ4/EVENT4/A20 PA3/ExIRQ3/EVENT3/A19 PA2/ExIRQ2/EVENT2/A18 PA1/ExIRQ1/EVENT1/A17 PA0/ExIRQ0/EVENT0/A16
Feature of I/O
Port A
General I/O port multiplexed with interrupt input, DTC event counter input, EtherC control I/O, and address output
PA7/ExIRQ7/EVENT7 PA6/ExIRQ6/EVENT6/LNKSTA PA5/ExIRQ5/EVENT5/WOL PA4/ExIRQ4/EVENT4 PA3/ExIRQ3/EVENT3 PA2/ExIRQ2/EVENT2 PA1/ExIRQ1/EVENT1 PA0/ExIRQ0/EVENT0
Built-in input pull-up MOS
Port B
General I/O port multiplexed with DTC event counter input and EtherC control I/O General I/O port multiplexed with debounced input, DTC event counter input, and EtherC control I/O
PB7/EVENT15/RM_RX-ER Same as left PB6/EVENT14/RM_CRS-DV PB5/EVENT13/RM_REF-CLK PB4/EVENT12/RM_TX-EN
PB3/DB3/EVENT11/RM_RXD1 PB2/DB2/EVENT10/RM_RXD0 PB1/DB1/EVENT9/RM_TXD1 PB0/DB0/EVENT8/RM_TXD0
Same as left
Port C
General I/O port multiplexed with bus control output
PC7 PC6
RD PC6/LWR Same as left NMOS push-pull output
PC5/SDA4 General I/O port multiplexed with IIC_2 PC4/SCL4 PC3/SDA3 to IIC_4 I/O PC2/SCL3 PC1/SDA2 PC0/SCL2
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Section 8 I/O Ports
Port Port D
Description
Single-Chip Mode (EXPE = 0)
Extended Mode (EXPE = 1) Same as left
Feature of I/O NMOS push-pull output Built-in input pull-up MOS
General I/O port PD7/SDA5 multiplexed with IIC_5 PD6/SCL5 I/O PD5/LPCPD General I/O port multiplexed with LPC PD4/CLKRUN PD3/GA20 I/O PD2/PME PD1/LSMI PD0/LSCI
Same as left
Port E
General I/O port PE7/SERIRQ multiplexed with LPC PE6/LCLK I/O PE5/LRESET PE4/LFRAME PE3/LAD3 PE2/LAD2 PE1/LAD1 PE0/LAD0 General I/O port multiplexed with PWMX output and EtherC control I/O * PF6/ExPWX2/RS14 PF1/RS9/MDC PF0/RS8/MDIO
Same as left
Port F
Same as left
Note:
Available when configured for 16-bit data bus.
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Section 8 I/O Ports
8.2.1
Port 1
Port 1 is an 8-bit I/O port. Port 1 pins can also function as the address bus and address-data multiplex bus pins. The pin functions change according to the operating mode. Port 1 has the following registers. * Port 1 data direction register (P1DDR) * Port 1 data register (P1DR) * Port 1 pull-up MOS control register (P1PCR) (1) Port 1 Data Direction Register (P1DDR)
The individual bits of P1DDR specify input or output for the pins of port 1.
Bit 7 6 5 4 3 2 1 0 Bit Name P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W * * Description * Normal extended mode (ADMXE = 0) When set to 1, the corresponding pins function as address output pins; when cleared to 0, function as input port pins. Address-data multiplex extended mode (ADMXE = 1) These bits correspond to the AD7 to AD0 pins of the address-data multiplex bus. Single-chip mode When set to 1, the corresponding pins function as output port pins; when cleared to 0, function as input port pins.
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Section 8 I/O Ports
(2)
Port 1 Data Register (P1DR)
P1DR stores output data for the port 1 pins.
Bit 7 6 5 4 3 2 1 0 Bit Name P17DR P16DR P15DR P14DR P13DR P12DR P11DR P10DR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description P1DR stores output data for the port 1 pins that are used as the general output port. If this register is read, the P1DR values are read for the bits with the corresponding P1DDR bits set to 1. For the bits with the corresponding P1DDR bits cleared to 0, the pin states are read.
(3)
Port 1 Pull-Up MOS Control Register (P1PCR)
P1PCR controls the port 1 built-in input pull-up MOSs.
Bit 7 6 5 4 3 2 1 0 Bit Name P17PCR P16PCR P15PCR P14PCR P13PCR P12PCR P11PCR P10PCR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description When the pins are in the input state, the corresponding input pull-up MOS is turned on when a P1PCR bit is set to 1. Do not change the initial value when using the address-data multiplex extended bus mode.
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(4)
Pin Functions
The relationship between the register settings and the pin function is shown below. (a) Extended Mode (EXPE = 1)
The pin function is switched as shown below according to the P1nDDR bit.
P1nDDR ADMXE ABW, ABW256 Pin function 0 X Either bit is 0 (8/16-bit bus) ADn input/output pin 0 1 Both bits are 1 (8-bit bus) P1n input pin 0 X 1 1 Either bit is 0 (8/16-bit bus) Setting prohibited Both bits are 1 (8-bit bus) P1n output pin
P1n input pin
An output pin
[Legend] n = 7 to 0, X: Don't care.
(b)
Single-Chip Mode (EXPE = 0)
The pin function is switched as shown below according to the P1nDDR bit.
P1nDDR Pin function [Legend] n = 7 to 0 0 P1n input pin 1 P1n output pin
(5)
Port 1 Input Pull-Up MOS
Port 1 has built-in input pull-up MOSs that can be controlled by software. The input pull-up MOS can be used regardless of the operating mode. Table 8.10 summarizes the input pull-up MOS states. Table 8.10 Port 1 Input Pull-Up MOS States
Reset Off Hardware Standby Software Standby Mode Mode Off On/Off In Other Operations On/Off
[Legend] Off: Always off. On/Off: On when P1DDR = 0 and P1PCR = 1; otherwise off.
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Section 8 I/O Ports
8.2.2
Port 2
Port 2 is an 8-bit I/O port. Port 2 pins can also function as the SCIF modem control signal, address bus, and address-data multiplex bus pins. The pin functions change according to the operating mode. Port 2 has the following registers. * Port 2 data direction register (P2DDR) * Port 2 data register (P2DR) * Port 2 pull-up MOS control register (P2PCR) (1) Port 2 Data Direction Register (P2DDR)
The individual bits of P2DDR specify input or output for the pins of port 2.
Bit 7 6 5 4 3 2 1 0 Bit Name P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W * Normal extended mode (ADMXE = 0) When set to 1, the corresponding pins function as address output pins; when cleared to 0, function as input port pins. The address output pins used are in accord with the settings of the IOSE and CS256E bits of SYSCR. * Address-data multiplex extended mode (ADMXE = 1) These bits correspond to the AD11 to AD8 pins of the address-data multiplex bus. * Single-chip mode When set to 1, the corresponding pins function as output port pins; when cleared to 0, function as input port pins. Description When set to 1, the corresponding pins function as output port pins; when cleared to 0, function as input port pins.
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Section 8 I/O Ports
(2)
Port 2 Data Register (P2DR)
P2DR stores output data for the port 2 pins.
Bit 7 6 5 4 3 2 1 0 Bit Name P27DR P26DR P25DR P24DR P23DR P22DR P21DR P20DR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description P2DR stores output data for the port 2 pins that are used as the general output port. If this register is read, the P2DR values are read for the bits with the corresponding P2DDR bits set to 1. For the bits with the corresponding P2DDR bits cleared to 0, the pin states are read.
(3)
Port 2 Pull-Up MOS Control Register (P2PCR)
P2PCR controls the port 2 built-in input pull-up MOSs.
Bit 7 6 5 4 3 2 1 0 Bit Name P27PCR P26PCR P25PCR P24PCR P23PCR P22PCR P21PCR P20PCR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W When the pins are in the input state, the corresponding input pull-up MOS is turned on when a P2PCR bit is set to 1. Do not change the initial value when using the address-data multiplex extended bus mode. Description When the pins are in the input state, the corresponding input pull-up MOS is turned on when a P2PCR bit is set to 1.
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Section 8 I/O Ports
(4)
Pin Functions
The relationship between the register settings and the pin function is shown below. (a) Extended Mode (EXPE = 1)
* P27 to P24 The pin function is the same as that in single-chip mode. * P23 The pin function is switched as shown below according to the combination of the CS256E and IOSE bits in SYSCR, the ADFULLE bit in BCR2 of the BSC, and the P23DDR bit. Address 11 in the table below is expressed by the following logical expression. Address 11 = 1: ADFULLE * CS256E * IOSE
P23DDR ADMXE Address 11 Pin function 0 X 0 1 X 0 0 1 1 1 X
P23 input pin AD11 input/output A11 output pin P23 output pin AD11 input/output pin pin
* P22 to P20
P2nDDR ADMXE Pin function [Legend] 0 P2n input pin 0 1 ADm input/output pin 0 Am output pin 1 1 ADm input/output pin
m = 10 to 8, n = 2 to 0, X: Don't care.
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Section 8 I/O Ports
(b)
Single-Chip Mode (EXPE = 0)
* P27/DTR The pin function is switched as shown below according to the combination of the SCIFE bit in HICR5 of the LPC, the SCIFOE1 and SCIFOE0 bits in SCIFCR of the SCIF, and the P27DDR bit.
SCIFE SCIFOE1, SCIFOE0 P27DDR Pin function [Legend] 0 Other than 10 0 P27 input pin 1 P27 output pin 10 X 0 X1 1 P27 output pin 1 X0 X DTR output pin
DTR output P27 input pin pin
X: Don't care.
* P26/DSR, P25/RI, P24/DCD The pin function is switched as shown below according to the P2nDDR bit.
P2nDDR Pin function [Legend] n = 6 to 4 0 P2n input pin DSR/RI/DCD input pin 1 P2n output pin
* P23 to P20 The pin function is switched as shown below according to the P2nDDR bit.
P2nDDR Pin function [Legend] n = 3 to 0 0 P2n input pin 1 P2n output pin
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Section 8 I/O Ports
(5)
Port 2 Input Pull-Up MOS
Port 2 has built-in input pull-up MOSs that can be controlled by software. The input pull-up MOS can be used regardless of the operating mode. Table 8.11 summarizes the input pull-up MOS states. Table 8.11
Reset Off
Port 2 Input Pull-Up MOS States
Hardware Standby Software Standby Mode Mode In Other Operations Off On/Off On/Off
[Legend] Off: Always off. On/Off: On when P2DDR = 0 and P2PCR = 1; otherwise off.
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Section 8 I/O Ports
8.2.3
Port 3
Port 3 is an 8-bit I/O port. Port 3 pins can also function as the bidirectional data bus and debounced input pins. The pin functions change according to the operating mode. Port 3 has the following registers. * Port 3 data direction register (P3DDR) * Port 3 data register (P3DR) * Port 3 pull-up MOS control register (P3PCR) * Noise canceler enable register (P3NCE) * Noise canceler mode control register (P3NCMC) * Noise cancel cycle setting register (NCCS) (1) Port 3 Data Direction Register (P3DDR)
The individual bits of P3DDR specify input or output for the port 3 pins.
Bit 7 6 5 4 3 2 1 0 Bit Name P37DDR P36DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR Initial Value 0 0 0 0 0 0 0 0 R/W Description W W W W W W W W * * Normal extended mode (ADMXE = 0) The pins function as bidirectional data bus pins. Other modes When set to 1, the corresponding pins function as output port pins; when cleared to 0, function as input port pins.
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Port 3 Data Register (P3DR)
P3DR stores output data for the port 3 pins.
Bit 7 6 5 4 3 2 1 0 Bit Name P37DR P36DR P35DR P34DR P33DR P32DR P31DR P30DR Initial Value 0 0 0 0 0 0 0 0 R/W Description R/W * R/W R/W R/W R/W R/W R/W * R/W Normal extended mode (ADMXE = 0) Since the port 3 pins function as bidirectional data bus pins, the value of this register has no effect on operation. If this register is read, the P3DR values are read for the bits with the corresponding P3DDR bits set to 1. For the bits with the corresponding P3DDR bits cleared to 0, 1 is read. Other modes P3DR stores output data for the port 3 pins that are used as the general output port. If this register is read, the P3DR values are read for the bits with the corresponding P3DDR bits set to 1. For the bits with the corresponding P3DDR bits cleared to 0, the pin states are read.
(3)
Port 3 Pull-Up MOS Control Register (P3PCR)
P3PCR controls the port 3 built-in input pull-up MOSs.
Bit 7 6 5 4 3 2 1 0 Bit Name P37PCR P36PCR P35PCR P34PCR P33PCR P32PCR P31PCR P30PCR Initial Value 0 0 0 0 0 0 0 0 R/W Description R/W * R/W R/W * R/W R/W R/W R/W R/W Normal extended mode (ADMXE = 0) This register has no effect on operation. Other modes When the pins are in the input state, the corresponding input pull-up MOS is turned on when a P3PCR bit is set to 1.
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Noise Canceler Enable Register (P3NCE)
P3NCE enables or disables the noise canceler circuit at port 3.
Bit 7 6 5 4 3 2 1 0 Bit Name P37NCE P36NCE P35NCE P34NCE P33NCE P32NCE P31NCE P30NCE Initial Value 0 0 0 0 0 0 0 0 R/W Description R/W * R/W R/W R/W R/W R/W R/W R/W * Normal extended mode (ADMXE = 0) The pins function as bidirectional data bus pins. Set this register to 0. Other modes Enables the noise canceler circuit for the corresponding pin and the pin state is fetched into P3DR at the sampling cycle set by NCCS. The operation changes according to the other control bits. See section 8.2.3 (7), Pin Functions, for details.
(5)
Noise Canceler Mode Control Register (P3NCMC)
When the noise canceler is enabled, P3NCMC controls whether 1 or 0 is expected for the input signal to port 3 in bit units.
Bit 7 6 5 4 3 2 1 0 Bit Name P37NCMC P36NCMC P35NCMC P34NCMC P33NCMC P32NCMC P31NCMC P30NCMC Initial Value 1 1 1 1 1 1 1 1 R/W Description R/W * R/W R/W * R/W R/W R/W R/W R/W Normal extended mode (ADMXE = 0) This register has no effect on operation. Other modes 1 expected: 1 is stored in the port data register while 1 is input stably. 0 expected: 0 is stored in the port data register while 0 is input stably.
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Noise Canceler Cycle Setting Register (NCCS)
NCCS controls the sampling cycle of the noise cancelers.
Bit Bit Name Initial Value R/W Undefined 0 0 0 R/W Description Reserved Undefined value is read from these bits. 2 1 0 NCCK2 NCCK1 NCCK0 R/W These bits set the sampling cycle of the noise cancelers. R/W * R/W When = 34 MHz 000: 0.06 s 001: 0.94 s 010: 15.1 s /2 /32 /512 100: 963.8 s /32768 101: 1.9 ms 110: 3.9 ms 111: 7.7 ms /65536 /131072 /262144
7 to 3
011: 240.9 s /8192
/2, /32, /512, /8192, /32768, /65536, /131072, /262144 Sampling clock selection t
Pin input
Latch
Latch
Latch
Match detection circuit
Port data register
t
Sampling clock
Figure 8.7 Noise Canceler Circuit
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P3n input
1 expected P3nDR
0 expected P3nDR
(n = 7 to 0)
Figure 8.8 Noise Canceler Operation (7) (a) Pin Functions Normal Extended Mode
Port 3 pins are automatically set to function as bidirectional data bus pins. (b) Address-Data Multiplex Extended Mode
The operation is the same as that in single-chip mode. (c) Single-Chip Mode
The pin function is switched as shown below according to the P3nDDR bit and the P3nNCE bit.
P3nDDR P3nNCE Pin function 0 P3n input pin 0 1 DBn input 1 X P3n output pin
[Legend] n = 7 to 0, X: Don't care
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Port 3 Input Pull-Up MOS
Port 3 has built-in input pull-up MOSs that can be controlled by software. The input pull-up MOS can be used in single-chip mode and address-data multiplex extended mode. Table 8.12 summarizes the input pull-up MOS states. Table 8.12 Port 3 Input Pull-Up MOS States
Mode Normal extended mode (EXPE = 1, ADMXE = 0) Address-data multiplex extended mode (EXPE = 1, ADMXE = 1) [Legend] Off: Always off. On/Off: On when input state and P3PCR = 1; otherwise off. Reset Off Hardware Standby Mode Off Off Software Standby In Other Mode Operations Off On/Off Off On/Off
Single-chip mode (EXPE = 0) Off
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8.2.4
Port 4
Port 4 is an 8-bit I/O port. Port 4 pins can also function as the external interrupt input, de-bounced input, bidirectional data bus, address bus, and address-data multiplex bus pins. Port 4 has the following registers. * Port 4 data direction register (P4DDR) * Port 4 data register (P4DR) * Port 4 pull-up MOS control register (P4PCR) * Noise canceler enable register (P4BNCE) * Noise canceler mode control register (P4BNCMC) * Noise cancel cycle setting register (NCCS) (1) Port 4 Data Direction Register (P4DDR)
The individual bits of P4DDR specify input or output for the port 4 pins. P4DDR is initialized only by a system reset, and retains the value even if an internal reset signal of the WDT is generated.
Bit 7 6 5 4 Bit Name P47DDR P46DDR P45DDR P44DDR Initial Value 0 0 0 0 R/W Description W W W W * * Normal extended mode (ADMXE = 0) When set to 1, the corresponding pins function as address output pins; when cleared to 0, function as input port pins. The address output pins used are in accord with the settings of the IOSE and CS256E bits of SYSCR. Address-data multiplex extended mode (ADMXE = 1) These bits correspond to the AD15 to AD12 pins of the address-data multiplex bus. * Single-chip mode When set to 1, the corresponding pins function as output port pins; when cleared to 0, function as input port pins.
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Bit 3 2 1 0
Bit Name P43DDR P42DDR P41DDR P40DDR
Initial Value 0 0 0 0
R/W Description W W W W * * Normal extended mode (16-bit bus) These bits have no effect on operation. Other modes If port 4 pins are specified for use as the general I/O port, the corresponding pins function as output port when the P4DDR bits are set to 1, and as input port when cleared to 0.
(2)
Port 4 Data Register (P4DR)
P4DR stores output data for the port 4 pins. P4DR is initialized only by a system reset, and retains the value even if an internal reset signal of the WDT is generated.
Bit 7 6 5 4 3 2 1 0 Bit Name P47DR P46DR P45DR P44DR P43DR P42DR P41DR P40DR Initial Value 0 0 0 0 0 0 0 0 R/W Description R/W These bits store output data for the port 4 pins that are used as the general output port. R/W If this register is read, the P4DR values are read for the R/W bits with the corresponding P4DDR bits set to 1. For the R/W bits with the corresponding P4DDR bits cleared to 0, the pin states are read. R/W * R/W R/W R/W Normal extended mode (16-bit data bus) Since the corresponding pins function as bidirectional data bus pins, the value in these bits has no effect on operation. If this register is read, the P4DR values are read for the bits with the corresponding P4DDR bits set to 1. For the bits with the corresponding P4DDR bits cleared to 0, 1 is read. * Other modes These bits store output data for the port 4 pins that are used as the general output port. If this register is read, the P4DR values are read for the bits with the corresponding P4DDR bits set to 1. For the bits with the corresponding P4DDR bits cleared to 0, the pin states are read.
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Port 4 Pull-Up MOS Control Register (P4PCR)
P4PCR controls the port 4 built-in input pull-up MOSs.
Bit 7 6 5 4 3 2 1 0 Bit Name P47PCR P46PCR P45PCR P44PCR P43PCR P42PCR P41PCR P40PCR Initial Value 0 0 0 0 0 0 0 0 R/W Description R/W * R/W R/W * R/W R/W R/W R/W R/W Normal extended mode (ADMXE = 0) This register has no effect on operation. Other modes When the pins are in the input state, the corresponding input pull-up MOS is turned on when a P4PCR bit is set to 1.
(4)
Noise Canceler Enable Register (P4BNCE)
The individual bits of P4BNCE enable or disable the noise canceler circuits for ports 4 and B.
Bit 7 6 5 4 Bit Name P47NCE P46NCE P45NCE P44NCE Initial Value 0 0 0 0 R/W Description R/W Enables the noise canceler circuit for the corresponding pin and the pin state is fetched into P4DR at the R/W sampling cycle set by NCCS. R/W The operation changes according to the other control R/W bits. See section 8.2.4 (7), Pin Functions, for details. R/W Bits for port B setting
3 to 0 PB3NCE to All 0 PB0NCE
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Noise Canceler Mode Control Register (P4BNCMC)
P4BNCMC controls whether 1 or 0 is expected for the input signal to port 4 in bit units.
Bit 7 6 5 4 Bit Name P47NCMC P46NCMC P45NCMC P44NCMC Initial Value 1 1 1 1 All 1 R/W Description R/W Expected value setting R/W 1 expected: 1 is stored in the port data register while 1 is input stably R/W 0 expected: 0 is stored in the port data register while 0 R/W is input stably R/W Bits for port B setting
3 to 0 PB3NCMC to PB0NCMC
(6)
Noise Canceler Cycle Setting Register (NCCS)
NCCS controls the sampling cycle of the noise cancelers.
Bit Bit Name Initial Value Undefined 0 0 0 R/W Description R/W Reserved Undefined value is read from these bits. 2 1 0 NCCK2 NCCK1 NCCK0 R/W These bits set the sampling cycle of the noise R/W cancelers. R/W * When = 34 MHz 000: 0.06 s 001: 0.94 s 010: 15.1 s /2 /32 /512 100: 963.8 s /32768 101: 1.9 ms 110: 3.9 ms 111: 7.7 ms /65536 /131072 /262144
7 to 3
011: 240.9 s /8192
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/2, /32, /512, /8192, /32768, /65536, /131072, /262144 Sampling clock selection t
Pin input
Latch
Latch
Latch
Match detection circuit
Port data register
Sampling clock
Figure 8.9 Noise Canceler Circuit
P4n input
1 expected P4nDR
0 expected P4nDR (n = 7 to 4)
Figure 8.10 Noise Canceler Operation
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Pin Functions
The relationship between the register settings and the pin function is shown below. (a) Normal Extended Mode
* P47 to P44 The pin function is switched as shown below according to the combination of the CS256E and IOSE bits in SYSCR, the ADFULLE bit in BCR2 of the BSC, and the P4nDDR bit. Address 13 in the table below is expressed by the following logical expression. Address 13 = 1: ADFULLE * CS256E * IOSE
P4nDDR Address 13 Pin function 0 X P4n input pin 0 Am output pin 1 1 P4n output pin
[Legend] n = 15 to 12, n = 7 to 4, X: Don't care
* P43 to P40 Port pins 43 to 40 function as bidirectional data bus pins in 16-bit bus extension, and can be used as general I/O port pins in 8-bit bus extension. (b) Address-Data Multiplex Extended Mode
Port pins 47 to 44 are automatically set to function as address bus pins. Port pins 43 to 40 can be used as general I/O port pins.
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(c)
Single-Chip Mode
The relationship between register setting values and pin functions are as follows. * P47 to P40 The pin function is switched as shown below according to the P4nDDR bit and P4nNCE bit. When the ISSn bit in ISSR is cleared to 0 and the IRQnE bit in IER of the interrupt controller is set to 1, the pin can be used as the IRQn input pin. To use as the IRQn input pin, clear the P4nDDR bit to 0.
P4nDDR P4nNCE Pin function 0 P4n input IRQn input [Legend] n = 7 to 4, X: Don't care 0 1 DBn input IRQn input (with the noise canceler) 1 X P4n output pin
* P44 to P40 The pin function is switched as shown below according to the P4nDDR bit. When the ISSn bit in ISSR is cleared to 0 and the IRQnE bit in IER of the interrupt controller is set to 1, the pin can be used as the IRQn input pin. To use as the IRQn input pin, clear the P4nDDR bit to 0.
P4nDDR Pin function 0 P4n input pin IRQn input pin [Legend] n = 3 to 0, X: Don't care 1 P4n output pin
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Port 4 Input Pull-Up MOS
Port 4 has built-in input pull-up MOSs that can be controlled by software. The input pull-up MOS can be used in single-chip mode and address-data multiplex extended mode. Table 8.13 summarizes the input pull-up MOS states. Table 8.13 Port 4 Input Pull-Up MOS States
Mode Normal extended mode (EXPE = 1, ADMXE = 0) Address-data multiplex extended mode (EXPE = 1, ADMXE = 1) [Legend] Off: Always off. On/Off: On when input state and P4PCR = 1; otherwise off. Reset Off Hardware Standby Mode Off Off Software Standby In Other Mode Operations Off On/Off Off On/Off
Single-chip mode (EXPE = 0) Off
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8.2.5
Port 5
Port 5 is an 8-bit I/O port. Port 5 pins can also function as the SCIF, SCI_1, and SSU input/output, bus control output, system clock output, external subclock input, and interrupt input pins. Port 5 has the following registers. * Port 5 data direction register (P5DDR) * Port 5 data register (P5DR) (1) Port 5 Data Direction Register (P5DDR)
The individual bits of P5DDR specify input or output for the port 5 pins.
Bit 7 Bit Name P57DDR Initial Value 0 R/W W Description If port 5 pins are specified for use as the general I/O port, the corresponding pins function as output port when the P5DDR bits are set to 1, and as input port when cleared to 0. The corresponding port 5 pin functions as the system clock output pin () when this bit is set to 1, and as the general I/O port when cleared to 0. If port 5 pins are specified for use as the general I/O port, the corresponding pins function as output port when the P5DDR bits are set to 1, and as input port when cleared to 0.
6
P56DDR
0
W
5 4 3 2 1 0
P55DDR P54DDR P53DDR P52DDR P51DDR P50DDR
0 0 0 0 0 0
W W W W W W
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Port 5 Data Register (P5DR)
P5DR stores output data for the port 5 pins.
Bit 7 6 5 4 3 2 1 0 Note: Bit Name P57DR P56DR P55DR P54DR P53DR P52DR P51DR P50DR * Initial Value 0 Undefined* 0 0 0 0 0 0 R/W R/W R R/W R/W R/W R/W R/W R/W Description P5DR stores output data for the port 5 pins that are used as the general output port. If this register is read, the P5DR values are read for the bits with the corresponding P5DDR bits set to 1. For the bits with the corresponding P5DDR bits cleared to 0, the pin states are read.
The initial value is determined in accordance with the pin state of P56.
(3) (a)
Pin Functions Normal Extended Mode and Address-Data Multiplex Extended Mode
Port pin 57 is automatically set to function as a bus control output pin. The functions of port pins 56 to 50 are the same as those in single-chip mode. (b) Single-Chip Mode
Port 5 pins can operate as the SCIF, SCI_1, and SSU input/output, noise canceler input, or general I/O port pins. The relationship between register setting values and pin functions are as follows. * P57 The pin function is switched as shown below according to the P57DDR bit.
P57DDR Pin function 0 P57 input pin 1 P57 output pin
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* P56/EXCL/ The pin function is switched as shown below according to the combination of the EXCLE bit in LPWRCR and the P56DDR bit.
P56DDR EXCLE Pin function [Legend] X: Don't care. 0 P56 input pin 0 1 EXCL input pin 1 X output pin
* P55/IRQ13/SSI The pin function is switched as shown below according to the RE bit in SSER of the SSU and the P55DDR bit. When the ISS13 bit in ISSR16 is cleared to 0 and the IRQ13E bit in IER16 of the interrupt controller is set to 1, this pin can be used as the IRQ13 input pin. To use as the IRQ13 input pin, clear the P55DDR bit to 0.
RE P55DDR Pin function 0 P55 input pin IRQ13 input pin [Legend] X: Don't care. 0 1 P55 output pin 1 X SSI input pin
* P54/IRQ12/SSO The pin function is switched as shown below according to the TE bit in SSER of the SSU and the P54DDR bit. When the ISS12 bit in ISSR16 is cleared to 0 and the IRQ12E bit in IER16 of the interrupt controller is set to 1, this pin can be used as the IRQ12 input pin. To use as the IRQ12 input pin, clear the P54DDR bit to 0.
TE P54DDR Pin function 0 P54 input pin IRQ12 input pin [Legend] X: Don't care. 0 1 P54 output pin 1 X SSO output pin
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* P53/IRQ11/RxD1 The pin function is switched as shown below according to the combination of the RE bit in SCR of SCI_1 and the P53DDR bit. When the ISS11 bit in ISSR16 is cleared to 0 and the IRQ11E bit in IER16 of the interrupt controller is set to 1, this pin can be used as the IRQ11 input pin. To use as the IRQ11 input pin, clear the P53DDR bit to 0.
RE P53DDR Pin function 0 P53 input pin IRQ11 input pin [Legend] X: Don't care. 0 1 P53 output pin 1 X RxD1 input pin
* P52/IRQ10/TxD1 The pin function is switched as shown below according to the combination of the TE bit in SCR of SCI_1 and the P52DDR bit. When the ISS10 bit in ISSR16 is cleared to 0 and the IRQ10E bit in IER16 of the interrupt controller is set to 1, this pin can be used as the IRQ10 input pin. To use as the IRQ10 input pin, clear the P52DDR bit to 0.
TE P52DDR Pin function 0 P52 input pin IRQ10 input pin [Legend] X: Don't care. 0 1 P52 output pin 1 X TxD1 output pin
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* P51/IRQ9/RxDF The pin function is switched as shown below according to the combination of the enable/disable setting of the SCIF and the P51DDR bit. When the ISS9 bit in ISSR16 is cleared to 0 and the IRQ9E bit in IER16 of the interrupt controller is set to 1, this pin can be used as the IRQ9 input pin. To use as the IRQ9 input pin, clear the P51DDR bit to 0.
SCIF P51DDR Pin function 0 P51 input pin IRQ9 input pin [Legend] X: Don't care. Disabled 1 P51 output pin Enabled X RxDF input pin
* P50/IRQ8/TxDF The pin function is switched as shown below according to the combination of the enable/disable setting of the SCIF and the P50DDR bit. When the ISS8 bit in ISSR16 is cleared to 0 and the IRQ8E bit in IER16 of the interrupt controller is set to 1, this pin can be used as the IRQ8 input pin. To use as the IRQ8 input pin, clear the P50DDR bit to 0.
SCIF P50DDR Pin function 0 P50 input pin IRQ8 input pin [Legend] X: Don't care. Disabled 1 P50 output pin Enabled X TxDF output pin
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8.2.6
Port 6
Port 6 is an 8-bit I/O port. Port 6 pins can also function as the bidirectional data bus, PWMX output, SCIF and SSU control input/output, and interrupt input pins. The pin functions change according to the operating mode. In addition, port 6 pins can also be used as the extended data bus pins (D0 to D0). Port 6 has the following registers. * Port 6 data direction register (P6DDR) * Port 6 data register (P6DR) * Port 6 pull-up MOS control register (P6PCR) (1) Port 6 Data Direction Register (P6DDR)
The individual bits of P6DDR specify input or output for the pins of port 6.
Bit 7 6 5 4 3 2 1 0 Bit Name P67DDR P66DDR P65DDR P64DDR P63DDR P62DDR P61DDR P60DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W * * Normal extended mode (16-bit bus) These bits have no effect on operation. Other modes If port 6 pins are specified for use as the general I/O port, the corresponding pins function as output port when the P6DDR bits are set to 1, and as input port when cleared to 0. Description If port 6 pins are specified for use as the general I/O port, the corresponding pins function as output port when the P6DDR bits are set to 1, and as input ports when cleared to 0.
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Port 6 Data Register (P6DR)
P6DR stores output data for the port 6 pins.
Bit 7 6 5 4 3 2 1 0 Bit Name P67DR P66DR P65DR P64DR P63DR P62DR P61DR P60DR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description These bits store output data for the port 6 pins that are used as the general output port. If this register is read, the P6DR values are read for the bits with the corresponding P6DDR bits set to 1. For the bits with the corresponding P6DDR bits cleared to 0, the pin states are read. * Normal extended mode (16-bit data bus) Since the corresponding pins function as bidirectional data bus pins, the value in these bits has no effect on operation. If this register is read, the P6DR values are read for the bits with the corresponding P6DDR bits set to 1. For the bits with the corresponding P6DDR bits cleared to 0, 1 is read. * Other modes These bits store output data for the port 6 pins that are used as the general output port. If this register is read, the P6DR values are read for the bits with the corresponding P6DDR bits set to 1. For the bits with the corresponding P6DDR bits cleared to 0, the pin states are read.
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Port 6 Pull-Up MOS Control Register (P6PCR)
P6PCR controls the port 6 built-in input pull-up MOSs.
Bit 7 6 5 4 3 2 1 0 Bit Name P67PCR P66PCR P65PCR P64PCR P23PCR P62PCR P61PCR P60PCR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W * Description * Normal extended mode (16-bit bus) This register has no effect on operation. Other modes When the pins are in the input state, the corresponding input pull-up MOS is turned on when a P6PCR bit is set to 1.
(4) (a)
Pin Functions Normal Extended Mode
* 16-bit bus mode Port pins 63 to 60 are automatically set to function as bidirectional data bus pins. * 8-bit bus mode The operation is the same as that in single-chip mode. (b) Address-Data Multiplex Extended Mode
The operation is the same as that in single-chip mode.
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(c)
Single-Chip Mode
Port 6 pins can operate as the PWMX output, SCIF and SSU control input/output, interrupt input, or general I/O port pins. The relationship between register setting values and pin functions are as follows. * P67/ExIRQ8/SSCK The pin function is switched as shown below according to the SCKS bit in SSCRH of the SSU and the P67DDR bit. When the ISS8 bit in ISSR16 is set to 1, this pin can be used as the ExIRQ8 input pin. To use as the ExIRQ8 input pin, clear the P67DDR bit to 0.
SCKS P67DDR Pin function 0 P67 input pin ExIRQ8 input pin [Legend] X: Don't care. 0 1 P67 output pin 1 X SSCK I/O pin
* P66/ExIRQ9/SCS The pin function is switched as shown below according to the CSS1 and CSS0 bits in SSCRH of the SSU and the P66DDR bit. When the ISS9 bit in ISSR16 is set to 1, this pin can be used as the ExIRQ9 input pin. To use as the ExIRQ9 input pin, clear the P66DDR bit to 0.
CSS1, CSS0 P66DDR Pin function 0 P66 input pin ExIRQ9 input pin [Legend] X: Don't care. 00 1 P66 output pin 01 or 1X X SCS I/O pin
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* P65/ExIRQ10/RTS The pin function is switched as shown below according to the combination of the enable/disable setting of the SCIF and the P65DDR bit. When the ISS10 bit in ISSR16 is set to 1, this pin can be used as the ExIRQ10 input pin. To use as the ExIRQ10 input pin, clear the P65DDR bit to 0.
SCIF P65DDR Pin function 0 P65 input pin IRQ10 input pin [Legend] X: Don't care. Disabled 1 P65 output pin Enabled X RTS output pin
* P64/ExIRQ11/CTS The pin function is switched as shown below according to the combination of the enable/disable setting of the SCIF and the P64DDR bit. When the ISS10 bit in ISSR16 is set to 1, this pin can be used as the ExIRQ11 input pin. To use as the ExIRQ11 input pin, clear the P64DDR bit to 0.
SCIF P64DDR Pin function 0 P64 input pin IRQ11 input pin [Legend] X: Don't care. Disabled 1 P64 output pin Enabled X CTS input pin
* P63/PWX3 The pin function is switched as shown below according to the combination of the OEB bit in DACR and the PWMXS bit in PTCNT0 of PWMX_1 and the P63DDR bit.
P63DDR PWMXS OEB Pin function 0 0 0 1 X 0 0 1 1 X X 0 1 PWX3 output pin
P63 input pin
P63 output pin
[Legend] X: Don't care.
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* P62/PWX2 The pin function is switched as shown below according to the combination of the OEA bit in DACR and the PWMXS bit in PTCNT0 of PWMX_1 and the P62DDR bit.
P62DDR PWMXS OEA Pin function 0 0 0 1 X 0 0 1 1 X X 0 1 PWX2 output pin
P62 input pin
P62 output pin
[Legend] X: Don't care.
* P61/IRQ15/PWX1 The pin function is switched as shown below according to the combination of the OEB bit in DACR and the PWMXS bit in PTCNT0 of PWMX_0 and the P61DDR bit. To use this pin as the IRQ15 input pin, clear the P61DDR bit to 0.
P61DDR PWMXS OEB Pin function 0 0 0 1 X 0 0 1 1 X X 0 1 PWX1 output pin
P61 input pin IRQ15 input pin
P61 output pin
[Legend] X: Don't care.
* P60/IRQ14/PWX1 The pin function is switched as shown below according to the combination of the OEA bit in DACR and the PWMXS bit in PTCNT0 of PWMX_0 and the P60DDR bit. To use this pin as the IRQ14 input pin, clear the P60DDR bit to 0.
P60DDR PWMXS OEA Pin function 0 0 0 1 X 0 0 1 1 X X 0 1 PWX0 output pin
P60 input pin IRQ14 input pin
P60 output pin
[Legend] X: Don't care.
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(5)
Port 6 Input Pull-Up MOS
Port 6 has built-in input pull-up MOSs that can be controlled by software. Table 8.14 summarizes the input pull-up MOS states. Table 8.14 Port 6 Input Pull-Up MOS States
Reset Off Hardware Standby Mode Off Software Standby Mode On/Off In Other Operations On/Off
[Legend] Off: Always off. On/Off: On when input state, P6DDR = 0, and P6PCR = 1; otherwise off.
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8.2.7
Port 7
Port 7 is an 8-bit input port. Port 7 pins can also function as the A/D converter analog input pins. Port 7 has the following register. * Port 7 input data register (P7PIN) (1) Port 7 Input Data Register (P7PIN)
P7PIN indicates the states of the port 7 pins.
Bit 7 6 5 4 3 2 1 0 Note: Bit Name P77PIN P76PIN P75PIN P74PIN P73PIN P72PIN P71PIN P70PIN * Initial Value Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* R/W R R R R R R R R Description When this register is read, the pin states are read. Since this register is allocated to the same address as PBDDR, writing to this register writes data to PBDDR and the port B setting is changed.
The initial values are determined in accordance with the pin states of P77 to P70.
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(2)
Pin Functions
Each pin of port 7 can also be used as the analog input pins of the A/D converter (AN0 to AN7). * P77/AN7 The pin function is switched as shown below according to the CH2 to CH0 bits in ADCSR of the A/D converter. Do not set these bits to other values than those shown in the following table.
CH2 to CH0 Pin function B'111 AN7 input pin Other than B'111 P77 input pin
* P76/AN6 The pin function is switched as shown below according to the combination of the SCANE bit in ADCR and the CH2 to CH0 bits in ADCSR of the A/D converter. Do not set these bits to other values than those shown in the following table.
SCANE CH2 to CH0 Pin function B'110 AN6 input pin 0 Other than B'110 P76 input pin B'110 to B'111 AN6 input pin 1 B'000 to B'101 P76 input pin
* P75/AN5 The pin function is switched as shown below according to the combination of the SCANE bit in ADCR and the CH2 to CH0 bits in ADCSR of the A/D converter. Do not set these bits to other values than those shown in the following table.
SCANE CH2 to CH0 Pin function B'101 AN5 input pin 0 Other than B'101 P75 input pin B'101 to B'111 AN5 input pin 1 B'000 to B'100 P75 input pin
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* P74/AN4 The pin function is switched as shown below according to the combination of the SCANE bit in ADCR and the CH2 to CH0 bits in ADCSR of the A/D converter. Do not set these bits to other values than those shown in the following table.
SCANE CH2 to CH0 Pin function B'100 AN4 input pin 0 Other than B'100 P74 input pin B'100 to B'111 AN4 input pin 1 B'000 to B'011 P74 input pin
* P73/AN3 The pin function is switched as shown below according to the combination of the SCANE and SCANE bits in ADCR and the CH2 to CH0 bits in ADCSR of the A/D converter. Do not set these bits to other values than those shown in the following table.
SCANE SCANS CH2 to CH0 Pin function
B'011 AN3 input pin
0 X
Other than B'011 P73 input pin B'011 AN3 input pin
1 0
Other than B'011 P73 input pin
1
B'011 to B'111 B'000 to B'010 AN3 input pin P73 input pin
[Legend] X: Don't care.
* P72/AN2 The pin function is switched as shown below according to the combination of the SCANE and SCANE bits in ADCR and the CH2 to CH0 bits in ADCSR of the A/D converter. Do not set these bits to other values than those shown in the following table.
SCANE SCANS CH2 to CH0 Pin function
B'010
0 X
Other than B'010
1 0
B'010 to B'011
1
B'000 to B'001 P72 input pin
Other than B'010 to B'111 B'010 to B'011 P72 input pin AN2 input pin
AN2 input pin P72 input pin AN2 input pin
[Legend] X: Don't care.
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* P71/AN1 The pin function is switched as shown below according to the combination of the SCANE and SCANS bits in ADCR and the CH2 to CH0 bits in ADCSR of the A/D converter. Do not set these bits to other values than those shown in the following table.
SCANE SCANS CH2 to CH0
B'001
0 X
Other than B'001 B'001 to B'011
1 0
Other than B'001 to B'011 B'001 to B'111
1
B'000
Pin function
AN1 input pin P71 input pin AN1 input pin P71 input pin AN1 input pin P71 input pin
[Legend] X: Don't care.
* P70/AN0 The pin function is switched as shown below according to the combination of the SCANE and SCANS bits in ADCR and the CH2 to CH0 bits in ADCSR of the A/D converter. Do not set these bits to other values than those shown in the following table.
SCANE SCANS CH2 to CH0 Pin function
B'000 AN0 input pin
0 X
Other than B'000 P70 input pin B'000 to B'011 AN0 input pin
1 0
Other than B'000 to B'011 P70 input pin
1
B'000 to B'111 AN0 input pin
[Legend] X: Don't care.
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8.2.8
Port 8
Port 8 is an 8-bit I/O port. Port 8 pins can also function as the A/D converter external trigger input, SCI_1 and SCI_3 input/output, IIC_0 and IIC_1 input/output, and interrupt input pins. Pins 83 to 80 perform the NMOS push-pull output. Port 8 has the following registers. * Port 8 data direction register (P8DDR) * Port 8 data register (P8DR) (1) Port 8 Data Direction Register (P8DDR)
The individual bits of P8DDR specify input or output for the port 8 pins.
Bit 7 6 5 4 3 2 1 0 Bit Name P87DDR P86DDR P85DDR P84DDR P83DDR P82DDR P81DDR P80DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description If port 8 pins are specified for use as the general I/O port, the corresponding pins function as output port when the P8DDR bits are set to 1, and as input port when cleared to 0. Since this register is allocated to the same address as PBPIN, states of the port 8 pins are when this register is read.
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Port 8 Data Register (P8DR)
P8DR stores output data for the port 8 pins.
Bit 7 6 5 4 3 2 1 0 Bit Name P87DR P86DR P85DR P84DR P83DR P82DR P81DR P80DR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description P8DR stores output data for the port 8 pins that are used as the general output port. If this register is read, the P8DR values are read for the bits with the corresponding P8DDR bits set to 1. For the bits with the corresponding P8DDR bits cleared to 0, the pin states are read.
(3)
Pin Functions
The relationship between register setting values and pin functions are as follows. * P87/ExIRQ15/TxD3/ADTRG The pin function is switched as shown below according to the combination of the TE bit in SCR of SCI_3, the SMIF bit in SCMR, and the P87DDR bit. When the TRGS1 and EXTRGS bits are both set to 1 and the TRGS0 bit is cleared to 0 in ADCR of the A/D converter, this pin can be used as the ADTRG input pin. When the ISS15 bit in ISSR16 is set to 1, this pin can be used as the ExIRQ15 input pin. To use this pin as the ExIRQ15 input pin, clear the P87DDR bit to 0.
P87DDR SMIF TE Pin function 0 0 P87 input pin ExIRQ15 input pin/ ADTRG input pin [Legend] X: Don't care. 0 1 X 0 0 1 X 1 0 1 TxD3 output pin
P87 output pin
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* P86/ExIRQ14/RxD3 The pin function is switched as shown below according to the combination of the RE bit in SCR of SCI_3, the SMIF bit in SCMR, and the P86DDR bit. When the ISS14 bit in ISSR16 is set to 1, this pin can be used as the ExIRQ14 input pin. To use this pin as the ExIRQ14 input pin, clear the P86DDR bit to 0.
P86DDR SMIF RE Pin function 0 P86 input pin ExIRQ14 input pin 0 1 RxD3 input pin RxD3 input/output pin 0 1 1 0 0 P86 output pin
* P85/ExIRQ13/SCK1 The pin function is switched as shown below according to the combination of the C/A bit in SMR of SCI_1, the CKE1 and CKE0 bits in SCR, and the P85DDR bit. When the ISS13 bit in ISSR16 is set to 1, this pin can be used as the ExIRQ13 input pin. To use this pin as the ExIRQ13 input pin, clear the P85DDR bit to 0.
CKE1 C/A CKE0 P85DDR Pin function 0 P85 input pin ExIRQ13 input pin [Legend] X: Don't care. 0 1 P85 output pin 0 1 X SCK1 output pin 0 1 X X SCK1 output pin 1 X X X SCK1 input pin
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* P84/ExIRQ12/SCK3 The pin function is switched as shown below according to the combination of the C/A bit in SMR of SCI_3, the CKE1 and CKE0 bits in SCR, and the P84DDR bit. When the ISS12 bit in ISSR16 is set to 1, this pin can be used as the ExIRQ12 input pin. To use this pin as the ExIRQ12 input pin, clear the P84DDR bit to 0.
CKE1 C/A CKE0 P84DDR Pin function 0 P84 input pin ExIRQ12 input pin [Legend] X: Don't care. 0 1 P84 output pin 0 1 X SCK3 output pin 0 1 X X SCK3 output pin 1 X X X SCK3 input pin
* P83/SDA1 The pin function is switched as shown below according to the combination of the ICE bit in ICCR of IIC_1 and the P83DDR bit. When this pin is used as the P83 output pin, the output format is NMOS push-pull output. The output format for SDA1 is NMOS open-drain output, which allows direct bus drive.
ICE P83DDR Pin function 0 P83 input pin 0 1 P83 output pin 1 X SDA1 input/output pin
[Legend] X: Don't care.
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* P82/SCL1 The pin function is switched as shown below according to the combination of the ICE bit in ICCR of IIC_1 and the P82DDR bit. When this pin is used as the P82 output pin, the output format is NMOS push-pull output. The output format for SCL1 is NMOS open-drain output, which allows direct bus drive.
ICE P82DDR Pin function 0 P82 input pin 0 1 P82 output pin 1 X SCL1 input/output pin
[Legend] X: Don't care.
* P81/SDA0 The pin function is switched as shown below according to the combination of the ICE bit in ICCR of IIC_0 and the P81DDR bit. When this pin is used as the P81 output pin, the output format is NMOS push-pull output. The output format for SDA0 is NMOS open-drain output, which allows direct bus drive.
ICE P81DDR Pin function 0 P81 input pin 0 1 P81 output pin 1 X SDA0 input/output pin
[Legend] X: Don't care.
* P80/SCL0 The pin function is switched as shown below according to the combination of the ICE bit in ICCR of IIC_0 and the P80DDR bit. When this pin is used as the P80 output pin, the output format is NMOS push-pull output. The output format for SCL0 is NMOS open-drain output, which allows direct bus drive.
ICE P80DDR Pin function 0 P80 input pin 0 1 P80 output pin 1 X SCL0 input/output pin
[Legend] X: Don't care.
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8.2.9
Port 9
Port 9 is an 8-bit I/O port. Port 9 pins can function as the bus control input/output pins. The pin functions change according to the operating mode. Port 9 has the following registers. * Port 9 data direction register (P9DDR) * Port 9 data register (P9DR) (1) Port 9 Data Direction Register (P9DDR)
The individual bits of P9DDR specify input or output for the port 9 pins.
Bit 7 6 5 4 3 2 1 0 Bit Name P97DDR P96DDR P95DDR P94DDR P93DDR P92DDR P91DDR P90DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description If port 9 pins are specified for use as the general I/O port, the corresponding pins function as output port when the P9DDR bits are set to 1, and as input port when cleared to 0.
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Port 9 Data Register (P9DR)
P9DR stores output data for the port 9 pins.
Bit 7 6 5 4 3 2 1 0 Bit Name P97DR P96DR P95DR P94DR P93DR P92DR P91DR P90DR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description P9DR stores output data for the port 9 pins that are used as the general output port. If this register is read, the P9DR values are read for the bits with the corresponding P9DDR bits set to 1. For the bits with the corresponding P9DDR bits cleared to 0, the pin states are read.
(3)
Pin Functions
The relationship between register setting values and pin functions are as follows. * P97/WAIT/CS256 The pin function is switched as shown below according to the operating mode and the combination of the CS256E bit in SYSCR, the WMS1 bit in WSCR and the P97DDR bit.
Operating mode WMS1 CS256E P97DDR Pin function 0 0 1 Extended mode 0 1 X CS256 output pin 1 X X 0 Single-chip mode X X 1
P97 input pin P97 output pin
WAIT input P97 input pin P97 output pin pin
[Legend] X: Don't care.
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* P96 The pin function is switched as shown below according to the P96DDR bit.
P96DDR Pin function 0 P96 input pin 1 P96 output pin
* P95/AS/IOS The pin function is switched as shown below according to the operating mode and the combination of the IOSE bit in SYSCR and the P95DDR bit.
Operating mode P95DDR IOSE Pin function [Legend] X: Don't care. 0 AS output pin Extended mode X 1 IOS output pin 0 X P95 input pin Single-chip mode 1 X P95 output pin
* P94/ExPWX1 The pin function is switched as shown below according to the combination of the OEB bit in DACR and the PWMXS bit in PTCNT0 of the PWMX_0 module and the P94DDR bit.
P94DDR PWMXS OEB Pin function 0 X P94 input pin 0 1 0 0 X P94 output pin 1 1 0 X 1 1 ExPWX1 output pin
[Legend] X: Don't care.
* P93/ExPWX0 The pin function is switched as shown below according to the combination of the OEA bit in DACR and the PWMXS bit in PTCNT0 of the PWMX_0 module and the P93DDR bit.
P93DDR PWMXS OEA Pin function [Legend] X: Don't care. 0 X P93 input pin 0 1 0 0 X P93 output pin 1 1 0 X 1 1 ExPWX0 output pin
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* P92/HBE The pin function is switched as shown below according to the operating mode, the OBE bit in PTCNT0, and the P92DDR bit.
Operating mode OBE P92DDR Pin function 0 P92 input pin Extended mode 0 1 1 X 0 P92 input pin P92 output pin HBE output pin Single-chip mode X 1 P92 output pin
[Legend] X: Don't care.
* P91/AH The pin function is switched as shown below according to the operating mode, the ADMXE bit in SYSCR2, and the P91DDR bit.
Operating mode ADMXE P91DDR Pin function 0 P91 input pin Extended mode 0 1 P91 output pin 1 X AH output pin 0 P91 input pin Single-chip mode X 1 P91 output pin
[Legend] X: Don't care.
* P90/LBE The pin function is switched as shown below according to the operating mode, the OBE bit in PTCNT0, and the P90DDR bit.
Operating mode OBE P90DDR Pin function 0 P90 input pin Extended mode 0 1 1 X 0 P90 input pin P90 output pin LBE output pin Single-chip mode X 1 P90 output pin
[Legend] X: Don't care.
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Section 8 I/O Ports
8.2.10
Port A
Port A is an 8-bit I/O port. Port A pins can also function as the address output, event counter input, interrupt input, and EtherC control input/output pins. Port A has the following registers. PADDR and PAPIN are allocated to the same address. * Port A data direction register (PADDR) * Port A output data register (PAODR) * Port A input data register (PAPIN) (1) Port A Data Direction Register (PADDR)
The individual bits of PADDR specify input or output for the port A pins.
Bit 7 6 5 4 3 2 1 0 Bit Name PA7DDR PA6DDR PA5DDR PA4DDR PA3DDR PA2DDR PA1DDR PA0DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description When set to 1, the corresponding pins function as output port pins; when cleared to 0, function as input port pins. As the address of this register is the same as that of PAPIN, reading from this register indicates the state of port A.
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(2)
Port A Output Data Register (PAODR)
PAODR stores output data for the port A pins.
Bit 7 6 5 4 3 2 1 0 Bit Name PA7ODR PA6ODR PA5ODR PA4ODR PA3ODR PA2ODR PA1ODR PA0ODR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description PAODR stores output data for the port A pins that are used as the general output port.
(3)
Port A Input Data Register (PAPIN)
PAPIN indicates the states of the port A pins.
Bit 7 6 5 4 3 2 1 0 Bit Name PA7PIN PA6PIN PA5PIN PA4PIN PA3PIN PA2PIN PA1PIN PA0PIN Initial Value Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* R/W R R R R R R R R Description Pin states are read from this register. As the address of this register is the same as that of PADDR, writing to this register changes the settings of port A, that have been written to PADDR.
Note: *
The initial values are determined in accordance with the pin states of PA7 to PA0.
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(4)
Pin Functions
The relationship between the operating mode, register setting values, and pin functions are as follows. (a) Normal Extended Mode
Port A pins can function as address output, interrupt input, event counter input, EtherC control input/output, or I/O port pins, and input or output can be specified in bit units. Address 18 and address 13 in the following tables are expressed by the following logical expressions according to the control bits of the bus controller or other module. Address 18 = 1: ADFULLE Address 13 = 1: ADFULLE * CS256E * IOSE * PA7/ExIRQ7/EVENT7/A23/EXOUT The pin function is switched as shown below according to the setting of address 18 and the PA7DDR bit. Setting the ISS7 bit in ISSR makes the pin to function as the ExIRQ7 input pin. When using the pin as the ExIRQ7 input or an EVENT input pin, clear the PA7DDR bit to 0. Though the settings for the EVENT input pin have been made, set the PA7DDR bit to 1 when using the pin as the PA7 or A23 output pin. When the module stop mode is cleared in both the EtherC and E-DMAC, this pin functions as the EXOUT output pin.
PA7DDR Address 18 Pin function [Legend] X: Don't care. 0 X PA7 input pin ExIRQ7 input pin/EVENT7 input pin 1 1 PA7 output pin 1 0 A23 output pin
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* PA6/ExIRQ6/EVENT6/A22/LNKSTA The pin function is switched as shown below according to the setting of address 18 and the PA6DDR bit. Setting the ISS6 bit in ISSR makes the pin to function as the ExIRQ6 input pin. When using the pin as the ExIRQ6 input, or an EVENT input pin, clear the PA6DDR bit to 0. Though the settings for the EVENT input pin have been made, set the PA6DDR bit to 1 when using the pin as the PA6 or A22 output pin. When the module stop mode is cleared in both the EtherC and E-DMAC, this pin functions as the LNKSTA input pin.
PA6DDR Address 18 Pin function PA6 input pin ExIRQ6 input pin/EVENT6 input pin 0 1 PA6 output pin 1 1 0 A22 output pin
* PA5/ExIRQ5/EVENT5/A21/WOL The pin function is switched as shown below according to the setting of the MPDE bit in ECMR in EtherC, the address 18, and the PA5DDR bit. Setting the ISS5 bit in ISSR to 1 makes the pin function as the ExIRQ5 input pin. When using the pin as the ExIRQ5 input, or an EVENT input pin, clear the PA5DDR bit to 0. Though the settings for the EVENT input pin have been made, set the PA5DDR bit to 1 when using the pin as the A21 or PA5 output pin. When the module stop mode is cleared in both the EtherC and E-DMAC, this pin functions as the WOL output pin.
MPDE PA5DDR Address 18 Pin function 0 X PA5 input pin ExIRQ5 input pin/ EVENT5 input pin 0 1 1 PA5 output pin 1 0 A21 output pin
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* PA4/ExIRQ4/EVENT4/A20, PA3/ExIRQ3/EVENT3/A19, PA2/ExIRQ2/EVENT2/A18 The pin function is switched as shown below according to the setting of address 18 and the PAnDDR bit. Setting the ISSn bit in ISSR makes the pin to function as the ExIRQn input pin. When using the pin as the ExIRQn input or an EVENT input pin, clear the PAnDDR bit to 0. Though the settings for the EVENT input pin have been made, set the PAnDDR bit to 1 when using the pin as the PAn or Am output pin.
PAnDDR Address 18 Pin function 0 X PAn input pin ExIRQn input pin/EVENTn input pin [Legend] n = 4 to 2, m = 20 to 18, X: Don't care. 1 1 PAn output pin 1 0 Am output pin
* PA1/ExIRQ1/EVENT1/A17, PA0/ExIRQ0/EVENT0/A16 The pin function is switched as shown below according to the setting of address 13 and the PAnDDR bit. Setting the ISSn bit in ISSR makes the pin to function as the ExIRQn input pin. When using the pin as the ExIRQn input, clear the PAnDDR bit to 0. When using the pin as an EVENT input pin, clear the PAnDDR bit to 0. Though the settings for the EVENT input pin have been made, set the PAnDDR bit to 1 when using the pin as the PAn or Am output pin.
PAnDDR Address 13 Pin function [Legend] 0 X PAn input pin ExIRQn input pin/EVENTn input pin n = 1, 0; m = 17, 16, X: Don't care. 1 PAn output pin 1 0 Am output pin
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(b)
Single-Chip Mode and Address-Data Multiplex Extended Mode
Port A pins can also function as interrupt input, EtherC control input/output, and event counter input pins. * PA7/ExIRQ7/EVENT7/EXOUT The pin function is switched as shown below according to the PA7DDR bit. Setting the ISS7 bit in ISSR makes the pin to function as the ExIRQ7 input pin. When using this pin as the ExIRQ7 input or EVENT7 input pin, clear the PA7DDR bit to 0. Though the settings for the EVENT input pin have been made, set the PA7DDR bit to 1 to use the pin as the PA7 output pin. When the module stop mode is cleared in both the EtherC and E-DMAC, this pin functions as the EXOUT output pin.
PA7DDR Pin function 0 PA7 input pin ExIRQ7 input pin/EVENT7 input pin 1 PA7 output pin
* PA6/ExIRQ6/EVENT6/LNKSTA The pin function is switched as shown below according to the PA6DDR bit. Setting the ISS6 bit in ISSR makes the pin to function as the ExIRQ6 input pin. When using this pin as the ExIRQ6 input, or EVENT6 input pin, clear the PA6DDR bit to 0. Though the settings for the EVENT input pin have been made, set the PA6DDR bit to 1 to use the pin as the PA6 output pin. When the module stop mode is cleared in both the EtherC and E-DMAC, this pin functions as the LNKSTA input pin.
PA6DDR Pin function 0 PA6 input pin ExIRQ6 input pin/EVENT6 input pin 1 PA6 output pin
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* PA5/ExIRQ5/EVENT5/WOL The pin function is switched as shown below according to the setting of the and the PA5DDR bit. Setting the ISS5 bit in ISSR makes the pin to function as the ExIRQ5 input pin. When using this pin as the ExIRQ5 input, or EVENT5 input pin, clear the PA5DDR bit to 0. Though the settings for the EVENT input pin have been made, set the PA5DDR bit to 1 to use the pin as the PA5 output pin. When the module stop mode is cleared in both the EtherC and E-DMAC, this pin functions as the WOL output pin.
PA5DDR Pin function 0 PA5 input pin ExIRQ5 input pin/EVENT5 input pin 1 PA5 output pin
* PA4/ExIRQ4/EVENT4, PA3/ExIRQ3/EVENT3, PA2/ExIRQ2/EVENT2, PA1/ExIRQ1/EVENT1, PA0/ExIRQ0/EVENT0 The pin function is switched as shown below according to the PAnDDR bit. Setting the ISSn bit in ISSR makes the pin to function as the ExIRQn input pin. When using this pin as the ExIRQn input or EVENTn input pin, clear the PAnDDR bit to 0. Though the settings for the EVENT input pin have been made, set the PAnDDR bit to 1 to use the pin as the PAn output pin.
PAnDDR Pin function [Legend] n = 4 to 0 0 PAn input pin ExIRQn input pin/EVENTn input pin 1 PAn output pin
(5)
Input Pull-Up MOS
Port A has built-in input pull-up MOSs that can be controlled by software. This input pull-up MOS can be used in any operating mode, and can be specified as on or off on a bit-by-bit basis.
PAnDDR PAnODR PAn pull-up MOS [Legend] 1 ON n = 7 to 0, X: Don't care. 0 0 OFF 1 X OFF
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The input pull-up MOS is in the off state after a reset and in hardware standby mode. The prior state is retained in software standby mode. Table 8.15 summarizes the input pull-up MOS states. Table 8.15 Input Pull-Up MOS States
Reset Off Hardware Standby Mode Off Software Standby Mode On/Off In Other Operations On/Off
[Legend] Off: Always off. On/Off: On when PADDR = 0 and PAODR = 1; otherwise off.
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8.2.11
Port B
Port B is an 8-bit I/O port. Port B pins can also function as the event counter input, de-bounced input, and EtherC control input/output pins. The pin functions change according to the operating mode. Port B has the following registers. * Port B data direction register (PBDDR) * Port B output data register (PBODR) * Port B input data register (PBPIN) * Noise canceler enable register (P4BNCE) * Noise canceler mode control register (P4BNCMC) * Noise cancel cycle setting register (NCCS) (1) Port B Data Direction Register (PBDDR)
The individual bits of PBDDR specify input or output for the pins of port B.
Bit 7 6 5 4 3 2 1 0 Bit Name PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR Initial Value 0 0 0 0 0 0 0 0 R/W Description W W W W W W W W When set to 1, the corresponding pins function as output port pins; when cleared to 0, function as input port pins.
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(2)
Port B Output Data Register (PBODR)
PBDR stores output data for the port B pins.
Bit 7 6 5 4 3 2 1 0 Bit Name PB7DR PB6DR PB5DR PB4DR PB3DR PB2DR PB1DR PB0DR Initial Value 0 0 0 0 0 0 0 0 R/W Description R/W PBODR stores output data for the port B pins that are used as the general output port. R/W R/W R/W R/W R/W R/W R/W
(3)
Port B Input Data Register (PBPIN)
PBPIN indicates the states of the port B pins.
Bit 7 6 5 4 3 2 1 0 Note: Bit Name PB7PIN PB6PIN PB5PIN PB4PIN PB3PIN PB2PIN PB1PIN PB0PIN * Initial Value Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* R/W R R R R R R R R Description When this register is read, the pin states are read. Since this register is allocated to the same address as P8DDR, writing to this register writes data to P8DDR and the port 8 setting is changed.
The initial values are determined in accordance with the pin states of PB7 to PB0.
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Noise Canceler Enable Register (P4BNCE)
P4BNCE enables or disables the noise canceler circuits of port 4 and port B pins in bit units.
Bit Bit Name Initial Value All 0 0 0 0 0 R/W Description R/W Bits for port 4 setting R/W Enables the noise canceler circuit for the corresponding pin and the pin state is fetched into PBDR at the R/W sampling cycle set by NCCS. R/W The operation changes according to the other control R/W bits. See section 8.2.11 (7), Pin Functions, for details.
7 to 4 P47NCE to P44NCE 3 2 1 0 PB3NCE PB2NCE PB1NCE PB0NCE
(5)
Noise Canceler Mode Control Register (P4BNCMC)
P4BNCMC controls whether 1 or 0 is expected for the input signal to port 4 and port B in bit units.
Bit Bit Name Initial Value All 1 R/W Description R/W Bits for port 4 setting
7 to 4 P47NCMC to P44NCMC 3 2 1 0 PB3NCMC PB2NCMC PB1NCMC PB0NCMC
1 1 1 1
R/W Expected value setting R/W 1 expected: 1 is stored in the port data register while 1 is input stably. R/W 0 expected: 0 is stored in the port data register while 0 R/W is input stably.
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(6)
Noise Canceler Cycle Setting Register (NCCS)
NCCS controls the sampling cycle of the noise cancelers.
Bit Bit Name Initial Value Undefined 0 0 0 R/W Description R/W Reserved Undefined value is read from these bits. 2 1 0 NCCK2 NCCK1 NCCK0 R/W These bits set the sampling cycle of the noise R/W cancelers. R/W * When = 34 MHz 000: 0.06 s 001: 0.94 s 010: 15.1 s /2 /32 /512 100: 963.8 s /32768 101: 1.9 ms 110: 3.9 ms 111: 7.7 ms /65536 /131072 /262144
7 to 3
011: 240.9 s /8192
/2, /32, /512, /8192, /32768, /65536, /131072, /262144 Sampling clock selection t
Pin input
Latch
Latch
Latch
Match detection circuit
Port data register
t
Sampling clock
Figure 8.11 Noise Canceler Circuit
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PBn input
1 expected PBnDR
0 expected PBnDR
(n = 3 to 0)
Figure 8.12 Noise Canceler Operation (7) Pin Functions
* PB7/EVENT15/RM_RX-ER, PB6/EVENT14/RM_CRS-DV, PB5/EVENT13/RM_REF-CLK PB4/EVENT12/RM_TX-EN The pin function is switched as shown below according to the PBnDDR bit. When using this pin as the EVENT input pin, clear the PBnDDR bit to 0. These pins can be used as EtherC I/O pins when the EtherC is enabled.
EtherC, E-DMAC PBnDDR Event counter Pin function [Legend] Note: * Disabled PBn input pin Either of them is stopped 0 Enabled EVENTm input pin 1 X PBn output pin Both of them are stopped X X RM_xxxx EtherC I/O pin
n = 7 to 4, m = 15 to 8, X: Don't care. See section 7.3, DTC Event Counter, for the event counter settings.
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* PB3/EVENT11/DB3/RM_RXD1, PB2/EVENT10/DB2/RM_RXD0, PB1/EVENT9/DB1/RM_TXD1, PB0/EVENT8/DB0/RM_TXD0 The pin function is switched as shown below according to the combination of the module stop state in the EtherC and E-DMAC and the PBnDDR bit.
EtherC, E-DMAC PBnDDR Event counter PBnNCE Pin function [Legend] 0 PBn input Disabled 1 DBn input Either of them is stopped 0 Enabled X EVENTm input 1 X X PBn output pin Both of them are stopped X X X RM_xxxx EtherC I/O pin
n = 3 to 0, m = 11 to 8, X: Don't care.
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8.2.12
Port C
Port C is an 8-bit I/O port. Port C pins can also function as the bus control output, and IIC_2, IIC_3, and IIC_4 input/output pins. The output format of ports C0 to C5 is NMOS push-pull output. Port C has the following registers. * Port C data direction register (PCDDR) * Port C output data register (PCODR) * Port C input data register (PCPIN) (1) Port C Data Direction Register (PCDDR)
The individual bits of PCDDR specify input or output for the port C pins.
Bit 7 6 5 4 3 2 1 0 Bit Name PC7DDR PC6DDR PC5DDR PC4DDR PC3DDR PC2DDR PC1DDR PC0DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description When set to 1, the corresponding pins function as output port pins; when cleared to 0, function as input port pins. Since this register is allocated to the same address as PCPIN, states of the port C pins are returned when this register is read.
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Port C Output Data Register (PCODR)
PCODR stores output data for the port C pins.
Bit 7 6 5 4 3 2 1 0 Bit Name PC7ODR PC6ODR PC5ODR PC4ODR PC3ODR PC2ODR PC1ODR PC0ODR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description The PCODR register stores the output data for the pins that are used as the general output port.
(3)
Port C Input Data Register (PCPIN)
PCPIN indicates the pin states of port C.
Bit 7 6 5 4 3 2 1 0 Bit Name PC7PIN PC6 PIN PC5PIN PC4 PIN PC3 PIN PC2 PIN PC1 PIN PC0 PIN Initial Value Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* R/W R R R R R R R R Description When this register is read, the pin states are read. Since this register is allocated to the same address as PCDDR, writing to this register writes data to PCDDR and the port C setting is changed.
Note: The initial values are determined in accordance with the states of PC7 to PC0 pins.
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(4) (a)
Pin Functions Normal Extended Mode and Address-Data Multiplex Extended Mode
Port C pins can also function as the bus control output and IIC_2, IIC_3, and IIC_4 input/output pins. The relationship between register setting values and pin functions are as follows. * PC7 The PC7 pin functions as a bus control output pin. * PC6 When set for 16-bit bus width, the PC7 pin functions as a bus control output pin. When 8-bit bus width, the pin function is the same as that in single-chip mode. * PC5 to PC0 The pin functions are the same as those in single-chip mode.
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(b)
Single-Chip Mode
* PC7, PC6 The pin function is switched as shown below according to the PCnDDR bit.
PCnDDR Pin function [Legend] n = 7, 6 0 PCn input pin 1 PCn output pin
* PC5/SDA4 The pin function is switched as shown below according to the combination of the ICE bit in ICCR of the IIC_4 and the PC5DDR bit.
ICE PC5DDR Pin function [Legend] X: Don't care. 0 PC5 input pin 0 1 PC5 output pin 1 X SDA4 input/output pin
* PC4/SCL4 The pin function is switched as shown below according to the combination of the ICE bit in ICCR of the IIC_4 and the PC4DDR bit.
ICE PC4DDR Pin function [Legend] X: Don't care. 0 PC4 input pin 0 1 PC4 output pin 1 X SCL4 input/output pin
* PC3/SDA3 The pin function is switched as shown below according to the combination of the ICE bit in ICCR of the IIC_3 and the PC3DDR bit.
ICE PC3DDR Pin function [Legend] X: Don't care. 0 PC3 input pin 0 1 PC3 output pin 1 X SDA3 input/output pin
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* PC2/SCL3 The pin function is switched as shown below according to the combination of the ICE bit in ICCR of the IIC_3 and the PC2DDR bit.
ICE PC2DDR Pin function [Legend] X: Don't care. 0 PC2 input pin 0 1 PC2 output pin 1 X SCL3 input/output pin
* PC1/SDA2 The pin function is switched as shown below according to the combination of the ICE bit in ICCR of the IIC_2 and the PC1DDR bit.
ICE PC1DDR Pin function [Legend] X: Don't care. 0 PC1 input pin 0 1 PC1 output pin 1 X SDA2 input/output pin
* PC0/SCL2 The pin function is switched as shown below according to the combination of the ICE bit in ICCR of the IIC_2 and the PC0DDR bit.
ICE PC0DDR Pin function [Legend] X: Don't care. 0 PC0 input pin 0 1 PC0 output pin 1 X SCL2 input/output pin
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8.2.13
Port D
Port D is an 8-bit I/O port. Port D pins can also function as the IIC_5 input/output and LPC input/output pins. The output format of PD7 and PD6 pins is NMOS push-pull output. Port D has the following registers. * Port D data direction register (PDDDR) * Port D output data register (PDODR) * Port D input data register (PDPIN) (1) Port D Data Direction Register (PDDDR)
The individual bits of PDDDR specify input or output for the port D pins.
Bit 7 6 5 4 3 2 1 0 Bit Name PD7DDR PD6DDR PD5DDR PD4DDR PD3DDR PD2DDR PD1DDR PD0DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description If port D pins are specified for use as the general I/O port, the corresponding pins function as output port when the PDDDR bits are set to 1, and as input port when cleared to 0. Since this register is allocated to the same address as PDPIN, the states of the port D pins are returned when this register is read.
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Port D Output Data Register (PDODR)
PDODR stores output data for the port D pins.
Bit 7 6 5 4 3 2 1 0 Bit Name PD7ODR PD6ODR PD5ODR PD4ODR PD3ODR PD2ODR PD1ODR PD0ODR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description The PCODR register stores the output data for the pins that are used as the general output port.
(3)
Port D Input Data Register (PDPIN)
PDPIN indicates the pin states of port D.
Bit 7 6 5 4 3 2 1 0 Bit Name PD7PIN PD6PIN PD5PIN PD4PIN PD3PIN PD2PIN PD1PIN PD0PIN Initial Value Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* R/W R R R R R R R R Description When this register is read, the pin states are read. Since this register is allocated to the same address as PDDDR, writing to this register writes data to PDDDR and the port D setting is changed.
Note: The initial values are determined in accordance with the states of PD7 to PD0 pins.
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Pin Functions
Port D pins can also function as the LPC input/output and IIC_5 input/output pins. The relationship between register setting values and pin functions are as follows. The LPC is disabled when all of the bits LPC1E, LPC2E, and LPC3E in HICR0 and SCIFE in HICR5 are cleared to 0. * PD7/SDA5 The pin function is switched as shown below according to the combination of the ICE bit in ICCR of the IIC_5 and the PD7DDR bit.
ICE PD7DDR Pin function [Legend] X: Don't care. 0 PD7 input pin 0 1 PD7 output pin 1 X SDA5 input/output pin
* PD6/SCL5 The pin function is switched as shown below according to the combination of the ICE bit in ICCR of the IIC_5 and the PD6DDR bit.
ICE PD6DDR Pin function [Legend] X: Don't care. 0 PD6 input pin 0 1 PD6 output pin 1 X SCL5 input/output pin
* PD5/LPCPD The pin function is switched as shown below according to the PD5DDR bit. This pin can be used as the LPCPD input pin when the LPC is enabled.
LPC PD5DDR Pin function 0 PD5 input pin Disabled 1 PD5 output pin Enabled 0 LPCPD input pin
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* PD4/CLKRUN The pin function is switched as shown below according to the PD4DDR bit. This pin can be used as the CLKRUN input pin when the LPC is enabled.
LPC PD4DDR Pin function 0 PD4 input pin Disabled 1 PD4 output pin Enabled 0 CLKRUN input/output pin
* PD3/GA20 The pin function is switched as shown below according to the combination of the FGA20E bit in HICR0 of the LPC and the PD3DDR bit.
FGA20E PD3DDR Pin function 0 PD3 input pin 0 1 PD3 output pin 1 0 GA20 output pin
* PD2/PME The pin function is switched as shown below according to the combination of the PMEE bit in HICR0 of the LPC and the PD2DDR bit.
PMEE PD2DDR Pin function 0 PD2 input pin 0 1 PD2 output pin 1 0 PME output pin
* PD1/LSMI The pin function is switched as shown below according to the combination of the LSMIE bit in HICR0 of the LPC and the PD1DDR bit.
LSMIE PD1DDR Pin function 0 PD1 input pin 0 1 PD1 output pin 1 0 LSMI output pin
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* PD0/LSCI The pin function is switched as shown below according to the combination of the LSCIE bit in HICR0 of the LPC and the PD0DDR bit.
LSCIE PD0DDR Pin function 0 PD0 input pin 0 1 PD0 output pin 1 0 LSCI output pin
(5)
Input Pull-Up MOS
Port pins D5 to D0 have built-in input pull-up MOSs that can be controlled by software. This input pull-up MOS can be used in any operating mode, and can be specified as on or off on a bit-by-bit basis.
PDnDDR PDnODR PDn pull-up MOS [Legend] 1 ON n = 5 to 0, X: Don't care. 0 0 OFF 1 X OFF
The input pull-up MOS is in the off state after a reset and in hardware standby mode. The prior state is retained in software standby mode. Table 8.16 summarizes the input pull-up MOS states. Table 8.16 Port D Input Pull-Up MOS States
Reset Off Hardware Standby Mode Off Software Standby Mode On/Off In Other Operations On/Off
[Legend] Off: Always off. On/Off: On when PDDDR = 0 and PDODR = 1; otherwise off.
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8.2.14
Port E
Port E is an 8-bit I/O port. Port E pins can also function as the LPC input/output pins. Port E has the following registers. * Port E data direction register (PEDDR) * Port E output data register (PEODR) * Port E input data register (PEPIN) (1) Port E Data Direction Register (PEDDR)
The individual bits of PEDDR specify input or output for the port E pins.
Bit 7 6 5 4 3 2 1 0 Bit Name PE7DDR PE6DDR PE5DDR PE4DDR PE3DDR PE2DDR PE1DDR PE0DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description When set to 1, the corresponding pins function as output port pins; when cleared to 0, function as input port pins. Since this register is allocated to the same address as PEPIN, states of the port E pins are returned when this register is read.
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Port E Output Data Register (PEODR)
PEODR stores output data for the port E pins.
Bit 7 6 5 4 3 2 1 0 Bit Name PE7ODR PE6ODR PE5ODR PE4ODR PE3ODR PE2ODR PE1ODR PE0ODR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description The PEODR register stores the output data for the pins that are used as the general output port.
(3)
Port E Input Data Register (PEPIN)
PEPIN indicates the pin states of port E.
Bit 7 6 5 4 3 2 1 0 Bit Name PE7PIN PE6PIN PE5PIN PE4PIN PE3PIN PE2PIN PE1PIN PE0PIN Initial Value Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* R/W R R R R R R R R Description When this register is read, the pin states are read. Since this register is allocated to the same address as PEDDR, writing to this register writes data to PEDDR and the port E setting is changed.
Note: The initial value of these pins is determined in accordance with the state of pins PE7 to PE0.
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Pin Functions
Port E pins can also function as LPC input/output pins. The pin function is switched according to whether the LPC module is enabled or disabled. The LPC is disabled when all of the bits LPC1E, LPC2E, and LPC3E in HICR0 and SCIFE in HICR5 are cleared to 0. * PE7/SERIRQ The pin function is switched as shown below according to whether the LPC is enabled or disabled and the PE7DDR bit.
LPC PE7DDR Pin function [Legend] X: Don't care. 0 PE7 input pin Disabled 1 PE7 output pin Enabled X SERIRQ input/output pin
* PE6/LCLK The pin function is switched as shown below according to whether the LPC is enabled or disabled and the PE6DDR bit.
LPC PE6DDR Pin function [Legend] X: Don't care. 0 PE6 input pin Disabled 1 PE6 output pin Enabled X LCLK input pin
* PE5/LRESET The pin function is switched as shown below according to whether the LPC is enabled or disabled and the PE5DDR bit.
LPC PE5DDR Pin function [Legend] X: Don't care. 0 PE5 input pin Disabled 1 PE5 output pin Enabled X LRESET input pin
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* PE4/LFRAME The pin function is switched as shown below according to whether the LPC is enabled or disabled and the PE4DDR bit.
LPC PE4DDR Pin function [Legend] X: Don't care. 0 PE4 input pin Disabled 1 PE4 output pin Enabled X LFRAME input pin
* PE3/LAD3 The pin function is switched as shown below according to whether the LPC is enabled or disabled and the PE3DDR bit.
LPC PE3DDR Pin function [Legend] X: Don't care. 0 PE3 input pin Disabled 1 PE3 output pin Enabled X LAD3 input/output pin
* PE2/LAD2 The pin function is switched as shown below according to whether the LPC is enabled or disabled and the PE2DDR bit.
LPC PE2DDR Pin function [Legend] X: Don't care. 0 PE2 input pin Disabled 1 PE2 output pin Enabled X LAD2 input/output pin
* PE1/LAD1 The pin function is switched as shown below according to whether the LPC is enabled or disabled and the PE1DDR bit.
LPC PE1DDR Pin function [Legend] X: Don't care. 0 PE1 input pin Disabled 1 PE1 output pin Enabled X LAD1 input/output pin
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* PE0/LAD0 The pin function is switched as shown below according to whether the LPC is enabled or disabled and the PE0DDR bit.
LPC PE0DDR Pin function [Legend] X: Don't care. 0 PE0 input pin Disabled 1 PE0 output pin Enabled X LAD0 input/output pin
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8.2.15
Port F
Port F is a 3-bit I/O port. Port F pins can also function as the PWMX output and EtherC control I/O pins. Port F has the following registers. * Port F data direction register (PFDDR) * Port F output data register (PFODR) * Port F input data register (PFPIN) (1) Port F Data Direction Register (PFDDR)
The individual bits of PFDDR specify input or output for the port F pins. PFDDR is initialized only by a system reset, and retains the value even if an internal reset signal of the WDT is generated.
Bit 7 6 Bit Name PF6DDR Initial Value 0 R/W W Description Reserved When set to 1, the corresponding pin functions as an output port pin; when cleared to 0, functions as an input port pin. Since this register is allocated to the same address as PFPIN, states of the port F pins are returned when this register is read. 5 to 2 1 0 PF1DDR PF0DDR 0 0 W W Reserved When set to 1, the corresponding pin functions as an output port pin; when cleared to 0, functions as an input port pin. Since this register is allocated to the same address as PFPIN, states of the port F pins are returned when this register is read.
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Port F Output Data Register (PFODR)
PFODR stores output data for the port F pins. PEODR is initialized only by a system reset, and retains the value even if an internal reset signal of the WDT is generated.
Bit 7 6 Bit Name PF6ODR Initial Value 0 0 0 R/W R/W R/W R/W Description Reserved Undefined value is read from this bit. Stores the output data for the pin that is used as the general output port. Reserved Undefined values are read from these bits. 1 0 PF1ODR PF0ODR Store the output data for the pins that are used as the general output port.
5 to 2
(3)
Port F Input Data Register (PFPIN)
PFPIN indicates the pin states of port F.
Bit 7 6 Bit Name PF6PIN Initial Value Undefined* R/W R Description Reserved Undefined value is read from this bit. When this register is read, the pin states are read. Since this register is allocated to the same address as PFDDR, writing to this register writes data to PFDDR and the port F setting is changed. 5 to 2 1 0 PF1PIN PF0PIN Undefined* Undefined* R R Reserved Undefined values are read from these bits. When this register is read, the pin states are read. Since this register is allocated to the same address as PFDDR, writing to this register writes data to PFDDR and the port F setting is changed.
Note: * The initial value of these pins is determined in accordance with the state of pins PF6, PF1, and PF0.
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Pin Functions
Port F is a 3-bit I/O port. Port F pins can also function as PWMX output pins and EtherC control I/O pins. The relationship between the register settings and the pin function is shown below. * PF6/ExPWX2/RS14 The pin function is switched as shown below according to the combination of the OEA bit in DACR, the PWMXS bit in PTCNT0 of PWMX_1, and the PF6DDR bit.
PF6DDR PWMXS OEA Pin function [Legend] 0 X X: Don't care. 0 1 0 0 X 1 1 0 X 1 1 ExPWX2 output pin
PF6 input pin
PF6 output pin
* PF1/RS9/MDC The pin function is switched as shown below according to the combination of the module stop state in the EtherC and e-DMAC and the PF1DDR bit.
EtherC, E-DMAC PF1DDR Pin function [Legend] X: Don't care. 0 PF1 input pin Either of them is stopped 1 PF1 output pin Both of them are stopped X MDC output pin
* PF0/RS0/MDIO The pin function is switched as shown below according to the combination of the module stop state in the EtherC and e-DMAC and the PF0DDR bit.
EtherC, E-DMAC PF0DDR Pin function [Legend] X: Don't care. 0 PF0 input pin Either of them is stopped 1 PF0 output pin Both of them are stopped X MDIO input/output pin
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8.3
Change of Peripheral Function Pins
The pin function assignments for the external interrupt inputs and 14-bit PWM timer outputs can be changed between multiplexed I/O ports. I/O port pins for external interrupt inputs are changed by the setting of ISSR16 and ISSR. I/O port pins for 14-bit PWM timer outputs are changed by the setting of PTCNT0. A pin name of the peripheral function after the assignment has been changed is indicated by adding `Ex' at the head of the original pin name. In each peripheral function description, the original pin name is used. 8.3.1 IRQ Sense Port Select Register 16 (ISSR16), IRQ Sense Port Select Register (ISSR)
ISSR16 and ISSR select pins for the IRQ15 to IRQ0 inputs. * ISSR16
Bit 15 14 13 12 11 10 9 8 Bit Name ISS15 ISS14 ISS13 ISS12 ISS11 ISS10 ISS9 ISS8 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description 0: P61/IRQ15 is selected 1: P87/ExIRQ15 is selected 0: P60/IRQ14 is selected 1: P86/ExIRQ14 is selected 0: P55/IRQ13 is selected 1: P85/ExIRQ13 is selected 0: P54/IRQ12 is selected 1: P84/ExIRQ12 is selected 0: P53/IRQ11 is selected 1: P64/ExIRQ11 is selected 0: P52/IRQ10 is selected 1: P65/ExIRQ10 is selected 0: P51/IRQ9 is selected 1: P66/ExIRQ9 is selected 0: P50/IRQ8 is selected 1: P67/ExIRQ8 is selected
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Section 8 I/O Ports
* ISSR
Bit 7 6 5 4 3 2 1 0 Bit Name ISS7 ISS6 ISS5 ISS4 ISS3 ISS2 ISS1 ISS0 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description 0: P47/IRQ7 is selected 1: PA7/ExIRQ7 is selected 0: P46/IRQ6 is selected 1: PA6/ExIRQ6 is selected 0: P45/IRQ5 is selected 1: PA5/ExIRQ5 is selected 0: P44/IRQ4 is selected 1: PA4/ExIRQ4 is selected 0: P43/IRQ3 is selected 1: PA3/ExIRQ3 is selected 0: P42/IRQ2 is selected 1: PA2/ExIRQ2 is selected 0: P41/IRQ1 is selected 1: PA1/ExIRQ1 is selected 0: P40/IRQ0 is selected 1: PA0/ExIRQ0 is selected
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Section 8 I/O Ports
8.3.2
Port Control Register 0 (PTCNT0)
PTCNT0 selects pins for 14-bit PWM timer outputs and the control mode for external extension.
Bit 7 Bit Name Initial Value R/W R/W Description Controls the internal connection of TxD1 and RxD1 with the SCI_1 as the smart card interface. 0: TxD1 and RxD1 are not internally connected. 1: TxD1 and RxD1 are internally connected. 6 SCPFSEL3 0 R/W Controls the internal connection of TxD3 and RxD3 with the SCI_3 as the smart card interface. 0: TxD3 and RxD3 are not internally connected. 1: TxD3 and RxD3 are internally connected. 5, 4 3 PWMXS All 0 0 R/W R/W Reserved The initial value should not be changed. Selects pins for 14-bit PWM timer outputs. 0: P60/PWX0, P61/PWX1, P62/PWX2, P63/PWX3 are selected 1: P93/ExPWX0, P94/ExPWX1, PF6/ExPWX2, PF3/ExPWX3* are selected 2 1 OBE 0 0 R/W R/W Reserved The initial value should not be changed. Selects glueless extension. 0: Control by RD, HWR, LWR 1: Control by RD, WR, HBE, LBE (glueless extension) 0 0 R/W Reserved The initial value should not be changed. Note: * The PF3/EXPWX3 pin is available only in the H8S/2472 Group.
SCPFSEL1 0
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Section 9 14-Bit PWM Timer (PWMX)
Section 9 14-Bit PWM Timer (PWMX)
This LSI has an on-chip 14-bit pulse-width modulator (PWM) timer with four output channels. It can be connected to an external low-pass filter to operate as a 14-bit D/A converter.
9.1
Features
* Division of pulse into multiple base cycles to reduce ripple * Eight resolution settings The resolution can be set to 1, 2, 64, 128, 256, 1024, 4096, or 16384 system clock cycles. * Two base cycle settings The base cycle can be set equal to T x 64 or T x 256, where T is the resolution. * Sixteen operation clocks (by combination of eight resolution settings and two base cycle settings) Figure 9.1 shows a block diagram of the PWM (D/A) module.
Internal clock /2, /64, /128, /256, /1024, /4096, /16384 Clock Base cycle compare match A PWX0 PWX1
Fine-adjustment pulse addition A
Internal data bus
Select clock
Bus interface
Comparator A Comparator B
DADRA DADRB
Base cycle compare match B
Fine-adjustment pulse addition B
Control logic Base cycle overflow DACNT
DACR Module data bus PWMX D/A control register (6 bits) PWMX D/A data register A (15 bits) PWMX D/A data register B (15 bits) PWMX D/A counter (14 bits)
[Legend] DACR: DADRA: DADRB: DACNT:
Figure 9.1 PWMX (D/A) Block Diagram
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Section 9 14-Bit PWM Timer (PWMX)
9.2
Input/Output Pins
Table 9.1 lists the PWMX (D/A) module input and output pins. Table 9.1
Name PWMX output pin 0 PWMX output pin 1 PWMX output pin 2 PWMX output pin 3
Pin Configuration
Abbreviation I/O PWX0 PWX1 PWX2 PWX3 Output Output Output Output Function PWM timer pulse output of PWMX_0 channel A PWM timer pulse output of PWMX_0 channel B PWM timer pulse output of PWMX_1 channel A PWM timer pulse output of PWMX_1 channel B
9.3
Register Descriptions
The PWMX (D/A) module has the following registers. For details on the module stop control register, see section 28.1.3, Module Stop Control Registers H, L, and A (MSTPCRH, MSTPCRL, MSTPCRA). * PWMX (D/A) counter (DACNT) * PWMX (D/A) data register A (DADRA) * PWMX (D/A) data register B (DADRB) * PWMX (D/A) control register (DACR) * Peripheral clock select register (PCSR) Note: The same addresses are shared by DADRA and DACR, and by DADRB and DACNT. Switching is performed by the REGS bit in DACNT or DADRB.
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Section 9 14-Bit PWM Timer (PWMX)
9.3.1
PWMX (D/A) Counter (DACNT)
DACNT is a 14-bit readable/writable up-counter. The input clock is selected by the clock select bit (CKS) in DACR. DACNT functions as the time base for both PWMX (D/A) channels. When a channel operates with 14-bit precision, it uses all DACNT bits. When a channel operates with 12bit precision, it uses the lower 12 bits and ignores the upper two bits. DACNT cannot be accessed in 8-bit units. DACNT should always be accessed in 16-bit units. For details, see section 9.4, Bus Master Interface. * DACNT
Bit Bit Name Initial Value All 0 All 0 1 1 R/W R/W R/W R R/W Description Lower Up-Counter Upper Up-Counter Reserved This bit is always read as 1 and cannot be modified. 0 REGS Register Select DADRA and DACR, and DADRB and DACNT, are located at the same addresses. The REGS bit specifies which registers can be accessed. When changing the register to be accessed, set this bit in advance. 0: DADRA and DADRB can be accessed 1: DACR and DACNT can be accessed
15 to 8 UC7 to UC0 7 to 2 1 UC8 to UC13
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Section 9 14-Bit PWM Timer (PWMX)
9.3.2
PWMX (D/A) Data Registers A and B (DADRA and DADRB)
DADRA corresponds to PWMX (D/A) channel A, and DADRB to PWMX (D/A) channel B. The DADR registers cannot be accessed in 8-bit units. The DADR registers should always be accessed in 16-bit units. For details, see section 9.4, Bus Master Interface. * DADRA
Bit Bit Name Initial Value R/W R/W Description D/A Data 13 to 0 These bits set a digital value to be converted to an analog value. In each base cycle, the DACNT value is continually compared with the DADR value to determine the duty cycle of the output waveform, and to decide whether to output a fine-adjustment pulse equal in width to the resolution. To enable this operation, this register must be set within a range that depends on the CFS bit. If the DADR value is outside this range, the PWM output is held constant. A channel can be operated with 12-bit precision by fixing DA0 and DA1 to 0. The two data bits are not compared with UC12 and UC13 of DACNT. 1 CFS 1 R/W Carrier Frequency Select 0: Base cycle = resolution (T) x 64 The range of DA13 to DA0: H'0100 to H'3FFF 1: Base cycle = resolution (T) x 256 The range of DA13 to DA0: H'0040 to H'3FFF 0 1 R Reserved This bit is always read as 1 and cannot be modified.
15 to 2 DA13 to DA0 All 1
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Section 9 14-Bit PWM Timer (PWMX)
* DADRB
Bit Bit Name Initial Value R/W R/W Description D/A Data 13 to 0 These bits set a digital value to be converted to an analog value. In each base cycle, the DACNT value is continually compared with the DADR value to determine the duty cycle of the output waveform, and to decide whether to output a fine-adjustment pulse equal in width to the resolution. To enable this operation, this register must be set within a range that depends on the CFS bit. If the DADR value is outside this range, the PWM output is held constant. A channel can be operated with 12-bit precision by fixing DA0 and DA1 to 0. The two data bits are not compared with UC12 and UC13 of DACNT. 1 CFS 1 R/W Carrier Frequency Select 0: Base cycle = resolution (T) x 64 DA13 to DA0 range = H'0100 to H'3FFF 1: Base cycle = resolution (T) x 256 DA13 to DA0 range = H'0040 to H'3FFF 0 REGS 1 R/W Register Select DADRA and DACR, and DADRB and DACNT, are located at the same addresses. The REGS bit specifies which registers can be accessed. When changing the register to be accessed, set this bit in advance. 0: DADRA and DADRB can be accessed 1: DACR and DACNT can be accessed
15 to 2 DA13 to DA0 All 1
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Section 9 14-Bit PWM Timer (PWMX)
9.3.3
PWMX (D/A) Control Register (DACR)
DACR enables the PWM outputs, and selects the output phase and operating speed.
Bit 7 6 Bit Name PWME Initial Value 0 0 R/W R/W R/W Description Reserved The initial value should not be changed. PWMX Enable Starts or stops the PWM D/A counter (DACNT). 0: DACNT operates as a 14-bit up-counter 1: DACNT halts at H'0003 5, 4 3 OEB All 1 0 R R/W Reserved These bits are always read as 1 and cannot be modified. Output Enable B Enables or disables output on PWMX (D/A) channel B. 0: PWMX (D/A) channel B output (at the PWX1, PWX3 pins) is disabled 1: PWMX (D/A) channel B output (at the PWX1, PWX3 pins) is enabled 2 OEA 0 R/W Output Enable A Enables or disables output on PWMX (D/A) channel A. 0: PWMX (D/A) channel A output (at the PWX0, PWX2 pin) is disabled 1: PWMX (D/A) channel A output (at the PWX0, PWX2 pins) is enabled 1 OS 0 R/W Output Select Selects the phase of the PWMX (D/A) output. 0: Direct PWMX (D/A) output 1: Inverted PWMX (D/A) output 0 CKS 0 R/W Clock Select Selects the PWMX (D/A) resolution. Eight kinds of resolution can be selected. 0: Operates at resolution (T) = system clock cycle time (tcyc) 1: Operates at resolution (T) = system clock cycle time (tcyc) x 2, x 64, x 128, x 256, x 1024, x 4096, and x 16384.
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Section 9 14-Bit PWM Timer (PWMX)
9.3.4
Peripheral Clock Select Register (PCSR)
PCSR and the CKS bit of DACR select the operating speed.
Bit 7 6 Bit Name PWCKX1B PWCKX1A Initial Value 0 0 R/W R/W R/W Description PWMX_1 Clock Select These bits select a clock cycle with the CKS bit of DACR of PWMX_1 being 1. See table 9.2. 5 4 PWCKX0B PWCKX0A 0 0 R/W R/W PWMX_0 Clock Select These bits select a clock cycle with the CKS bit of DACR of PWMX_0 being 1. See table 9.2. 3 PWCKX1C 0 R/W PWMX_1 Clock Select This bit selects a clock cycle with the CKS bit of DACR of PWMX_1 being 1. See table 9.2. 2 1 0 PWCKX0C 0 0 0 R/W R/W R/W Reserved The initial value should not be changed. PWMX_0 Clock Select This bit selects a clock cycle with the CKS bit of DACR of PWMX_0 being 1. See table 9.2.
Table 9.2
PWCKX0C PWCKX1C 0 0 0 0 1 1 1 1
Clock Select of PWMX_1 and PWMX_0
PWCKX0B PWCKX1B 0 0 1 1 0 0 1 1 PWCKX0A PWCKX1A 0 1 0 1 0 1 0 1 Resolution (T) Operates on the system clock cycle (tcyc) x 2 Operates on the system clock cycle (tcyc) x 64 Operates on the system clock cycle (tcyc) x 128 Operates on the system clock cycle (tcyc) x 256 Operates on the system clock cycle (tcyc) x 1024 Operates on the system clock cycle (tcyc) x 4096 Operates on the system clock cycle (tcyc) x 16384 Setting prohibited
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Section 9 14-Bit PWM Timer (PWMX)
9.4
Bus Master Interface
DACNT, DADRA, and DADRB are 16-bit registers. The data bus linking the bus master and the on-chip peripheral modules, however, is only 8 bits wide. When the bus master accesses these registers, it therefore uses an 8-bit temporary register (TEMP). These registers are written to and read from as follows. * Write When the upper byte is written to, the upper-byte write data is stored in TEMP. Next, when the lower byte is written to, the lower-byte write data and TEMP value are combined, and the combined 16-bit value is written in the register. * Read When the upper byte is read from, the upper-byte value is transferred to the CPU and the lower-byte value is transferred to TEMP. Next, when the lower byte is read from, the lowerbyte value in TEMP is transferred to the CPU. These registers should always be accessed 16 bits at a time with a MOV instruction, and the upper byte should always be accessed before the lower byte. Correct data will not be transferred if only the upper byte or only the lower byte is accessed. Also note that a bit manipulation instruction cannot be used to access these registers. Example 1: Write to DACNT
MOV.W R0, @DACNT ; Write R0 contents to DACNT
Example 2: Read DADRA
MOV.W @DADRA, R0 ; Copy contents of DADRA to R0
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Section 9 14-Bit PWM Timer (PWMX)
9.5
Operation
A PWM waveform like the one shown in figure 9.2 is output from the PWX pin. DA13 to DA0 in DADR corresponds to the total width (TL) of the low (0) pulses output in one conversion cycle (256 pulses when CFS = 0, 64 pulses when CFS = 1). When OS = 0, this waveform is directly output. When OS = 1, the output waveform is inverted, and DA13 to DA0 in DADR value corresponds to the total width (TH) of the high (1) output pulses. Figures 9.3 and 9.4 show the types of waveform output available.
1 conversion cycle (T x 214 (= 16384)) tf Base cycle (T x 64 or T x 256)
tL
T: Resolution TL = tLn (OS = 0)
n=1 m
(When CFS = 0, m = 256 When CFS = 1, m = 64)
Figure 9.2 PWMX (D/A) Operation Table 9.3 summarizes the relationships between the CKS and CFS bit settings and the resolution, base cycle, and conversion cycle. The PWM output remains fixed unless DA13 to DA0 in DADR contain at least a certain minimum value. The relationship between the OS bit and the output waveform is shown in figures 9.3 and 9.4.
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Section 9 14-Bit PWM Timer (PWMX)
Table 9.3
PCSR PWCKX0 PWCKX1 C B A
Settings and Operation (Examples when = 34 MHz)
Fixed DADR Bits Resolution T CKS (s) 0 0.03 () Base CFS Cycle 0 1.88 s 531.3 kHz Conversion Cycle TL/TH (OS = 0/OS = 1) Precision DA3 DA2 DA1 (Bits) 14 12 10 14 12 10 14 12 10 14 12 10 14 12 10 14 12 10 14 12 10 14 12 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DA0 Bit Data Conversion Cycle* 481.88 s 120.47 s 30.12 s 481.88 s 120.47 s 30.12 s 0.964 ms 0.241 ms 0.060 ms 0.964 ms 0.241 ms 0.060 ms 30.840 ms 7.710 ms 1.928 ms 30.840 ms 7.710 ms 1.928 ms 61.681 ms 15.420 ms 3.855 ms 61.681 ms 15.420 ms 3.855 ms
481.88 s Always low/high output DA13 to 0 = H'0000 to H'00FF (Data value) x T DA13 to 0 = H'0100 to H'3FFF
1
7.53 s 132.8 kHz
481.88 s Always low/high output DA13 to 0 = H'0000 to H'003F (Data value) x T DA13 to 0 = H'0040 to H'3FFF
0
0
0
1
0.06 (/2)
0
3.76 s 265.6 kHz
0.964 ms
Always low/high output DA13 to 0 = H'0000 to H'00FF (Data value) x T DA13 to 0 = H'0100 to H'3FFF
1
15.06 s 66.4 kHz
0.964 ms
Always low/high output DA13 to 0 = H'0000 to H'003F (Data value) x T DA13 to 0 = H'0040 to H'3FFF
0
0
1
1
1.88 (/64)
0
120.5 s 8.3 kHz
30.840 ms Always low/high output DA13 to 0 = H'0000 to H'00FF (Data value) x T DA13 to 0 = H'0100 to H'3FFF
1
481.9 s 2.1 kHz
30.840 ms Always low/high output DA13 to 0 = H'0000 to H'003F (Data value) x T DA13 to 0 = H'0040 to H'3FFF
0
1
0
1
3.76 (/128)
0
240.9 s 4.2 kHz
61.681 ms Always low/high output DA13 to 0 = H'0000 to H'00FF (Data value) x T DA13 to 0 = H'0100 to H'3FFF
1
963.8 s 1.0 kHz
61.681 ms Always low/high output DA13 to 0 = H'0000 to H'003F (Data value) x T DA13 to 0 = H'0040 to H'3FFF
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Section 9 14-Bit PWM Timer (PWMX)
PCSR PWCKX0 PWCKX1 C 0 B 1 A 1 Resolution T CKS (s) 1 7.53 (/256) Base CFS Cycle 0 481.9 s 2.1 kHz Conversion Cycle TL/TH (OS = 0/OS = 1)
Fixed DADR Bits
Bit Data Precision DA3 DA2 DA1 (Bits) 14 12 10 14 12 10 14 12 10 14 12 10 14 12 10 14 12 10 14 12 10 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DA0 0 0
Conversion Cycle* 123.36 ms 30.84 ms 7.71 ms 123.36 ms 30.84 ms 7.71 ms 493.45 ms 123.36 ms 30.84 ms 493.45 ms 123.36 ms 30.84 ms 1.974 s 0.493 s 0.123 s 1.974 s 0.493 s 0.123 s 7.895 s 1.974 s 0.493 s 7.895 s
123.36 ms Always low/high output DA13 to 0 = H'0000 to H'00FF (Data value) x T DA13 to 0 = H'0100 to H'3FFF
1
1927.5 s 123.36 ms Always low/high output 0.5 kHz DA13 to 0 = H'0000 to H'003F (Data value) x T DA13 to 0 = H'0040 to H'3FFF
1
0
0
1
30.12 (/1024)
0
1.93 ms 518.8 Hz
493.45 ms Always low/high output DA13 to 0 = H'0000 to H'00FF (Data value) x T DA13 to 0 = H'0100 to H'3FFF
1
7.71 ms 129.7 Hz
493.45 ms Always low/high output DA13 to 0 = H'0000 to H'003F (Data value) x T DA13 to 0 = H'0040 to H'3FFF
1
0
1
1
120.47 (/4096)
0
7.71 ms 129.7 Hz
1.974 s
Always low/high output DA13 to 0 = H'0000 to H'00FF (Data value) x T DA13 to 0 = H'0100 to H'3FFF
1
30.84 ms 1.974 s 32.4 Hz
Always low/high output DA13 to 0 = H'0000 to H'003F (Data value) x T DA13 to 0 = H'0040 to H'3FFF
1
1
0
1
481.88 (/16384)
0
30.84 ms 7.895 s 32.4 Hz
Always low/high output DA13 to 0 = H'0000 to H'00FF (Data value) x T DA13 to 0 = H'0100 to H'3FFF
1
123.36 ms 8.1 Hz
7.895 s
Always low/high output DA13 to 0 = H'0000 to H'003F (Data value) x T DA13 to 0 = H'0040 to H'3FFF
12 10 0 0
0 0
1.974 s 0.493 s
1
1
1
1
Setting prohibited

Note:
*
Indicates the conversion cycle when specific DA3 to DA0 bits are fixed.
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Section 9 14-Bit PWM Timer (PWMX)
1 conversion cycle tf1 tf2 tf255 tf256
tL1
tL2
tL3
tL255
tL256
tf1 = tf2 = tf3 = *** = tf255 = tf256 = Tx 64 tL1 + tL2 + tL3+ *** + tL255 + tL256 = TL a. CFS = 0 [base cycle = resolution (T) x 64]
1 conversion cycle tf1 tf2 tf63 tf64
tL1
tL2
tL3
tL63
tL64
tf1 = tf2 = tf3 = *** = tf63 = tf64 = Tx 256 tL1 + tL2 + tL3 + *** + tL63 + tL64 = TL b. CFS = 1 [base cycle = resolution (T) x 256]
Figure 9.3 Output Waveform (OS = 0, DADR corresponds to TL)
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Section 9 14-Bit PWM Timer (PWMX)
1 conversion cycle tf1 tf2 tf255 tf256
tH1
tH2
tH3
tH255
tH256
tf1 = tf2 = tf3 = *** = tf255 = tf256 = Tx 64 tH1 + tH2 + tH3 + *** + tH255 + tH256 = TH a. CFS = 0 [base cycle = resolution (T) x 64]
1 conversion cycle tf1 tf2 tf63 tf64
tH1
tH2
tH3
tH63
tH64
tf1 = tf2 = tf3 = *** = tf63 = tf64 = Tx 256 tH1 + tH2 + tH3 + *** + tH63 + tH64 = TH b. CFS = 1 [base cycle = resolution (T) x 256]
Figure 9.4 Output Waveform (OS = 1, DADR corresponds to TH) An example of the additional pulses when CFS = 1 (base cycle = resolution (T) x 256) and OS = 1 (inverted PWM output) is described below. When CFS = 1, the upper eight bits (DA13 to DA6) in DADR determine the duty cycle of the base pulse while the subsequent six bits (DA5 to DA0) determine the locations of the additional pulses as shown in figure 9.5. Table 9.4 lists the locations of the additional pulses.
DA13 DA12 DA11 DA10 DA9
DA8
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
CFS 1 1
Duty cycle of base pulse
Location of additional pulses
Figure 9.5 D/A Data Register Configuration when CFS = 1 In this example, DADR = H'0207 (B'0000 0010 0000 0111). The output waveform is shown in figure 9.6. Since CFS = 1 and the value of the upper eight bits is B'0000 0010, the high width of the base pulse duty cycle is 2/256 x (T).
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Section 9 14-Bit PWM Timer (PWMX)
Since the value of the subsequent six bits is B'0000 01, an additional pulse is output only at the location of base pulse No. 63 according to table 9.4. Thus, an additional pulse of 1/256 x (T) is to be added to the base pulse.
1 conversion cycle Base cycle No. 0 Base cycle No. 1 Base cycle No. 63
Base pulse High width: 2/256 x (T) Base pulse 2/256 x (T)
Additional pulse output location Additional pulse 1/256 x (T)
Figure 9.6 Output Waveform when DADR = H'0207 (OS = 1) However, when CFS = 0 (base cycle = resolution (T) x 64), the duty cycle of the base pulse is determined by the upper six bits and the locations of the additional pulses by the subsequent eight bits with a method similar to as above.
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Table 9.4
0
Base pulse No. 12345 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
6
7
Locations of Additional Pulses Added to Base Pulse (When CFS = 1)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Lower 6 bits 0000 0000 0001 0001 0010 0010 0011 0011 0100 0100 0101 0101 0110 0110 0111 0111 1000 1000 1001 1001 1010 1010 1011 1011 1100 1100 1101 1101 1110 1110 1111 1111 0000 0000 0001 0001 0010 0010 0011 0011 0100 0100 0101 0101 0110 0110 0111 0111 1000 1000 1001 1001 1010 1010 1011 1011 1100 1100 1101 1101 1110 1110 1111 1111
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
Section 9 14-Bit PWM Timer (PWMX)
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REJ09B0403-0200
Section 9 14-Bit PWM Timer (PWMX)
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Section 10 16-Bit Free-Running Timer (FRT)
Section 10 16-Bit Free-Running Timer (FRT)
This LSI has a 16-bit free-running timer (FRT).
10.1
Features
* Selection of four clock sources One of the three internal clocks (/2, /8, or /32) can be selected. * Two independent comparators * Counter clearing The free-running counters can be cleared on compare-match A. * Three independent interrupts Two compare-match interrupts and one overflow interrupt can be requested independently. * Special functions provided by automatic addition function The contents of OCRAR and OCRAF can be added to the contents of OCRA automatically, enabling a periodic waveform to be generated without software intervention.
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Section 10 16-Bit Free-Running Timer (FRT)
Figure 10.1 is a block diagram of the FRT.
Internal clock
/2 /8 /32 Clock selector
Clock
OCRAR/F
OCRA
Compare-match A Overflow
Comparator A
Module data bus Bus interface
Internal data bus
FRC
Clear Compare-match B
Comparator B
Control logic
OCRB
TCSR TIER TCR TOCR
OCIA OCIB FOVI
Interrupt signal
[Legend] OCRA, OCRB: OCRAR,OCRAF: FRC: TCSR: TIER: TCR: TOCR: Output compare registers A and B (16 bits) Output compare registers AR and AF (16 bits) Free-running counter (16 bits) Timer control/status register (8 bits) Timer interrupt enable register (8 bits) Timer control register (8 bits) Timer output compare control register (8 bits)
Figure 10.1 Block Diagram of 16-Bit Free-Running Timer
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Section 10 16-Bit Free-Running Timer (FRT)
10.2
Register Descriptions
The FRT has the following registers. * Free-running counter (FRC) * Output compare register A (OCRA) * Output compare register B (OCRB) * Output compare register AR (OCRAR) * Output compare register AF (OCRAF) * Timer interrupt enable register (TIER) * Timer control/status register (TCSR) * Timer control register (TCR) * Timer output compare control register (TOCR) Note: OCRA and OCRB share the same address. Register selection is controlled by the OCRS bit in TOCR. 10.2.1 Free-Running Counter (FRC)
FRC is a 16-bit readable/writable up-counter. The clock source is selected by bits CKS1 and CKS0 in TCR. FRC can be cleared by compare-match A. When FRC overflows from H'FFFF to H'0000, the overflow flag bit (OVF) in TCSR is set to 1. FRC should always be accessed in 16-bit units; cannot be accessed in 8-bit units. FRC is initialized to H'0000. 10.2.2 Output Compare Registers A and B (OCRA and OCRB)
The FRT has two output compare registers, OCRA and OCRB, each of which is a 16-bit readable/writable register whose contents are continually compared with the value in FRC. When a match is detected (compare-match), the corresponding output compare flag (OCFA or OCFB) is set to 1 in TCSR. OCR should always be accessed in 16-bit units; cannot be accessed in 8-bit units. OCR is initialized to H'FFFF.
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Section 10 16-Bit Free-Running Timer (FRT)
10.2.3
Output Compare Registers AR and AF (OCRAR and OCRAF)
OCRAR and OCRAF are 16-bit readable/writable registers. They are accessed when the ICRS bit in TOCR is set to 1. When the OCRAMS bit in TOCR is set to 1, the operation of OCRA is changed to include the use of OCRAR and OCRAF. The contents of OCRAR and OCRAF are automatically added alternately to OCRA, and the result is written to OCRA. The write operation is performed on the occurrence of compare-match A. In the 1st compare-match A after setting the OCRAMS bit to 1, OCRAF is added. The operation due to compare-match A varies according to whether the compare-match follows addition of OCRAR or OCRAF. When using the OCRA automatic addition function, do not select internal clock /2 as the FRC input clock together with a set value of H'0001 or less for OCRAR (or OCRAF). OCRAR and OCRAF should always be accessed in 16-bit units; cannot be accessed in 8-bit units. OCRAR and OCRAF are initialized to H'FFFF.
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Section 10 16-Bit Free-Running Timer (FRT)
10.2.4
Timer Interrupt Enable Register (TIER)
TIER enables and disables interrupt requests.
Bit 7 to 4 3 Bit Name OCIAE Initial Value All 0 0 R/W R R/W Description Reserved These bits are always read as 0 and cannot be modified. Output Compare Interrupt A Enable Selects whether to enable output compare interrupt A request (OCIA) when output compare flag A (OCFA) in TCSR is set to 1. 0: OCIA requested by OCFA is disabled 1: OCIA requested by OCFA is enabled 2 OCIBE 0 R/W Output Compare Interrupt B Enable Selects whether to enable output compare interrupt B request (OCIB) when output compare flag B (OCFB) in TCSR is set to 1. 0: OCIB requested by OCFB is disabled 1: OCIB requested by OCFB is enabled 1 OVIE 0 R/W Timer Overflow Interrupt Enable Selects whether to enable a free-running timer overflow request interrupt (FOVI) when the timer overflow flag (OVF) in TCSR is set to 1. 0: FOVI requested by OVF is disabled 1: FOVI requested by OVF is enabled 0 0 R Reserved This bit is always read as 0 and cannot be modified.
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Section 10 16-Bit Free-Running Timer (FRT)
10.2.5
Timer Control/Status Register (TCSR)
TCSR is used for counter clear selection and control of interrupt request signals.
Bit 7 to 4 3 Bit Name OCFA Initial Value All 0 0 R/W R Description Reserved These bits are always read as 0 and cannot be modified. R/(W)* Output Compare Flag A Indicates that the FRC value matches the OCRA value. [Setting condition] When FRC = OCRA [Clearing condition] Read OCFA when OCFA = 1, then write 0 to OCFA 2 OCFB 0 R/(W)* Output Compare Flag B Indicates that the FRC value matches the OCRB value. [Setting condition] When FRC = OCRB [Clearing condition] Read OCFB when OCFB = 1, then write 0 to OCFB 1 OVF 0 R/(W)* Overflow Flag Indicates that the FRC has overflowed. [Setting condition] When FRC overflows (changes from H'FFFF to H'0000) [Clearing condition] Read OVF when OVF = 1, then write 0 to OVF 0 CCLRA 0 R/W Counter Clear A Selects whether the FRC is to be cleared on comparematch A (when the FRC and OCRA values match). 0: FRC clearing is disabled 1: FRC is cleared on compare-match A Note: * Only 0 can be written to clear the flag.
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Section 10 16-Bit Free-Running Timer (FRT)
10.2.6
Timer Control Register (TCR)
TCR selects the rising or falling edge of the input capture signals, enables the input capture buffer mode, and selects the FRC clock source.
Bit 7 to 2 1 0 Bit Name CKS1 CKS0 Initial Value All 0 0 0 R/W R R/W R/W Description Reserved These bits are always read as 0 and cannot be modified. Clock Select 1 and 0 Select clock source for FRC. 00: /2 internal clock source 01: /8 internal clock source 10: /32 internal clock source 11: Reserved
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Section 10 16-Bit Free-Running Timer (FRT)
10.2.7
Timer Output Compare Control Register (TOCR)
TOCR enables output from the output compare pins, selects the output levels, switches access between output compare registers A and B, and controls the OCRA operating modes.
Bit 7 6 Bit Name OCRAMS Initial Value 0 0 R/W R R/W Description Reserved This bit is always read as 0 and cannot be modified. Output Compare A Mode Select Specifies whether OCRA is used in the normal operating mode or in the operating mode using OCRAR and OCRAF. 0: The normal operating mode is specified for OCRA 1: The operating mode using OCRAR and OCRAF is specified for OCRA 5 ICRS 0 R/W Input Capture Register Select Controls the access to OCRAR and OCRAF. 0: Access is disabled 1: Access is enabled 4 OCRS 0 R/W Output Compare Register Select OCRA and OCRB share the same address. When this address is accessed, the OCRS bit selects which register is accessed. The operation of OCRA or OCRB is not affected. 0: OCRA is selected 1: OCRB is selected 3 to 0 All 0 R Reserved These bits are always read as 0 and cannot be modified.
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Section 10 16-Bit Free-Running Timer (FRT)
10.3
10.3.1
Operation Timing
FRC Increment Timing
Figure 10.2 shows the FRC increment timing with an internal clock source.
Internal clock
FRC input clock
FRC
N-1
N
N+1
Figure 10.2 Increment Timing with Internal Clock Source 10.3.2 Output Compare Output Timing
A compare-match signal occurs at the last state when the FRC and OCR values match (at the timing when the FRC updates the counter value). Figure 10.3 shows the timing of this operation for compare-match A.
FRC
N
N+1
N
N+1
OCRA
N
N
Compare-match A signal
Figure 10.3 Timing of Output Compare A Output
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Section 10 16-Bit Free-Running Timer (FRT)
10.3.3
FRC Clear Timing
FRC can be cleared when compare-match A occurs. Figure 10.4 shows the timing of this operation.
Compare-match A signal
FRC
N
H'0000
Figure 10.4 Clearing of FRC by Compare-Match A Signal 10.3.4 Timing of Output Compare Flag (OCF) Setting
The output compare flag, OCFA or OCFB, is set to 1 by a compare-match signal generated when the FRC value matches the OCRA or OCRB value. This compare-match signal is generated at the last state in which the two values match, just before FRC increments to a new value. When the FRC and OCRA or OCRB value match, the compare-match signal is not generated until the next cycle of the clock source. Figure 10.5 shows the timing of setting the OCFA or OCFB flag.
FRC
N
N+1
OCRA, OCRB
N
Compare-match signal
OCFA, OCFB
Figure 10.5 Timing of Output Compare Flag (OCFA or OCFB) Setting
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Section 10 16-Bit Free-Running Timer (FRT)
10.3.5
Timing of FRC Overflow Flag (OVF) Setting
The FRC overflow flag (OVF) is set to 1 when FRC overflows (changes from H'FFFF to H'0000). Figure 10.6 shows the timing of setting the OVF flag.
FRC
H'FFFF
H'0000
Overflow signal
OVF
Figure 10.6 Timing of Overflow Flag (OVF) Setting
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Section 10 16-Bit Free-Running Timer (FRT)
10.3.6
Automatic Addition Timing
When the OCRAMS bit in TOCR is set to 1, the contents of OCRAR and OCRAF are automatically added to OCRA alternately, and when an OCRA compare-match occurs, a write to OCRA is performed. Figure 10.7 shows the OCRA write timing.
FRC
N
N +1
OCRA
N
N+A
OCRAR, OCRAF
A
Compare-match signal
Figure 10.7 OCRA Automatic Addition Timing
10.4
Interrupt Sources
The free-running timer can request three interrupts: OCIA, OCIB, and FOVI. Each interrupt can be enabled or disabled by an enable bit in TIER. Independent signals are sent to the interrupt controller for each interrupt. Table 10.1 lists the sources and priorities of these interrupts. The OCIA and OCIB interrupts can be used as the on-chip DTC activation sources. Table 10.1 FRT Interrupt Sources
Interrupt OCIA OCIB FOVI Interrupt Source Compare match of OCRA Compare match of OCRB Overflow of FRC Interrupt Flag OCFA OCFB OVF DTC Activation Possible Possible Not possible Low Priority High
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Section 10 16-Bit Free-Running Timer (FRT)
10.5
10.5.1
Usage Notes
Conflict between FRC Write and Clear
If an internal counter clear signal is generated during the state after an FRC write cycle, the clear signal takes priority and the write is not performed. Figure 10.8 shows the timing for this type of conflict.
Write cycle of FRC T1 T2
Address
FRC address
Internal write signal
Counter clear signal
FRC
N
H'0000
Figure 10.8 Conflict between FRC Write and Clear
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Section 10 16-Bit Free-Running Timer (FRT)
10.5.2
Conflict between FRC Write and Increment
If an FRC increment pulse is generated during the state after an FRC write cycle, the write takes priority and FRC is not incremented. Figure 10.9 shows the timing for this type of conflict.
Write cycle of FRC
T1
T2
Address
FRC address
Internal write signal
FRC input clock
FRC
N
M
Write data
Figure 10.9 Conflict between FRC Write and Increment
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Section 10 16-Bit Free-Running Timer (FRT)
10.5.3
Conflict between OCR Write and Compare-Match
If a compare-match occurs during the state after an OCRA or OCRB write cycle, the write takes priority and the compare-match signal is disabled. Figure 10.10 shows the timing for this type of conflict. If automatic addition of OCRAR and OCRAF to OCRA is selected, and a compare-match occurs in the cycle following the OCRA, OCRAR, and OCRAF write cycle, the OCRA, OCRAR and OCRAF write takes priority and the compare-match signal is disabled. Consequently, the result of the automatic addition is not written to OCRA. Figure 10.11 shows the timing of this type of conflict.
Write cycle of OCR
T1
T2
Address
OCR address
Internal write signal
FRC
N
N+1
OCR
N
M
Write data Compare-match signal Disabled
Figure 10.10 Conflict between OCR Write and Compare-Match (When Automatic Addition Function is Not Used)
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Section 10 16-Bit Free-Running Timer (FRT)
Address
OCRAR (OCRAF) address
Internal write signal
OCRAR (OCRAF)
Old data
New data
Compare-match signal
Disabled
FRC
N
N+1
OCR
N Automatic addition is not performed because compare-match signals are disabled.
Figure 10.11 Conflict between OCR Write and Compare-Match (When Automatic Addition Function is Used) 10.5.4 Switching of Internal Clock and FRC Operation
When the internal clock is changed, the changeover may source FRC to increment. This depends on the time at which the clock is switched (bits CKS1 and CKS0 are rewritten), as shown in table 10.2. When an internal clock is used, the FRC clock is generated on detection of the falling edge of the internal clock scaled from the system clock (). If the clock is changed when the old source is high and the new source is low, as in case no. 3 in table 10.2, the changeover is regarded as a falling edge that triggers the FRC clock, and FRC is incremented. Switching between an internal clock and external clock can also source FRC to increment.
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Section 10 16-Bit Free-Running Timer (FRT)
Table 10.2 Switching of Internal Clock and FRC Operation
Timing of Switchover by Means of CKS1 and CKS0 Bits Switching from low to low
No. 1
FRC Operation
Clock before switchover
Clock after switchover
FRC clock
FRC
N
N+1
CKS bit rewrite
2
Switching from low to high
Clock before switchover
Clock after switchover
FRC clock
FRC
N
N+1
N+2
CKS bit rewrite
3
Switching from high to low
Clock before switchover
Clock after switchover
*
FRC clock
FRC
N
N+1
N+2
CKS bit rewrite
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Section 10 16-Bit Free-Running Timer (FRT)
No. 4
Timing of Switchover by Means of CKS1 and CKS0 Bits Switching from high to high
FRC Operation
Clock before switchover
Clock after switchover
FRC clock
FRC
N
N+1
N+2
CKS bit rewrite
Note:
*
Generated because the switchover is assumed to take place on a falling edge, and FRC is incremented.
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Section 11 8-Bit Timer (TMR)
Section 11 8-Bit Timer (TMR)
This LSI has two channels of 8-bit timer modules (TMR_0 and TMR_1) which operate on the 8bit counter. This LSI also has two channels of similar 8-bit timer modules (TMR_Y and TMR_X).
11.1
Features
* Selection of clock sources TMR_0, TMR_1: The counter input clock can be selected from six internal clocks. TMR_Y, TMR_X: The counter input clock can be selected from three internal clocks. * Selection of two ways to clear the counters The counters can be cleared on compare-match A and compare-match B. * Cascading of TMR_0 and TMR_1 (Cascading of TMR_Y and TMR_X is not allowed) Operation as a 16-bit timer can be performed using TMR_0 as the upper half and TMR_1 as the lower half (16-bit count mode). TMR_1 can be used to count TMR_0 compare match occurrences (compare-match count mode). * Multiple interrupt sources for each channel TMR_0, TMR_1, TMR_Y and TMR_X: compare-match B, and overflow Three interrupts: Compare-match A,
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Section 11 8-Bit Timer (TMR)
Figures 11.1 and 11.2 are block diagrams of 8-bit timers.
Internal clock
TMR_0 /2, /8, /32, /64, /256, /1024
TMR_1 /2, /8, /64, /128, /1024, /2048
Clock 1 Clock 0
Select clock
TCORA_0
TCORA_1
Compare match A1 Compare match A0
Overflow 1 Overflow 0 Clear 0
Comparator A_0
Comparator A_1
Clear 1
Control logic Compare match B1 Compare match B0
Comparator B_0
Comparator B_1
TCORB_0
TCORB_1
TCSR_0
TCSR_1
TCR_0
Interrupt signals
TCR_1
CMIA0 CMIB0 OVI0 CMIA1 CMIB1 OVI1
[Legend] TCORA_0: TCORB_0: TCNT_0: TCSR_0: TCR_0: Time constant register A_0 Time constant register B_0 Timer counter_0 Timer control/status register_0 Timer control register_0 TCORA_1: TCORB_1: TCNT_1: TCSR_1: TCR_1: Time constant register A_1 Time constant register B_1 Timer counter_1 Timer control/status register_1 Timer control register_1
Figure 11.1 Block Diagram of 8-Bit Timer (TMR_0 and TMR_1)
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Internal bus
TCNT_0
TCNT_1
Section 11 8-Bit Timer (TMR)
Internal clock
TMR_X
, /2, /4
TMR_Y
/4, /256, /2048
Clock X Clock Y
Select clock
TCORA_Y
TCORA1_X
Compare match AX Compare match AY
Overflow X Overflow Y Clear Y
Comparator A_Y
Comparator A_X
TCNT_Y
TCNT_X
Clear X
Control logic
Compare match BX Compare match BY
Comparator B_Y
Comparator B_X
TCORB_Y
TCORB_X TCSR_X
TCR_X
TCOR_Y TCR_Y
Interrupt signals CMIAX CMIBX OVIX CMIAY CMIBY OVIY Time constant register A_Y Time constant register B_Y Timer counter_Y Timer control / status register_Y Timer control register_Y TCORA_X: TCORB_X: TCNT_X: TCSR_X: TCR_X: TCORC: Time constant register A_X Time constant register B_X Timer counter_X Timer control / status register_X Timer control register_X Tme constant registerC
[Legend] TCORA_Y: TCORB_Y: TCNT_Y: TCSR_Y: TCR_Y:
Figure 11.2 Block Diagram of 8-Bit Timer (TMR_Y and TMR_X)
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Internal bus
Section 11 8-Bit Timer (TMR)
11.2
Register Descriptions
The TMR has the following registers for each channel. For details on the serial timer control register, see section 3.2.3, Serial Timer Control Register (STCR). * Timer counter (TCNT) * Time constant register A (TCORA) * Time constant register B (TCORB) * Timer control register (TCR) * Timer control/status register (TCSR) * Timer connection register S (TCONRS)* Notes: Some of the registers of TMR_X and TMR_Y use the same address. The registers can be switched by the TMRX/Y bit in TCONRS. * TCONRS is only provided for TMR_X 11.2.1 Timer Counter (TCNT)
Each TCNT is an 8-bit readable/writable up-counter. TCNT_0 and TCNT_1 comprise a single 16bit register, so they can be accessed together by word access. The clock source is selected by the CKS2 to CKS0 bits in TCR. TCNT can be cleared by a compare-match A signal or comparematch B signal. The method of clearing can be selected by the CCLR1 and CCLR0 bits in TCR. When TCNT overflows (changes from H'FF to H'00), the OVF bit in TCSR is set to 1. TCNT is initialized to H'00. TCNT_Y can be accessed when the TMRX/Y bit in TCONRS is 1. TCNT_X can be accessed when the TMRX/Y bit in TCONRS is 0. See section 11.2.6, Timer Connection Register S (TCONRS).
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Section 11 8-Bit Timer (TMR)
11.2.2
Time Constant Register A (TCORA)
TCORA is an 8-bit readable/writable register. TCORA_0 and TCORA_1 comprise a single 16-bit register, so they can be accessed together by word access. TCORA is continually compared with the value in TCNT. When a match is detected, the corresponding compare-match flag A (CMFA) in TCSR is set to 1. However, comparison is disabled during the T2 state of a TCORA write cycle. TCORA is initialized to H'FF. TCORA_Y can be accessed when the TMRX/Y bit in TCONRS is 1. TCORA_X can be accessed when the TMRX/Y bit in TCONRS is 0. See section 11.2.6, Timer Connection Register S (TCONRS). 11.2.3 Time Constant Register B (TCORB)
TCORB is an 8-bit readable/writable register. TCORB_0 and TCORB_ 1 comprise a single 16-bit register, so they can be accessed together by word access. TCORB is continually compared with the value in TCNT. When a match is detected, the corresponding compare-match flag B (CMFB) in TCSR is set to 1. However, comparison is disabled during the T2 state of a TCORB write cycle. TCORB is initialized to H'FF. TCORB_Y can be accessed when the TMRX/Y bit in TCONRS is 1. TCORB_X can be accessed when the TMRX/Y bit in TCONRS is 0. See section 11.2.6, Timer Connection Register S (TCONRS).
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Section 11 8-Bit Timer (TMR)
11.2.4
Timer Control Register (TCR)
TCR selects the TCNT clock source and the condition by which TCNT is cleared, and enables/disables interrupt requests. TCR_Y can be accessed when the TMRX/Y bit in TCONRS is 1. TCR_X can be accessed when the TMRX/Y bit in TCONRS is 0. See section 11.2.6, Timer Connection Register S (TCONRS).
Bit 7 Bit Name CMIEB Initial Value 0 R/W R/W Description Compare-Match Interrupt Enable B Selects whether the CMFB interrupt request (CMIB) is enabled or disabled when the CMFB flag in TCSR is set to 1. 0: CMFB interrupt request (CMIB) is disabled 1: CMFB interrupt request (CMIB) is enabled 6 CMIEA 0 R/W Compare-Match Interrupt Enable A Selects whether the CMFA interrupt request (CMIA) is enabled or disabled when the CMFA flag in TCSR is set to 1. 0: CMFA interrupt request (CMIA) is disabled 1: CMFA interrupt request (CMIA) is enabled 5 OVIE 0 R/W Timer Overflow Interrupt Enable Selects whether the OVF interrupt request (OVI) is enabled or disabled when the OVF flag in TCSR is set to 1. 0: OVF interrupt request (OVI) is disabled 1: OVF interrupt request (OVI) is enabled 4 3 CCLR1 CCLR0 0 0 R/W R/W Counter Clear 1 and 0 Specify the clearing conditions of TCNT. 00: Counter clear is disabled 01: Counter clear is enabled on compare-match A 10: Counter clear is enabled on compare-match B 11: Setting prohibited 2 to 0 CKS2 to CKS0 All 0 R/W Clock Select 2 to 0 Select the clock input to TCNT and count condition, together with the ICKS1 and ICKS0 bits in STCR. For details, see table 11.1.
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Section 11 8-Bit Timer (TMR)
Table 11.1 (1)
TCR CKS2 0 0 0 0 0 0 0 1 1 1 Note: * CKS1 0 0 0 1 1 1 1 0 0 1
Clock Input to TCNT and Count Condition (TMR_0)
STCR CKS0 0 1 1 0 0 1 1 0 1 X ICKS0 X 0 1 0 1 0 1 X X X Description Disables clock input Increments at falling edge of internal clock /8 Increments at falling edge of internal clock /2 Increments at falling edge of internal clock /64 Increments at falling edge of internal clock /32 Increments at falling edge of internal clock /1024 Increments at falling edge of internal clock /256 Increments at overflow signal from TCNT_1* Setting prohibited Setting prohibited
If the TMR_0 clock input is set as the TCNT_1 overflow signal and the TMR_1 clock input is set as the TCNT_0 compare-match signal simultaneously, a count-up clock cannot be generated. Simultaneous setting of these conditions should be avoided. X: Don't care
[Legend]
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Section 11 8-Bit Timer (TMR)
Table 11.1 (2)
TCR CKS2 0 0 0 0 0 0 0 1 1 1 Note: * CKS1 0 0 0 1 1 1 1 0 0 1
Clock Input to TCNT and Count Condition (TMR_1)
STCR CKS0 0 1 1 0 0 1 1 0 1 X ICKS1 X 0 1 0 1 0 1 X X X Description Disables clock input Increments at falling edge of internal clock /8 Increments at falling edge of internal clock /2 Increments at falling edge of internal clock /64 Increments at falling edge of internal clock /128 Increments at falling edge of internal clock /1024 Increments at falling edge of internal clock /2048 Increments at compare-match A from TCNT_0* Setting prohibited Setting prohibited
[Legend]
If the TMR_0 clock input is set as the TCNT_1 overflow signal and the TMR_1 clock input is set as the TCNT_0 compare-match signal simultaneously, a count-up clock cannot be generated. Simultaneous setting of these conditions should be avoided. X: Don't care
Table 11.1 (3)
Clock Input to TCNT and Count Condition (TMR_X, TMR_Y)
TCR
Channel TMR_Y
CKS2 0 0 0 0 1
CKS1 0 0 1 1 X 0 0 1 1 X
CKS0 0 1 0 1 X 0 1 0 1 X
Description Disables clock input Increments at falling edge of internal clock /4 Increments at falling edge of internal clock /256 Increments at falling edge of internal clock /2048 Setting prohibited Disables clock input Increments at falling edge of internal clock Increments at falling edge of internal clock /2 Increments at falling edge of internal clock /4 Setting prohibited
TMR_Y
0 0 0 0 1
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Section 11 8-Bit Timer (TMR)
11.2.5
Timer Control/Status Register (TCSR)
TCSR indicates the status flags and controls compare-match output. See section 11.2.6, Timer Connection Register S (TCONRS) for details on the TCSR_Y and TCSR_X accesses. * TCSR_0
Bit 7 Bit Name CMFB Initial Value 0 R/W Description
R/(W)* Compare-Match Flag B [Setting condition] When the values of TCNT_0 and TCORB_0 match [Clearing condition] Read CMFB when CMFB = 1, then write 0 in CMFB
6
CMFA
0
R/(W)* Compare-Match Flag A [Setting condition] When the values of TCNT_0 and TCORA_0 match [Clearing condition] Read CMFA when CMFA = 1, then write 0 in CMFA
5
OVF
0
R/(W)* Timer Overflow Flag [Setting condition] When TCNT_0 overflows from H'FF to H00 [Clearing condition] Read OVF when OVF = 1, then write 0 in OVF
4
ADTE
0
R/W
A/D Trigger Enable Selects whether the A/D conversion start request on compare match A is enabled or disabled. 0: A/D conversion start request is disabled 1: A/D conversion start request is enabled
3 to 0 Note:
*
All 1
R
Reserved These bits are always read as 1 and cannot be modified.
Only 0 can be written to clear the flag.
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Section 11 8-Bit Timer (TMR)
* TCSR_1
Bit 7 Bit Name CMFB Initial Value 0 R/W Description
R/(W)* Compare-Match Flag B [Setting condition] When the values of TCNT_1 and TCORB_1 match [Clearing condition] Read CMFB when CMFB = 1, then write 0 in CMFB
6
CMFA
0
R/(W)* Compare-Match Flag A [Setting condition] When the values of TCNT_1 and TCORA_1 match [Clearing condition] Read CMFA when CMFA = 1, then write 0 in CMFA
5
OVF
0
R/(W)* Timer Overflow Flag [Setting condition] When TCNT_1 overflows from H'FF to H'00 [Clearing condition] Read OVF when OVF = 1, then write 0 in OVF
4 to 0 Note:
*
All 1
R
Reserved These bits are always read as 1 and cannot be modified.
Only 0 can be written to clear the flag.
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Section 11 8-Bit Timer (TMR)
* TCSR_Y This register can be accessed when the TMRX/Y bit in TCONRS is 1.
Bit 7 Bit Name CMFB Initial Value 0 R/W Description
R/(W)* Compare-Match Flag B [Setting condition] When the values of TCNT_Y and TCORB_Y match [Clearing condition] Read CMFB when CMFB = 1, then write 0 in CMFB
6
CMFA
0
R/(W)* Compare-Match Flag A [Setting condition] When the values of TCNT_Y and TCORA_Y match [Clearing condition] Read CMFA when CMFA = 1, then write 0 in CMFA
5
OVF
0
R/(W)* Timer Overflow Flag [Setting condition] When TCNT_Y overflows from H'FF to H'00 [Clearing condition] Read OVF when OVF = 1, then write 0 in OVF
4 to 0 Note:
*
All 1
R
Reserved These bits are always read as 1 and cannot be modified.
Only 0 can be written to clear the flag.
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Section 11 8-Bit Timer (TMR)
* TCSR_X This register can be accessed when the TMRX/Y bit in TCONRS is 0.
Bit 7 Bit Name CMFB Initial Value 0 R/W Description
R/(W)* Compare-Match Flag B [Setting condition] When the values of TCNT_X and TCORB_X match [Clearing condition] Read CMFB when CMFB = 1, then write 0 in CMFB
6
CMFA
0
R/(W)* Compare-Match Flag A [Setting condition] When the values of TCNT_X and TCORA_X match [Clearing condition] Read CMFA when CMFA = 1, then write 0 in CMFA
5
OVF
0
R/(W)* Timer Overflow Flag [Setting condition] When TCNT_X overflows from H'FF to H'00 [Clearing condition] Read OVF when OVF = 1, then write 0 in OVF
4 to 0 Note:
*
All 1
R
Reserved These bits are always read as 1 and cannot be modified.
Only 0 can be written to clear the flag.
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Section 11 8-Bit Timer (TMR)
11.2.6
Timer Connection Register S (TCONRS)
TCONRS selects whether to access TMR_X or TMR_Y registers.
Bit 7 Bit Name TMRX/Y Initial Value 0 R/W R/W Description TMR_X/TMR_Y Access Select For details, see table 11.2. 0: The TMR_X registers are accessed at addresses H'FFFFF0 to H'FFFFF5 1: The TMR_Y registers are accessed at addresses H'FFFFF0 to H'FFFFF5 6 to 0 All 0 R/W Reserved The initial values should not be changed.
Table 11.2 Registers Accessible by TMR_X/TMR_Y
TMRX/Y 0 H'FFFFF0 H'FFFFF1 H'FFFFF2 H'FFFFF3 H'FFFFF4 H'FFFFF5 H'FFFFF6 H'FFFFF7 TMR_X TCR_X 1 TMR_Y TCR_Y TMR_X TCSR_X TMR_Y TCSR_Y TMR_Y TMR_Y TMR_X TMR_X TMR_X TCNT_X TMR_Y TMR_Y TMR_X TMR_X TMR_X
TCORA_X TCORB_X
TCORA_Y TCORB_Y TCNT_Y
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Section 11 8-Bit Timer (TMR)
11.3
11.3.1
Operation Timing
TCNT Count Timing
Figure 11.3 shows the TCNT count timing with an internal clock source.
External clock input pin
TCNT input clock
TCNT
N-1
N
N+1
Figure 11.3 Count Timing for Internal Clock Input 11.3.2 Timing of CMFA and CMFB Setting at Compare-Match
The CMFA and CMFB flags in TCSR are set to 1 by a compare-match signal generated when the TCNT and TCOR values match. The compare-match signal is generated at the last state in which the match is true, just when the timer counter is updated. Therefore, when TCNT and TCOR match, the compare-match signal is not generated until the next TCNT input clock. Figure 11.4 shows the timing of CMF flag setting.
TCNT
N
N+1
TCOR Compare-match signal
N
CMF
Figure 11.4 Timing of CMF Setting at Compare-Match
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Section 11 8-Bit Timer (TMR)
11.3.3
Timing of Counter Clear at Compare-Match
TCNT is cleared when compare-match A or compare-match B occurs, depending on the setting of the CCLR1 and CCLR0 bits in TCR. Figure 11.5 shows the timing of clearing the counter by a compare-match.
Compare-match signal
TCNT
N
H'00
Figure 11.5 Timing of Counter Clear by Compare-Match 11.3.4 Timing of Overflow Flag (OVF) Setting
The OVF bit in TCSR is set to 1 when the TCNT overflows (changes from H'FF to H'00). Figure 11.6 shows the timing of OVF flag setting.
TCNT
H'FF
H'00
Overflow signal
OVF
Figure 11.6 Timing of OVF Flag Setting
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Section 11 8-Bit Timer (TMR)
11.4
TMR_0 and TMR_1 Cascaded Connection
If bits CKS2 to CKS0 in either TCR_0 or TCR_1 are set to B'100, the 8-bit timers of the two channels are cascaded. With this configuration, 16-bit count mode or compare-match count mode can be selected. 11.4.1 16-Bit Count Mode
When bits CKS2 to CKS0 in TCR_0 are set to B'100, the timer functions as a single 16-bit timer with TMR_0 occupying the upper eight bits and TMR_1 occupying the lower eight bits. * Setting of compare-match flags The CMF flag in TCSR_0 is set to 1 when a 16-bit compare-match occurs. The CMF flag in TCSR_1 is set to 1 when a lower 8-bit compare-match occurs. * Counter clear specification If the CCLR1 and CCLR0 bits in TCR_0 have been set for counter clear at compare-match, the 16-bit counter (TCNT_0 and TCNT_1 together) is cleared when a 16-bit comparematch occurs. The 16-bit counter (TCNT_0 and TCNT_1 together) is also cleared when counter clear by the TMI0 pin has been set. The settings of the CCLR1 and CCLR0 bits in TCR_1 are ignored. The lower 8 bits cannot be cleared independently. 11.4.2 Compare-Match Count Mode
When bits CKS2 to CKS0 in TCR_1 are B100, TCNT_1 counts the occurrence of compare-match A for TMR_0. TMR_0 and TMR_1 are controlled independently. Conditions such as setting of the CMF flag, generation of interrupts, and counter clearing are in accordance with the settings for each channel.
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Section 11 8-Bit Timer (TMR)
11.5
Interrupt Sources
TMR_0, TMR_1, TMR_Y and TMR_X can generate three types of interrupts: CMIA, CMIB, and OVI. Table 11.3 shows the interrupt sources and priorities. Each interrupt source can be enabled or disabled independently by interrupt enable bits in TCR or TCSR. Independent signals are sent to the interrupt controller for each interrupt. The CMIA and CMIB interrupts can be used as on-chip DTC activation interrupt sources. Table 11.3 Interrupt Sources of 8-Bit Timers TMR_0, TMR_1, TMR_Y, and TMR_X
Channel TMR_X Name CMIAX CMIBX OVIX TMR_0 CMIA0 CMIB0 OVI0 TMR_1 CMIA1 CMIB1 OVI1 TMR_Y CMIAY CMIBY OVIY Interrupt Source TCORA_X compare-match TCORB_X compare-match TCNT_X overflow TCORA_0 compare-match TCORB_0 compare-match TCNT_0 overflow TCORA_1 compare-match TCORB_1 compare-match TCNT_1 overflow TCORA_Y compare-match TCORB_Y compare-match TCNT_Y overflow Interrupt Flag CMFA CMFB OVF CMFA CMFB OVF CMFA CMFB OVF CMFA CMFB OVF DTC Activation Possible Possible Not possible Possible Possible Not possible Possible Possible Not possible Possible Possible Not possible Low Interrupt Priority High
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Section 11 8-Bit Timer (TMR)
11.6
11.6.1
Usage Notes
Conflict between TCNT Write and Counter Clear
If a counter clear signal is generated during the T2 state of a TCNT write cycle as shown in figure 11.7, the counter clear takes priority and the write is not performed.
TCNT write cycle by CPU T1 T2
Address
TCNT address
Internal write signal
Counter clear signal
TCNT
N
H'00
Figure 11.7 Conflict between TCNT Write and Counter Clear
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Section 11 8-Bit Timer (TMR)
11.6.2
Conflict between TCNT Write and Increment
If a TCNT input clock is generated during the T2 state of a TCNT write cycle as shown in figure 11.8, the write takes priority and the counter is not incremented.
TCNT write cycle by CPU T1 T2
Address
TCNT address
Internal write signal
TCNT input clock
TCNT
N
M
Counter write data
Figure 11.8 Conflict between TCNT Write and Increment
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Section 11 8-Bit Timer (TMR)
11.6.3
Conflict between TCOR Write and Compare-Match
If a compare-match occurs during the T2 state of a TCOR write cycle as shown in figure 11.9, the TCOR write takes priority and the compare-match signal is disabled.
TCOR write cycle by CPU
T1
T2
Address
TCOR address
Internal write signal
TCNT
N
N+1
TCOR
N
M
TCOR write data Compare-match signal
Disabled
Figure 11.9 Conflict between TCOR Write and Compare-Match
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Section 11 8-Bit Timer (TMR)
11.6.4
Switching of Internal Clocks and TCNT Operation
TCNT may increment erroneously when the internal clock is switched over. Table 11.8 shows the relationship between the timing at which the internal clock is switched (by writing to the CKS1 and CKS0 bits) and the TCNT operation. When the TCNT clock is generated from an internal clock, the falling edge of the internal clock pulse is detected. If clock switching causes a change from high to low level, as shown in no. 3 in table 11.4, a TCNT clock pulse is generated on the assumption that the switchover is a falling edge, and TCNT is incremented. Erroneous incrementation can also happen when switching between internal and external clocks. Table 11.4 Switching of Internal Clocks and TCNT Operation
Timing of Switchover by Means of CKS1 and CKS0 Bits Clock switching from low 1 to low level*
No. 1
TCNT Clock Operation
Clock before switchover Clock after switchover TCNT clock
TCNT
N CKS bit rewrite
N+1
2
Clock switching from low 2 to high level
Clock before switchover Clock after switchover TCNT clock
TCNT
N
N+1
N+2
CKS bit rewrite
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Section 11 8-Bit Timer (TMR)
No. 3
Timing of Switchover by Means of CKS1 and CKS0 Bits Clock switching from high 3 to low level
TCNT Clock Operation
Clock before switchover Clock after switchover TCNT clock *4
TCNT
N
N+1 CKS bit rewrite
N+2
4
Clock switching from high to high level
Clock before switchover Clock after switchover TCNT clock
TCNT
N
N+1
N+2 CKS bit rewrite
Notes: 1. 2. 3. 4.
Includes switching from low to stop, and from stop to low. Includes switching from stop to high. Includes switching from high to stop. Generated on the assumption that the switchover is a falling edge; TCNT is incremented.
11.6.5
Mode Setting with Cascaded Connection
If the 16-bit count mode and compare-match count mode are set simultaneously, the input clock pulses for TCNT_0 and TCNT_1 are not generated, and thus the counters will stop operating. Simultaneous setting of these two modes should be avoided.
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Section 12 Watchdog Timer (WDT)
Section 12 Watchdog Timer (WDT)
This LSI has two watchdog timer channels (WDT_0 and WDT_1). The watchdog timer can output an overflow signal (RESO) externally if a system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow. Simultaneously, it can generate an internal reset signal or an internal NMI interrupt signal. When this watchdog function is not needed, the WDT can be used as an interval timer. In interval timer operation, an interval timer interrupt is generated each time the counter overflows. A block diagram of the WDT_0 and WDT_1 are shown in figure 12.1.
12.1
Features
* Selectable from eight (WDT_0) or 16 (WDT_1) counter input clocks. * Switchable between watchdog timer mode and interval timer mode Watchdog Timer Mode: * If the counter overflows, an internal reset or an internal NMI interrupt is generated.
* When the LSI is selected to be internally reset at counter overflow, a low level signal is output from the RESO pin if the counter overflows. Internal Timer Mode: * If the counter overflows, an internal timer interrupt (WOVI) is generated.
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Section 12 Watchdog Timer (WDT)
WOVI0 (Interrupt request signal) Internal NMI (Interrupt request signal*2) RESO signal*1 Internal reset signal*1
Interrupt control Reset control
Overflow
Clock
Clock selection
/2 /64 /128 /512 /2048 /8192 /32768 /131072 Internal clock
TCNT_0
TCSR_0
Module bus
Bus interface
WDT_0
WOVI1 (Interrupt request signal) Internal NMI (Interrupt request signal*2) RESO signal*1 Internal reset signal*1
Interrupt control Reset control
Overflow
Clock
Clock selection
/2 /64 /128 /512 /2048 /8192 /32768 /131072 Internal clock
SUB/2 SUB/4 SUB/8 SUB/16 SUB/32 SUB/64 SUB/128 SUB/256
TCNT_1
TCSR_1
Module bus
Bus interface
WDT_1 [Legend] TCSR_0: TCNT_0: TCSR_1: TCNT_1: Timer control/status register_0 Timer counter_0 Timer control/status register_1 Timer counter_1
Notes: 1. The RESO signal outputs the low level signal when the internal reset signal is generated due to a TCNT overflow of either WDT_0 or WDT_1. The internal reset signal first resets the WDT in which the overflow has occurred first. 2. The internal NMI interrupt signal can be independently output from either WDT_0 or WDT_1. The interrupt controller does not distinguish the NMI interrupt request from WDT_0 from that from WDT_1.
Figure 12.1 Block Diagram of WDT
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Internal bus
Internal bus
Section 12 Watchdog Timer (WDT)
12.2
Input/Output Pins
The WDT has the pins listed in table 12.1. Table 12.1 Pin Configuration
Name Reset output pin Symbol RESO I/O Output Input Function Outputs the counter overflow signal in watchdog timer mode Inputs the clock pulses to the WDT_1 prescaler counter
External sub-clock input EXCL pin
12.3
Register Descriptions
The WDT has the following registers. To prevent accidental overwriting, TCSR and TCNT have to be written to in a method different from normal registers. For details, see section 12.6.1, Notes on Register Access. For details on the system control register, see section 3.2.2, System Control Register (SYSCR). * Timer counter (TCNT) * Timer control/status register (TCSR) 12.3.1 Timer Counter (TCNT)
TCNT is an 8-bit readable/writable up-counter. TCNT is initialized to H'00 when the TME bit in timer control/status register (TCSR) is cleared to 0.
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Section 12 Watchdog Timer (WDT)
12.3.2
Timer Control/Status Register (TCSR)
TCSR selects the clock source to be input to TCNT, and the timer mode. * TCSR_0
Bit 7 Bit Name OVF Initial Value 0 R/W Description
R/(W)* Overflow Flag Indicates that TCNT has overflowed (changes from H'FF to H'00). [Setting conditions] * * When TCNT overflows (changes from H'FF to H'00) When internal reset request generation is selected in watchdog timer mode, OVF is cleared automatically by the internal reset. When TCSR is read when OVF = 1, then 0 is written to OVF When 0 is written to TME
[Clearing conditions] * * 6 WT/IT 0 R/W
Timer Mode Select Selects whether the WDT is used as a watchdog timer or interval timer. 0: Interval timer mode 1: Watchdog timer mode
5
TME
0
R/W
Timer Enable When this bit is set to 1, TCNT starts counting. When this bit is cleared, TCNT stops counting and is initialized to H'00.
4 3
RST/NMI
0 0
R/W R/W
Reserved The initial value should not be changed. Reset or NMI Selects to request an internal reset or an NMI interrupt when TCNT has overflowed. 0: An NMI interrupt is requested 1: An internal reset is requested
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Section 12 Watchdog Timer (WDT)
Bit 2 to 0
Bit Name CKS2 to CKS0
Initial Value All 0
R/W R/W
Description Clock Select 2 to 0 Select the clock source to be input to TCNT. The overflow period for = 34 MHz is enclosed in parentheses. 000: /2 (period: 15.1 s) 001: /64 (period: 481.9 s) 010: /128 (period: 963.8 s) 011: /512 (period: 3.856 ms) 100: /2048 (period: 15.42 ms) 101: /8192 (period: 61.68 ms) 110: /32768 (period: 246.7 ms) 111: /131072 (period: 986.9 ms)
Note:
*
Only 0 can be written to clear the flag.
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Section 12 Watchdog Timer (WDT)
* TCSR_1
Bit 7 Bit Name OVF Initial Value 0 R/W
1
Description
R/(W)* Overflow Flag Indicates that TCNT has overflowed (changes from H'FF to H'00). [Setting conditions] * * When TCNT overflows (changes from H'FF to H'00) When internal reset request generation is selected in watchdog timer mode, OVF is cleared automatically by the internal reset. When TCSR is read when OVF = 1* , then 0 is written to OVF When 0 is written to TME
2
[Clearing conditions] * * 6 WT/IT 0 R/W
Timer Mode Select Selects whether the WDT is used as a watchdog timer or interval timer. 0: Interval timer mode 1: Watchdog timer mode
5
TME
0
R/W
Timer Enable When this bit is set to 1, TCNT starts counting. When this bit is cleared, TCNT stops counting and is initialized to H'00. When PSS = 1, TCNT is not initialized. Write H'00 to TCNT to initialize TCNT.
4
PSS
0
R/W
Prescaler Select Selects the clock source to be input to TCNT. 0: Counts the divided cycle of -based prescaler (PSM) 1: Counts the divided cycle of SUB-based prescaler (PSS)
3
RST/NMI
0
R/W
Reset or NMI Selects to request an internal reset or an NMI interrupt when TCNT has overflowed. 0: An NMI interrupt is requested 1: An internal reset is requested
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Section 12 Watchdog Timer (WDT)
Bit 2 to 0
Bit Name CKS2 to CKS0
Initial Value All 0
R/W R/W
Description Clock Select 2 to 0 Select the clock source to be input to TCNT. The overflow cycle for = 34 MHz and SUB = 32.768 kHz is enclosed in parentheses. When PSS = 0: 000: /2 (cycle: 15.1 s) 001: /64 (cycle: 481.9 s) 010: /128 (cycle: 963.8 s) 011: /512 (cycle: 3.856 ms) 100: /2048 (cycle: 15.42 ms) 101: /8192 (cycle: 61.68 ms) 110: /32768 (cycle: 246.7 ms) 111: /131072 (cycle: 986.9 ms) When PSS = 1: 000: SUB/2 (cycle: 15.6 ms) 001: SUB/4 (cycle: 31.3 ms) 010: SUB/8 (cycle: 62.5 ms) 011: SUB/16 (cycle: 125 ms) 100: SUB/32 (cycle: 250 ms) 101: SUB/64 (cycle: 500 ms) 110: SUB/128 (cycle: 1 s) 111: SUB/256 (cycle: 2 s)
Notes: 1. Only 0 can be written to clear the flag. 2. When OVF is polled with the interval timer interrupt disabled, OVF = 1 must be read at least twice.
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Section 12 Watchdog Timer (WDT)
12.4
12.4.1
Operation
Watchdog Timer Mode
To use the WDT as a watchdog timer, set the WT/IT bit and the TME bit in TCSR to 1. While the WDT is used as a watchdog timer, if TCNT overflows without being rewritten because of a system malfunction or another error, an internal reset or NMI interrupt request is generated. TCNT does not overflow while the system is operating normally. Software must prevent TCNT overflows by rewriting the TCNT value (normally be writing H'00) before overflows occurs. If the RST/NMI bit of TCSR is set to 1, when the TCNT overflows, an internal reset signal for this LSI is issued for 518 system clocks, and the low level signal is simultaneously output from the RESO pin for 132 states, as shown in figure 12.2. If the RST/NMI bit is cleared to 0, when the TCNT overflows, an NMI interrupt request is generated. Here, the output from the RESO pin remains high. An internal reset request from the watchdog timer and a reset input from the RES pin are processed in the same vector. Reset source can be identified by the XRST bit status in SYSCR. If a reset caused by a signal input to the RES pin occurs at the same time as a reset caused by a WDT overflow, the RES pin reset has priority and the XRST bit in SYSCR is set to 1. An NMI interrupt request from the watchdog timer and an interrupt request from the NMI pin are processed in the same vector. Do not handle an NMI interrupt request from the watchdog timer and an interrupt request from the NMI pin at the same time.
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Section 12 Watchdog Timer (WDT)
TCNT value Overflow H'FF
H'00 WT/IT = 1 TME = 1 Internal reset signal 518 system clocks WT/IT: TME: OVF: Timer mode select bit Timer enable bit Overflow flag Write H'00 to TCNT OVF = 1*
Time WT/IT = 1 Write H'00 to TME = 1 TCNT
Note: * After the OVF bit becomes 1, it is cleared to 0 by an internal reset. The XRST bit is also cleared to 0.
Figure 12.2 Watchdog Timer Mode (RST/NMI = 1) Operation
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Section 12 Watchdog Timer (WDT)
12.4.2
Interval Timer Mode
When the WDT is used as an interval timer, an interval timer interrupt (WOVI) is generated each time the TCNT overflows, as shown in figure 12.3. Therefore, an interrupt can be generated at intervals. When the TCNT overflows in interval timer mode, an interval timer interrupt (WOVI) is requested at the same time the OVF bit of TCSR is set to 1. The timing is shown in figure 12.4.
TCNT value H'FF Overflow Overflow Overflow Overflow
H'00 WT/IT = 0 TME = 1 WOVI WOVI WOVI WOVI
Time
WOVI : Interval timer interrupt request occurrence
Figure 12.3 Interval Timer Mode Operation
TCNT
H'FF
H'00
Overflow signal (internal signal)
OVF
Figure 12.4 OVF Flag Set Timing
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Section 12 Watchdog Timer (WDT)
12.4.3
RESO Signal Output Timing
When TCNT overflows in watchdog timer mode, the OVF bit in TCSR is set to 1. When the RST/NMI bit is 1 here, the internal reset signal is generated for the entire LSI. At the same time, the low level signal is output from the RESO pin. The timing is shown in figure 12.5.
TCNT
H'FF
H'00
Overflow signal (internal signal)
OVF
RESO signal
132 states
Internal reset signal
518 states
Figure 12.5 Output Timing of RESO signal This LSI has retain state pins, which are only initialized by a system reset. The outputs on these pins are retained even when an internal reset is generated by the overflow signal of the WDT. For more information, see section 8, I/O Ports.
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Section 12 Watchdog Timer (WDT)
12.5
Interrupt Sources
During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI). The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. OVF must be cleared to 0 in the interrupt handling routine. When the NMI interrupt request is selected in watchdog timer mode, an NMI interrupt request is generated by an overflow Table 12.2 WDT Interrupt Source
Name WOVI Interrupt Source TCNT overflow Interrupt Flag OVF DTC Activation Not possible
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Section 12 Watchdog Timer (WDT)
12.6
12.6.1
Usage Notes
Notes on Register Access
The watchdog timer's registers, TCNT and TCSR differ from other registers in being more difficult to write to. The procedures for writing to and reading from these registers are given below. Writing to TCNT and TCSR (Example of WDT_0): These registers must be written to by a word transfer instruction. They cannot be written to by a byte transfer instruction. TCNT and TCSR both have the same write address. Therefore, satisfy the relative condition shown in figure 12.6 to write to TCNT or TCSR. To write to TCNT, the higher bytes must contain the value H'5A and the lower bytes must contain the write data. To write to TCSR, the higher bytes must contain the value H'A5 and the lower bytes must contain the write data.
15 Address : H'FFA8 H'5A 87 Write data 0
15 Address : H'FFA8 H'A5 87 Write data 0
Figure 12.6 Writing to TCNT and TCSR (WDT_0) Reading from TCNT and TCSR (Example of WDT_0): These registers are read in the same way as other registers. The read address is H'FFA8 for TCSR and H'FFA9 for TCNT.
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Section 12 Watchdog Timer (WDT)
12.6.2
Conflict between Timer Counter (TCNT) Write and Increment
If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write takes priority and the timer counter is not incremented. Figure 12.7 shows this operation.
TCNT write cycle T1 T2
Address
Internal write signal
TCNT input clock
TCNT
N
M
Counter write data
Figure 12.7 Conflict between TCNT Write and Increment 12.6.3 Changing Values of CKS2 to CKS0 Bits
If CKS2 to CKS0 bits in TCSR are written to while the WDT is operating, errors could occur in the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0) before changing the values of CKS2 to CKS0 bits. 12.6.4 Changing Value of PSS Bit
If the PSS bit in TCSR_1 is written to while the WDT is operating, errors could occur in the operation. Stop the watchdog timer (by clearing the TME bit to 0) before changing the values of PSS bit.
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Section 12 Watchdog Timer (WDT)
12.6.5
Switching between Watchdog Timer Mode and Interval Timer Mode
If the mode is switched from/to watchdog timer to/from interval timer, while the WDT is operating, errors could occur in the operation. Software must stop the watchdog timer (by clearing the TME bit to 0) before switching the mode. 12.6.6 System Reset by RESO Signal
Inputting the RESO output signal to the RES pin of this LSI prevents the LSI from being initialized correctly; the RESO signal must not be logically connected to the RES pin of the LSI. To reset the entire system by the RESO signal, use the circuit as shown in figure 12.8.
This LSI Reset input RES
Reset signal for entire system
RESO
Figure 12.8 Sample Circuit for Resetting the System by the RESO Signal
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Section 12 Watchdog Timer (WDT)
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Section 13 Serial Communication Interface (SCI)
Section 13 Serial Communication Interface (SCI)
This LSI has two independent serial communication interface (SCI) channels. The SCI can handle both asynchronous and clock synchronous serial communication. Asynchronous serial data communication can be carried out with standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA). A function is also provided for serial communication between processors (multiprocessor communication function). The SCI also supports the smart card (IC card) interface based on ISO/IEC 7816-3 (Identification Card) as an enhanced asynchronous communication function.
13.1
Features
* Choice of asynchronous or clock synchronous serial communication mode * Full-duplex communication capability The transmitter and receiver are mutually independent, enabling transmission and reception to be executed simultaneously. Double-buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data. * On-chip baud rate generator allows any bit rate to be selected The external clock can be selected as a transfer clock source (except for the smart card interface). * Choice of LSB-first or MSB-first transfer (except in the case of asynchronous mode 7-bit data) * Four interrupt sources Four interrupt sources transmit-end, transmit-data-empty, receive-data-full, and receive error that can issue requests. The transmit-data-empty and receive-data-full interrupt sources can activate DTC. * Module stop mode availability
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Section 13 Serial Communication Interface (SCI)
Asynchronous Mode: * Data length: 7 or 8 bits * Stop bit length: 1 or 2 bits * Parity: Even, odd, or none * Receive error detection: Parity, overrun, and framing errors * Break detection: Break can be detected by reading the RxD pin level directly in case of a framing error Clock Synchronous Mode: * Data length: 8 bits * Receive error detection: Overrun errors Smart Card Interface: * An error signal can be automatically transmitted on detection of a parity error during reception * Data can be automatically re-transmitted on detection of a error signal during transmission * Both direct convention and inverse convention are supported
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Section 13 Serial Communication Interface (SCI)
Figure 13.1 is a block diagram of SCI_1 and SCI_3.
Module data bus
RDR
TDR
SCMR SSR SCR
BRR Baud rate generator /4 /16 /64 Clock External clock TEI TXI RXI ERI
RxD1/RxD3
RSR
TSR
SMR Transmission/ reception control
TxD1/TxD3 Parity check SCK1/SCK3
Parity generation
[Legend] RSR: Receive shift register RDR: Receive data register TSR: Transmit shift register TDR: Transmit data register SMR: Serial mode register
SCR: SSR: SCMR: BRR:
Serial control register Serial status register Smart card mode register Bit rate register
Figure 13.1 Block Diagram of SCI_1 and SCI_3
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Internal data bus
Bus interface
Section 13 Serial Communication Interface (SCI)
13.2
Input/Output Pins
Table 13.1 shows the input/output pins for each SCI channel. Table 13.1 Pin Configuration
Channel 1 Symbol* SCK1 RxD1 Input/Output Input/Output Input Input/Output TxD1 3 SCK3 RxD3 Output Input/Output Input Input/Output TxD3 Note: * Output Function Channel 1 clock input/output Channel 1 receive data input Channel 1 transmit/receive data input/output (when smart card interface is selected) Channel 1 transmit data output Channel 3 clock input/output Channel 3 receive data input Channel 3 transmit/receive data input/output (when smart card interface is selected) Channel 3 transmit data output
Pin names SCK, RxD, and TxD are used in the text for all channels, omitting the channel designation.
13.3
Register Descriptions
The SCI has the following registers for each channel. Some bits in the serial mode register (SMR), serial status register (SSR), and serial control register (SCR) have different functions in different modesnormal serial communication interface mode and smart card interface mode; therefore, the bits are described separately for each mode in the corresponding register sections. * Receive shift register (RSR) * Receive data register (RDR) * Transmit data register (TDR) * Transmit shift register (TSR) * Serial mode register (SMR) * Serial control register (SCR) * Serial status register (SSR) * Smart card mode register (SCMR) * Bit rate register (BRR)
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Section 13 Serial Communication Interface (SCI)
13.3.1
Receive Shift Register (RSR)
RSR is a shift register used to receive serial data that converts it into parallel data. When one frame of data has been received, it is transferred to RDR automatically. RSR cannot be directly accessed by the CPU. 13.3.2 Receive Data Register (RDR)
RDR is an 8-bit register that stores receive data. When the SCI has received one frame of serial data, it transfers the received serial data from RSR to RDR where it is stored. After this, RSR can receive the next data. Since RSR and RDR function as a double buffer in this way, continuous receive operations be performed. After confirming that the RDRF bit in SSR is set to 1, read RDR for only once. RDR cannot be written to by the CPU. 13.3.3 Transmit Data Register (TDR)
TDR is an 8-bit register that stores transmit data. When the SCI detects that TSR is empty, it transfers the transmit data written in TDR to TSR and starts transmission. The double-buffered structures of TDR and TSR enables continuous serial transmission. If the next transmit data has already been written to TDR when one frame of data is transmitted, the SCI transfers the written data to TSR to continue transmission. Although TDR can be read from or written to by the CPU at all times, to achieve reliable serial transmission, write transmit data to TDR for only once after confirming that the TDRE bit in SSR is set to 1. 13.3.4 Transmit Shift Register (TSR)
TSR is a shift register that transmits serial data. To perform serial data transmission, the SCI first transfers transmit data from TDR to TSR, then sends the data to the TxD pin. TSR cannot be directly accessed by the CPU.
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Section 13 Serial Communication Interface (SCI)
13.3.5
Serial Mode Register (SMR)
SMR is used to set the SCI's serial transfer format and select the baud rate generator clock source. Some bits in SMR have different functions in normal mode and smart card interface mode. * Bit Functions in Normal Serial Communication Interface Mode (when SMIF in SCMR = 0)
Bit 7 Bit Name C/A Initial Value 0 R/W R/W Description Communication Mode 0: Asynchronous mode 1: Clock synchronous mode 6 CHR 0 R/W Character Length (enabled only in asynchronous mode) 0: Selects 8 bits as the data length. 1: Selects 7 bits as the data length. LSB-first is fixed and the MSB of TDR is not transmitted in transmission. In clock synchronous mode, a fixed data length of 8 bits is used. 5 PE 0 R/W Parity Enable (enabled only in asynchronous mode) When this bit is set to 1, the parity bit is added to transmit data before transmission, and the parity bit is checked in reception. For a multiprocessor format, parity bit addition and checking are not performed regardless of the PE bit setting. 4 O/E 0 R/W Parity Mode (enabled only when the PE bit is 1 in asynchronous mode) 0: Selects even parity. 1: Selects odd parity. 3 STOP 0 R/W Stop Bit Length (enabled only in asynchronous mode) Selects the stop bit length in transmission. 0: 1 stop bit 1: 2 stop bits In reception, only the first stop bit is checked. If the second stop bit is 0, it is treated as the start bit of the next transmit frame. 2 MP 0 R/W Multiprocessor Mode (enabled only in asynchronous mode) When this bit is set to 1, the multiprocessor communication function is enabled. The PE bit and O/E bit settings are invalid in multiprocessor mode.
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Section 13 Serial Communication Interface (SCI)
Bit 1 0
Bit Name CKS1 CKS0
Initial Value 0 0
R/W R/W R/W
Description Clock Select 1 and 0 These bits select the clock source for the baud rate generator. 00: clock (n = 0) 01: /4 clock (n = 1) 10: /16 clock (n = 2) 11: /64 clock (n = 3) For the relation between the bit rate register setting and the baud rate, see section 13.3.9, Bit Rate Register (BRR). n is the decimal display of the value of n in BRR (see section 13.3.9, Bit Rate Register (BRR)).
* Bit Functions in Smart Card Interface Mode (when SMIF in SCMR = 1)
Bit 7 Bit Name GM Initial Value 0 R/W R/W Description GSM Mode Setting this bit to 1 allows GSM mode operation. In GSM mode, the TEND set timing is put forward to 11.0 etu* from the start and the clock output control function is appended. For details, see section 13.7.8, Clock Output Control. 6 5 BLK PE 0 0 R/W R/W Setting this bit to 1 allows block transfer mode operation. For details, see section 13.7.3, Block Transfer Mode. Parity Enable (valid only in asynchronous mode) When this bit is set to 1, the parity bit is added to transmit data before transmission, and the parity bit is checked in reception. Set this bit to 1 in smart card interface mode. 4 O/E 0 R/W Parity Mode (valid only when the PE bit is 1 in asynchronous mode) 0: Selects even parity 1: Selects odd parity For details on the usage of this bit in smart card interface mode, see section 13.7.2, Data Format (Except in Block Transfer Mode).
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Section 13 Serial Communication Interface (SCI)
Bit 3 2
Bit Name BCP1 BCP0
Initial Value 0 0
R/W R/W R/W
Description Basic Clock Pulse 1 and 0 These bits select the number of basic clock cycles in a 1bit data transfer time in smart card interface mode. 00: 32 clock cycles (S = 32) 01: 64 clock cycles (S = 64) 10: 372 clock cycles (S = 372) 11: 256 clock cycles (S = 256) For details, see section 13.7.4, Receive Data Sampling Timing and Reception Margin. S is described in section 13.3.9, Bit Rate Register (BRR).
1 0
CKS1 CKS0
0 0
R/W R/W
Clock Select 1 and 0 These bits select the clock source for the baud rate generator. 00: clock (n = 0) 01: /4 clock (n = 1) 10: /16 clock (n = 2) 11: /64 clock (n = 3) For the relation between the bit rate register setting and the baud rate, see section 13.3.9, Bit Rate Register (BRR). n is the decimal display of the value of n in BRR (see section 13.3.9, Bit Rate Register (BRR)).
Note:
*
etu: Element Time Unit (time taken to transfer one bit)
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Section 13 Serial Communication Interface (SCI)
13.3.6
Serial Control Register (SCR)
SCR is a register that performs enabling or disabling of SCI transfer operations and interrupt requests, and selection of the transfer clock source. For details on interrupt requests, see section 13.8, Interrupt Sources. Some bits in SCR have different functions in normal mode and smart card interface mode. * Bit Functions in Normal Serial Communication Interface Mode (when SMIF in SCMR = 0)
Bit 7 Bit Name TIE Initial Value 0 R/W R/W Description Transmit Interrupt Enable When this bit is set to 1, a TXI interrupt request is enabled. 6 RIE 0 R/W Receive Interrupt Enable When this bit is set to 1, RXI and ERI interrupt requests are enabled. 5 4 3 TE RE MPIE 0 0 0 R/W R/W R/W Transmit Enable When this bit is set to 1, transmission is enabled. Receive Enable When this bit is set to 1, reception is enabled. Multiprocessor Interrupt Enable (enabled only when the MP bit in SMR is 1 in asynchronous mode) When this bit is set to 1, receive data in which the multiprocessor bit is 0 is skipped, and setting of the RDRF, FER, and ORER status flags in SSR is disabled. On receiving data in which the multiprocessor bit is 1, this bit is automatically cleared and normal reception is resumed. For details, see section 13.5, Multiprocessor Communication Function. 2 TEIE 0 R/W Transmit End Interrupt Enable When this bit is set to 1, a TEI interrupt request is enabled.
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Section 13 Serial Communication Interface (SCI)
Bit 1 0
Bit Name CKE1 CKE0
Initial Value 0 0
R/W R/W R/W
Description Clock Enable 1 and 0 These bits select the clock source and SCK pin function. Asynchronous mode: 00: Internal clock (SCK pin functions as I/O port.) 01: Internal clock (Outputs a clock of the same frequency as the bit rate from the SCK pin.) 1x: External clock (Inputs a clock with a frequency 16 times the bit rate from the SCK pin.) Clock synchronous mode: 0x: Internal clock (SCK pin functions as clock output.) 1x: External clock (SCK pin functions as clock input.)
[Legend] x: Don't care
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Section 13 Serial Communication Interface (SCI)
* Bit Functions in Smart Card Interface Mode (when SMIF in SCMR = 1)
Bit 7 6 Bit Name TIE RIE Initial Value 0 0 R/W R/W R/W Description Transmit Interrupt Enable When this bit is set to 1, a TXI interrupt request is enabled. Receive Interrupt Enable When this bit is set to 1, RXI and ERI interrupt requests are enabled. 5 4 3 TE RE MPIE 0 0 0 R/W R/W R/W Transmit Enable When this bit is set to 1, transmission is enabled. Receive Enable When this bit is set to 1, reception is enabled. Multiprocessor Interrupt Enable (enabled only when the MP bit in SMR is 1 in asynchronous mode) Write 0 to this bit in smart card interface mode. Transmit End Interrupt Enable Write 0 to this bit in smart card interface mode. Clock Enable 1 and 0 These bits control the clock output from the SCK pin. In GSM mode, clock output can be dynamically switched. For details, see section 13.7.8, Clock Output Control. When GM in SMR = 0 00: Output disabled (SCK pin functions as I/O port.) 01: Clock output 1x: Reserved When GM in SMR = 1 00: Output fixed to low 01: Clock output 10: Output fixed to high 11: Clock output [Legend] x: Don't care
2 1 0
TEIE CKE1 CKE0
0 0 0
R/W R/W R/W
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Section 13 Serial Communication Interface (SCI)
13.3.7
Serial Status Register (SSR)
SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. TDRE, RDRF, ORER, PER, and FER can only be cleared. Some bits in SSR have different functions in normal mode and smart card interface mode. * Bit Functions in Normal Serial Communication Interface Mode (when SMIF in SCMR = 0)
Bit 7 Bit Name TDRE Initial Value 1 R/W Description Indicates whether TDR contains transmit data. [Setting conditions] * * When the TE bit in SCR is 0 When data is transferred from TDR to TSR and TDR is ready for data write When 0 is written to TDRE after reading TDRE = 1 When a TXI interrupt request is issued allowing DTC to write data to TDR
R/(W)* Transmit Data Register Empty
[Clearing conditions] * * 6 RDRF 0
R/(W)* Receive Data Register Full Indicates that receive data is stored in RDR. [Setting condition] * When serial reception ends normally and receive data is transferred from RSR to RDR When 0 is written to RDRF after reading RDRF = 1 When an RXI interrupt request is issued allowing DTC to read data from RDR
[Clearing conditions] * *
The RDRF flag is not affected and retains its previous value when the RE bit in SCR is cleared to 0.
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Section 13 Serial Communication Interface (SCI)
Bit 5
Bit Name ORER
Initial Value 0
R/W
Description
R/(W)* Overrun Error [Setting condition] When the next serial reception is completed while RDRF = 1 [Clearing condition] When 0 is written to ORER after reading ORER = 1
4
FER
0
R/(W)* Framing Error [Setting condition] When the stop bit is 0 [Clearing condition] When 0 is written to FER after reading FER = 1 In 2-stop-bit mode, only the first stop bit is checked.
3
PER
0
R/(W)* Parity Error [Setting condition] When a parity error is detected during reception [Clearing condition] When 0 is written to PER after reading PER = 1
2
TEND
1
R
Transmit End [Setting conditions] * * When the TE bit in SCR is 0 When TDRE = 1 at transmission of the last bit of a 1byte serial transmit character When 0 is written to TDRE after reading TDRE = 1 When a TXI interrupt request is issued allowing DTC to write data to TDR
[Clearing conditions] * * 1 MPB 0 R
Multiprocessor Bit MPB stores the multiprocessor bit in the receive frame. When the RE bit in SCR is cleared to 0, its previous state is retained.
0
MPBT
0
R/W
Multiprocessor Bit Transfer MPBT stores the multiprocessor bit to be added to the transmit frame.
Note:
*
Only 0 can be written to clear the flag.
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Section 13 Serial Communication Interface (SCI)
* Bit Functions in Smart Card Interface Mode (when SMIF in SCMR = 1)
Bit 7 Bit Name TDRE Initial Value 1 R/W
1
Description
R/(W)* Transmit Data Register Empty Indicates whether TDR contains transmit data. [Setting conditions] * * When the TE bit in SCR is 0 When data is transferred from TDR to TSR, and TDR can be written to. When 0 is written to TDRE after reading TDRE = 1 When a TXI interrupt request is issued allowing DTC to write data to TDR
[Clearing conditions] * * 6 RDRF 0
1
R/(W)* Receive Data Register Full Indicates whether the receive data is stored in RDR. [Setting condition] * When serial reception ends normally and receive data is transferred from RSR to RDR When 0 is written to RDRF after reading RDRF = 1 When an RXI interrupt request is issued allowing DTC to read data from RDR
[Clearing conditions] * *
The RDRF flag is not affected and retains its previous value when the RE bit in SCR is cleared to 0. 5 ORER 0 R/(W)* Overrun Error [Setting condition] When the next serial reception is completed while RDRF = 1 [Clearing condition] When 0 is written to ORER after reading ORER = 1 4 ERS 0 R/(W)* Error Signal Status [Setting condition] When a low error signal is sampled [Clearing condition] When 0 is written to ERS after reading ERS = 1
1 1
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Section 13 Serial Communication Interface (SCI)
Bit 3
Bit Name PER
Initial Value 0
R/W
1
Description
R/(W)* Parity Error [Setting condition] When a parity error is detected during reception [Clearing condition] When 0 is written to PER after reading PER = 1
2
TEND
1
R
Transmit End TEND is set to 1 when the receiving end acknowledges no error signal and the next transmit data is ready to be transferred to TDR. [Setting conditions] * * When both TE in SCR and ERS are 0 When ERS = 0 and TDRE = 1 after a specified time passed after the start of 1-byte data transfer. The set timing depends on the register setting as follows. When GM = 0 and BLK = 0, 2.5 etu* after transmission start When GM = 0 and BLK = 1, 1.5 etu* after transmission start When GM = 1 and BLK = 0, 1.0 etu* after transmission start When GM = 1 and BLK = 1, 1.0 etu* after transmission start [Clearing conditions] * * When 0 is written to TDRE after reading TDRE = 1 When a TXI interrupt request is issued allowing DTC to write the next data to TDR
2 2 2 2
1 0
MPB MPBT
0 0
R R/W
Multiprocessor Bit Not used in smart card interface mode. Multiprocessor Bit Transfer Write 0 to this bit in smart card interface mode.
Notes: 1. Only 0 can be written to clear the flag. 2. etu: Element Time Unit (time taken to transfer one bit)
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Section 13 Serial Communication Interface (SCI)
13.3.8
Smart Card Mode Register (SCMR)
SCMR selects smart card interface mode and its format.
Bit 7 to 4 3 Bit Name SDIR Initial Value All 1 0 R/W R R/W Description Reserved These bits are always read as 1 and cannot be modified. Smart Card Data Transfer Direction Selects the serial/parallel conversion format. 0: TDR contents are transmitted with LSB-first. Stores receive data as LSB first in RDR. 1: TDR contents are transmitted with MSB-first. Stores receive data as MSB first in RDR. The SDIR bit is valid only when the 8-bit data format is used for transmission/reception; when the 7-bit data format is used, data is always transmitted/received with LSB-first. 2 SINV 0 R/W Smart Card Data Invert Specifies inversion of the data logic level. The SINV bit does not affect the logic level of the parity bit. When the parity bit is inverted, invert the O/E bit in SMR. 0: TDR contents are transmitted as they are. Receive data is stored as it is in RDR. 1: TDR contents are inverted before being transmitted. Receive data is stored in inverted form in RDR. 1 0 SMIF 1 0 R R/W Reserved This bit is always read as 1 and cannot be modified. Smart Card Interface Mode Select When this bit is set to 1, smart card interface mode is selected. 0: Normal asynchronous or clock synchronous mode 1: Smart card interface mode
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Section 13 Serial Communication Interface (SCI)
13.3.9
Bit Rate Register (BRR)
BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control independently for each channel, different bit rates can be set for each channel. Table 13.2 shows the relationships between the N setting in BRR and bit rate B for normal asynchronous mode and clock synchronous mode, and smart card interface mode. The initial value of BRR is H'FF, and it can be read from or written to by the CPU at all times. Table 13.2 Relationships between N Setting in BRR and Bit Rate B
Mode Asynchronous mode
B= 64 x 2
Bit Rate
x 106
2n - 1
Error
Error (%) = { x 106 B x 64 x 2
2n - 1
- 1 } x 100
x (N + 1)
x (N + 1)
Clock synchronous mode
B=
x 106 8x2
2n - 1
x (N + 1)
x 106 BxSx2
2n + 1
Smart card interface mode
B= Sx2
x 106
2n + 1
Error (%) = {
-1 } x 100
x (N + 1)
x (N + 1)
[Legend] B: N: : n and S:
Bit rate (bit/s) BRR setting for baud rate generator (0 N 255) Operating frequency (MHz) Determined by the SMR settings shown in the following table. SMR Setting CKS1 0 0 1 1 CKS0 0 1 0 1 n 0 1 2 3 BCP1 0 0 1 1 SMR Setting BCP0 0 1 0 1 S 32 64 372 256
Table 13.3 shows sample N settings in BRR in normal asynchronous mode. Table 13.4 shows the maximum bit rate settable for each frequency. Table 13.6 and 13.8 show sample N settings in BRR in clock synchronous mode and smart card interface mode, respectively. In smart card interface mode, the number of basic clock cycles S in a 1-bit data transfer time can be selected. For details, see section 13.7.4, Receive Data Sampling Timing and Reception Margin. Tables 13.5 and 13.7 show the maximum bit rates with external clock input.
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Section 13 Serial Communication Interface (SCI)
Table 13.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode)
Operating Frequency (MHz) 20 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 Note: n 3 3 2 2 1 1 0 0 0 0 0 N 88 64 129 64 129 64 129 64 32 19 15 Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -1.36 0.00 1.73 n 3 3 2 2 1 1 0 0 0 0 0 N 110 80 162 80 162 80 162 80 40 24 19 25 Error (%) -0.02 -0.47 0.15 -0.47 0.15 -0.47 0.15 -0.47 -0.76 0.00 1.73 n 3 3 2 2 1 1 0 0 0 0 0 N 150 110 220 110 220 110 220 110 54 33 27 34 Error (%) -0.05 -0.29 0.16 -0.29 0.16 -0.29 0.16 -0.29 0.62 0.00 -1.18
Make the settings so that the error does not exceed 1%.
Table 13.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode)
(MHz) 20 25 34 Maximum Bit Rate (bit/s) 625000 781250 1062500 n 0 0 0 N 0 0 0
Table 13.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode)
(MHz) 20 25 34 External Input Clock (MHz) 5.0000 6.2500 8.0000 Maximum Bit Rate (bit/s) 312500 390625 531250
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Section 13 Serial Communication Interface (SCI)
Table 13.6 BRR Settings for Various Bit Rates (Clock Synchronous Mode)
Operating Frequency (MHz) 20 Bit Rate (bit/s) 110 250 500 1k 2.5 k 5k 10 k 25 k 50 k 100 k 250 k 500 k 1M 2.5 M 5M 2 1 1 0 0 0 0 0 0 0 0 124 249 124 199 99 49 19 9 4 1 0* 2 2 1 0 0 0 0 0 0 149 74 149 239 119 59 23 11 5 2 2 1 1 0 0 0 0 212 105 212 84 169 84 33 16 n N n 24 N n 34 N
[Legend] Blank: Setting prohibited. : Can be set, but there will be a degree of error. *: Continuous transfer or reception is not possible.
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Section 13 Serial Communication Interface (SCI)
Table 13.7 Maximum Bit Rate with External Clock Input (Clock Synchronous Mode)
(MHz) 20 25 34 External Input Clock (MHz) 3.3333 4.1667 5.6667 Maximum Bit Rate (bit/s) 3333333.3 4166666.7 5666666.7
Table 13.8 BRR Settings for Various Bit Rates (Smart Card Interface Mode, n = 0, s = 372)
Operating Frequency (MHz) Bit Rate (bit/s) n 9600 0 20.00 N 2 Error (%) -6.65 n 0 N 2 21.4272 Error(%) 0.00 n 0 N 3 25 Error (%) -12.49 n 0 N 4 34 Error (%) -4.79
Table 13.9 Maximum Bit Rate for Each Frequency (Smart Card Interface Mode, S = 372)
(MHz) 20.00 21.4272 25.00 34.00 Maximum Bit Rate (bit/s) 26882 28800 33602 45699 n 0 0 0 0 N 0 0 0 0
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Section 13 Serial Communication Interface (SCI)
13.4
Operation in Asynchronous Mode
Figure 13.2 shows the general format for asynchronous serial communication. One frame consists of a start bit (low level), followed by transmit/receive data, a parity bit, and finally stop bits (high level). In asynchronous serial communication, the transmission line is usually held in the mark state (high level). The SCI monitors the transmission line, and when it goes to the space state (low level), recognizes a start bit and starts serial communication. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication. Both the transmitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transfer and reception.
Idle state (mark state) 1 Serial data 0 Start bit 1 bit LSB D0 D1 D2 D3 D4 D5 D6 MSB D7 0/1 Parity bit 1 bit or none 1 1 1
Stop bit
Transmit/receive data 7 or 8 bits
1 or 2 bits
One unit of transfer data (character or frame)
Figure 13.2 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits)
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Section 13 Serial Communication Interface (SCI)
13.4.1
Data Transfer Format
Table 13.10 shows the data transfer formats that can be used in asynchronous mode. Any of 12 transfer formats can be selected according to the SMR setting. For details on the multiprocessor bit, see section 13.5, Multiprocessor Communication Function. Table 13.10 Serial Transfer Formats (Asynchronous Mode)
SMR Settings CHR 0 PE 0 MP 0 STOP 0 1 S Serial Transmit/Receive Format and Frame Length 2 3 4 5 6 7 8 9 10 STOP 11 12
8-bit data
0
0
0
1
S
8-bit data
STOP STOP
0
1
0
0
S
8-bit data
P STOP
0
1
0
1
S
8-bit data
P STOP STOP
1
0
0
0
S
7-bit data
STOP
1
0
0
1
S
7-bit data
STOP STOP
1
1
0
0
S
7-bit data
P
STOP
1
1
0
1
S
7-bit data
P
STOP STOP
0
--
1
0
S
8-bit data
MPB STOP
0
--
1
1
S
8-bit data
MPB STOP STOP
1
--
1
0
S
7-bit data
MPB STOP
1
--
1
1
S
7-bit data
MPB STOP STOP
[Legend] S: Start bit STOP: Stop bit P: Parity bit MPB: Multiprocessor bit
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Section 13 Serial Communication Interface (SCI)
13.4.2
Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the bit rate. In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs internal synchronization. Since receive data is latched internally at the rising edge of the 8th pulse of the basic clock, data is latched at the middle of each bit, as shown in figure 13.3. Thus the reception margin in asynchronous mode is determined by formula (1) below.
M = } (0.5 -
1 2N
)-
D - 0.5 (1+F) - (L - 0.5) F } x 100 N
[%]
... Formula (1)
M: Reception margin (%) N: Ratio of bit rate to clock (N = 16) D: Clock duty (D = 0.5 to 1.0) L: Frame length (L = 9 to 12) F: Absolute value of clock rate deviation
Assuming values of F = 0 and D = 0.5 in formula (1), the reception margin is determined by the formula below.
M = {0.5 - 1/(2 x 16) } x 100 [%] = 46.875 %
However, this is only the computed value, and a margin of 20% to 30% should be allowed in system design.
16 clocks 8 clocks 0 Internal basic clock 7 15 0 7 15 0
Receive data (RxD) Synchronization sampling timing
Start bit
D0
D1
Data sampling timing
Figure 13.3 Receive Data Sampling Timing in Asynchronous Mode
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Section 13 Serial Communication Interface (SCI)
13.4.3
Clock
Either an internal clock generated by the on-chip baud rate generator or an external clock input at the SCK pin can be selected as the SCI's transfer clock, according to the setting of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR. When an external clock is input at the SCK pin, the clock frequency should be 16 times the bit rate used. When the SCI is operated on an internal clock, the clock can be output from the SCK pin. The frequency of the clock output in this case is equal to the bit rate, and the phase is such that the rising edge of the clock is in the middle of the transmit data, as shown in figure 13.4.
SCK TxD 0 D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1
1 frame
Figure 13.4 Relation between Output Clock and Transmit Data Phase (Asynchronous Mode)
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Section 13 Serial Communication Interface (SCI)
13.4.4
SCI Initialization (Asynchronous Mode)
Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as shown in figure 13.5. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag in SSR is set to 1. Note that clearing the RE bit to 0 does not initialize the contents of the RDRF, PER, FER, and ORER flags in SSR, or the contents of RDR. When the external clock is used in asynchronous mode, the clock must be supplied even during initialization.
[1] Set the clock selection in SCR. Be sure to clear bits RIE, TIE, TEIE, and MPIE, and bits TE and RE, to 0. When the clock is selected in asynchronous mode, it is output immediately after SCR settings are made. [2] Set the data transfer format in SMR and SCMR. [3] Write a value corresponding to the bit rate to BRR. Not necessary if an external clock is used. [4] Wait at least one bit interval, then set the TE bit or RE bit in SCR to 1. Also set the RIE, TIE, TEIE, and MPIE bits. Setting the TE and RE bits enables the TxD and RxD pins to be used.
[4]
Start initialization
Clear TE and RE bits in SCR to 0
Set CKE1 and CKE0 bits in SCR (TE and RE bits are 0)
[1]
Set data transfer format in SMR and SCMR Set value in BRR Wait
[2]
[3]
No 1-bit interval elapsed? Yes Set TE and RE bits in SCR to 1, and set RIE, TIE, TEIE, and MPIE bits

Figure 13.5 Sample SCI Initialization Flowchart
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Section 13 Serial Communication Interface (SCI)
13.4.5
Serial Data Transmission (Asynchronous Mode)
Figure 13.6 shows an example of the operation for transmission in asynchronous mode. In transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if it is cleared to 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit in SCR is set to 1 at this time, a transmit data empty interrupt request (TXI) is generated. Because the TXI interrupt routine writes the next transmit data to TDR before transmission of the current transmit data has finished, continuous transmission can be enabled. 3. Data is sent from the TxD pin in the following order: start bit, transmit data, parity bit or multiprocessor bit (may be omitted depending on the format), and stop bit. 4. The SCI checks the TDRE flag at the timing for sending the stop bit. 5. If the TDRE flag is 0, the data is transferred from TDR to TSR, the stop bit is sent, and then serial transmission of the next frame is started. 6. If the TDRE flag is 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the "mark state" is entered in which 1 is output. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request is generated. Figure 13.7 shows a sample flowchart for transmission in asynchronous mode.
Start bit 0 D0 D1 Data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 D1 Data D7 Parity Stop bit bit 0/1 1
1
1 Idle state (mark state)
TDRE TEND TXI interrupt Data written to TDR and TXI interrupt request generated TDRE flag cleared to 0 in request generated TXI interrupt service routine
TEI interrupt request generated
1 frame
Figure 13.6 Example of Operation in Transmission in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit)
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Section 13 Serial Communication Interface (SCI)
Initialization Start transmission
[1]
Read TDRE flag in SSR
[2]
[1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. After the TE bit is set to 1, a frame of 1s is output, and transmission is enabled. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. [3] Serial transmission continuation procedure:
No TDRE = 1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0
No All data transmitted? Yes [3] Read TEND flag in SSR
No TEND = 1 Yes No Break output? Yes Clear DR to 0 and set DDR to 1
To continue serial transmission, read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and clear the TDRE flag to 0. However, the TDRE flag is checked and cleared automatically when the DTC is initiated by a transmit data empty interrupt (TXI) request and writes data to TDR. [4] Break output at the end of serial transmission: To output a break in serial transmission, set DDR for the port corresponding to the TxD pin to 1, clear DR to 0, then clear the TE bit in SCR to 0.
[4]
Clear TE bit in SCR to 0
Figure 13.7 Sample Serial Transmission Flowchart
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Section 13 Serial Communication Interface (SCI)
13.4.6
Serial Data Reception (Asynchronous Mode)
Figure 13.8 shows an example of the operation for reception in asynchronous mode. In serial reception, the SCI operates as described below. 1. The SCI monitors the communication line, and if a start bit is detected, performs internal synchronization, receives receive data in RSR, and checks the parity bit and stop bit. 2. If an overrun error (when reception of the next data is completed while the RDRF flag in SSR is still set to 1) occurs, the ORER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. Receive data is not transferred to RDR. The RDRF flag remains to be set to 1. 3. If a parity error is detected, the PER bit in SSR is set to 1 and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. 4. If a framing error (when the stop bit is 0) is detected, the FER bit in SSR is set to 1 and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. 5. If reception finishes successfully, the RDRF bit in SSR is set to 1, and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is generated. Because the RXI interrupt routine reads the receive data transferred to RDR before reception of the next receive data has finished, continuous reception can be enabled.
Start bit 0 D0 D1 Data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 D1 Data D7 Parity Stop bit bit 0/1 0
1
1 Idle state (mark state)
RDRF FER RXI interrupt request generated RDR data read and RDRF flag cleared to 0 in RXI interrupt service routine
ERI interrupt request generated by framing error
1 frame
Figure 13.8 Example of SCI Operation in Reception (Example with 8-Bit Data, Parity, One Stop Bit)
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Section 13 Serial Communication Interface (SCI)
Table 13.11 shows the states of the SSR status flags and receive data handling when a receive error is detected. If a receive error is detected, the RDRF flag retains its state before receiving data. Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the ORER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 13.9 shows a sample flowchart for serial data reception. Table 13.11 SSR Status Flags and Receive Data Handling
SSR Status Flag RDRF* 1 0 0 1 1 0 1 Note: * ORER 1 0 0 1 1 0 1 FER 0 1 0 1 0 1 1 PER 0 0 1 0 1 1 1 Receive Data Lost Transferred to RDR Transferred to RDR Lost Lost Transferred to RDR Lost Receive Error Type Overrun error Framing error Parity error Overrun error + framing error Overrun error + parity error Framing error + parity error Overrun error + framing error + parity error
The RDRF flag retains the state it had before data reception.
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Section 13 Serial Communication Interface (SCI)
Initialization Start reception
[1]
[1] SCI initialization: The RxD pin is automatically designated as the receive data input pin.
[2] [3] Receive error processing and break detection: [2] If a receive error occurs, read the ORER, PER, and FER flags in SSR to identify the error. After performing the Yes appropriate error processing, ensure PER FER ORER = 1 that the ORER, PER, and FER flags are [3] all cleared to 0. Reception cannot be No Error processing resumed if any of these flags are set to 1. In the case of a framing error, a (Continued on next page) break can be detected by reading the value of the input port corresponding to [4] Read RDRF flag in SSR the RxD pin.
Read ORER, PER, and FER flags in SSR No RDRF = 1 Yes Read receive data in RDR, and clear RDRF flag in SSR to 0
[4] SCI status check and receive data read: Read SSR and check that RDRF = 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. [5] Serial reception continuation procedure: To continue serial reception, before the stop bit for the current frame is received, read the RDRF flag, read RDR, and clear the RDRF flag to 0. However, the RDRF flag is cleared automatically when the DTC is initiated by an RXI interrupt and reads data from RDR.
[Legend] : Logical add (OR)
No All data received? Yes Clear RE bit in SCR to 0 [5]
Figure 13.9 Sample Serial Reception Flowchart (1)
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Section 13 Serial Communication Interface (SCI)
[3] Error processing
No ORER = 1 Yes Overrun error processing
No FER = 1 Yes Yes Break? No Framing error processing Clear RE bit in SCR to 0
No PER = 1 Yes Parity error processing
Clear ORER, PER, and FER flags in SSR to 0

Figure 13.9 Sample Serial Reception Flowchart (2)
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Section 13 Serial Communication Interface (SCI)
13.5
Multiprocessor Communication Function
Use of the multiprocessor communication function enables data transfer to be performed among a number of processors sharing communication lines by means of asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data. When multiprocessor communication is carried out, each receiving station is addressed by a unique ID code. The serial communication cycle consists of two component cycles: an ID transmission cycle which specifies the receiving station, and a data transmission cycle for the specified receiving station. The multiprocessor bit is used to differentiate between the ID transmission cycle and the data transmission cycle. If the multiprocessor bit is 1, the cycle is an ID transmission cycle, and if the multiprocessor bit is 0, the cycle is a data transmission cycle. Figure 13.10 shows an example of inter-processor communication using the multiprocessor format. The transmitting station first sends the ID code of the receiving station with which it wants to perform serial communication as data with a 1 multiprocessor bit added. It then sends transmit data as data with a 0 multiprocessor bit added. When data with a 1 multiprocessor bit is received, the receiving station compares that data with its own ID. The station whose ID matches then receives the data sent next. Stations whose ID does not match continue to skip data until data with a 1 multiprocessor bit is again received. The SCI uses the MPIE bit in SCR to implement this function. When the MPIE bit is set to 1, transfer of receive data from RSR to RDR, error flag detection, and setting the RDRF, FER, and ORER status flags in SSR to 1 are prohibited until data with a 1 multiprocessor bit is received. On reception of a receive character with a 1 multiprocessor bit, the MPB bit in SSR is set to 1 and the MPIE bit is automatically cleared, thus normal reception is resumed. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt is generated. When the multiprocessor format is selected, the parity bit setting is invalid. All other bit settings are the same as those in normal asynchronous mode. The clock used for multiprocessor communication is the same as that in normal asynchronous mode.
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Section 13 Serial Communication Interface (SCI)
Transmitting station Serial communication line Receiving station A (ID = 01) Serial data Receiving station B (ID = 02) H'01 (MPB = 1) Receiving station C (ID = 03) H'AA (MPB = 0) Receiving station D (ID = 04)
ID transmission cycle = Data transmission cycle = receiving station Data transmission to specification receiving station specified by ID [Legend] MPB: Multiprocessor bit
Figure 13.10 Example of Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A)
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Section 13 Serial Communication Interface (SCI)
13.5.1
Multiprocessor Serial Data Transmission
Figure 13.11 shows a sample flowchart for multiprocessor serial data transmission. For an ID transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission cycle, clear the MPBT bit in SSR to 0 before transmission. All other SCI operations are the same as those in asynchronous mode.
[1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. After the TE bit is set to 1, a frame of 1s is output, and transmission is enabled. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. Set the MPBT bit in SSR to 0 or 1. Finally, clear the TDRE flag to 0. [3] Serial transmission continuation procedure: To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0. However, the TDRE flag is checked and cleared automatically when the DTC is initiated by a transmit data empty interrupt (TXI) request and writes data to TDR. [4] Break output at the end of serial transmission: To output a break in serial transmission, set port DDR to 1, clear DR to 0, and then clear the TE bit in SCR to 0.
Initialization Start transmission
[1]
Read TDRE flag in SSR
[2]
No TDRE = 1 Yes Write transmit data to TDR and set MPBT bit in SSR
Clear TDRE flag to 0
No All data transmitted? Yes [3]
Read TEND flag in SSR
No TEND = 1 Yes No Break output? Yes [4]
Clear DR to 0 and set DDR to 1
Clear TE bit in SCR to 0

Figure 13.11 Sample Multiprocessor Serial Transmission Flowchart
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Section 13 Serial Communication Interface (SCI)
13.5.2
Multiprocessor Serial Data Reception
Figure 13.13 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in SCR is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. On receiving data with a 1 multiprocessor bit, the receive data is transferred to RDR. An RXI interrupt request is generated at this time. All other SCI operations are the same as in asynchronous mode. Figure 13.12 shows an example of SCI operation for multiprocessor format reception.
Start bit 0 D0 D1 Data (ID1) MPB D7 1 Stop bit 1 Start bit 0 D0 Data (Data 1) D1 D7 Stop MPB bit 0
1
1
1 Idle state (mark state)
MPIE
RDRF
RDR value MPIE = 0 RXI interrupt request (multiprocessor interrupt) generated RDR data read and RDRF flag cleared to 0 in RXI interrupt service routine
ID1 If not this station's ID, MPIE bit is set to 1 again RXI interrupt request is not generated, and RDR retains its state
(a) Data does not match station's ID
1
Start bit 0 D0 D1
Data (ID2) D7
Stop MPB bit 1 1
Start bit 0 D0
Data (Data 2) D1 D7
Stop MPB bit 0
1
1 Idle state (mark state)
MPIE
RDRF
RDR value
ID1 MPIE = 0 RXI interrupt request (multiprocessor interrupt) generated RDR data read and RDRF flag cleared to 0 in RXI interrupt service routine
ID2 Matches this station's ID, so reception continues, and data is received in RXI interrupt service routine
Data 2 MPIE bit set to 1 again
(b) Data matches station's ID
Figure 13.12 Example of SCI Operation in Reception (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)
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Section 13 Serial Communication Interface (SCI)
Initialization Start reception
[1]
[1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] ID reception cycle: Set the MPIE bit in SCR to 1. [3] SCI status check, ID reception and comparison: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and compare it with this station's ID. If the data is not this station's ID, set the MPIE bit to 1 again, and clear the RDRF flag to 0. If the data is this station's ID, clear the RDRF flag to 0. [4] SCI status check and data reception: Read SSR and check that the RDRF flag is set to 1, then read the data in RDR. [5] Receive error processing and break detection: If a receive error occurs, read the ORER and FER flags in SSR to identify the error. After performing the appropriate error processing, ensure that the ORER and FER flags are all cleared to 0. Reception cannot be resumed if either of these flags is set to 1. In the case of a framing error, a break can be detected by reading the RxD pin [4] value.
[Legend] : Logical add (OR)
Set MPIE bit in SCR to 1 Read ORER and FER flags in SSR
[2]
FER ORER = 1 No Read RDRF flag in SSR No RDRF = 1 Yes Read receive data in RDR No This station's ID? Yes Read ORER and FER flags in SSR
Yes
[3]
FER ORER = 1 No Read RDRF flag in SSR
Yes
No RDRF = 1 Yes Read receive data in RDR No All data received? Yes Clear RE bit in SCR to 0 (Continued on next page)
[5] Error processing
Figure 13.13 Sample Multiprocessor Serial Reception Flowchart (1)
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Section 13 Serial Communication Interface (SCI)
[5]
Error processing
No ORER = 1 Yes Overrun error processing
No FER = 1 Yes Yes Break? No Framing error processing Clear RE bit in SCR to 0
Clear ORER, PER, and FER flags in SSR to 0

Figure 13.13 Sample Multiprocessor Serial Reception Flowchart (2)
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Section 13 Serial Communication Interface (SCI)
13.6
Operation in Clock Synchronous Mode
Figure 13.14 shows the general format for clock synchronous communication. In clock synchronous mode, data is transmitted or received in synchronization with clock pulses. One character in transfer data consists of 8-bit data. In data transmission, the SCI outputs data from one falling edge of the synchronization clock to the next. In data reception, the SCI receives data in synchronization with the rising edge of the synchronization clock. After 8-bit data is output, the transmission line holds the MSB state. In clock synchronous mode, no parity or multiprocessor bit is added. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication by use of a common clock. Both the transmitter and the receiver also have a double-buffered structure, so that the next transmit data can be written during transmission or the previous receive data can be read during reception, enabling continuous data transfer.
One unit of transfer data (character or frame) * Synchronization clock LSB Serial data Don't care Note: * High except in continuous transfer Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 MSB Bit 7 Don't care *
Figure 13.14 Data Format in Synchronous Communication (LSB-First) 13.6.1 Clock
Either an internal clock generated by the on-chip baud rate generator or an external synchronization clock input at the SCK pin can be selected, according to the setting of the CKE1 and CKE0 bits in SCR. When the SCI is operated on an internal clock, the synchronization clock is output from the SCK pin. Eight synchronization clock pulses are output in the transfer of one character, and when no transfer is performed the clock is fixed high.
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Section 13 Serial Communication Interface (SCI)
13.6.2
SCI Initialization (Clock Synchronous Mode)
Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as described in a sample flowchart in figure 13.15. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag in SSR is set to 1. However, clearing the RE bit to 0 does not initialize the RDRF, PER, FER, and ORER flags in SSR, or RDR.
Start initialization
[1] Set the clock selection in SCR. Be sure to clear bits RIE, TIE, TEIE, and MPIE, TE and RE to 0. [2] Set the data transfer format in SMR and SCMR.
[1]
Clear TE and RE bits in SCR to 0
Set CKE1 and CKE0 bits in SCR (TE and RE bits are 0)
[3] Write a value corresponding to the bit rate to BRR. This step is not necessary if an external clock is used. [4] Wait at least one bit interval, then set the TE bit or RE bit in SCR to 1. Also set the RIE, TIE TEIE, and MPIE bits. Setting the TE and RE bits enables the TxD and RxD pins to be used.
Set data transfer format in SMR and SCMR Set value in BRR Wait
[2]
[3]
No 1-bit interval elapsed? Yes
Set TE and RE bits in SCR to 1, and set RIE, TIE, TEIE, and MPIE bits
[4]

Note: In simultaneous transmit and receive operations, the TE and RE bits should both be cleared to 0 or set to 1 simultaneously.
Figure 13.15 Sample SCI Initialization Flowchart
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Section 13 Serial Communication Interface (SCI)
13.6.3
Serial Data Transmission (Clock Synchronous Mode)
Figure 13.16 shows an example of SCI operation for transmission in clock synchronous mode. In serial transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if it is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit in SCR is set to 1 at this time, a TXI interrupt request is generated. Because the TXI interrupt routine writes the next transmit data to TDR before transmission of the current transmit data has finished, continuous transmission can be enabled. 3. 8-bit data is sent from the TxD pin synchronized with the output clock when output clock mode has been specified and synchronized with the input clock when use of an external clock has been specified. 4. The SCI checks the TDRE flag at the timing for sending the last bit. 5. If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, and serial transmission of the next frame is started. 6. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, and the TxD pin maintains the output state of the last bit. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request is generated. The SCK pin is fixed high.
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Section 13 Serial Communication Interface (SCI)
Figure 13.17 shows a sample flowchart for serial data transmission. Even if the TDRE flag is cleared to 0, transmission will not start while a receive error flag (ORER, FER, or PER) is set to 1. Make sure to clear the receive error flags to 0 before starting transmission. Note that clearing the RE bit to 0 does not clear the receive error flags.
Transfer direction Synchronization clock Serial data TDRE TEND TXI interrupt request generated Data written to TDR and TDRE flag cleared to 0 in TXI interrupt service routine 1 frame TXI interrupt request generated TEI interrupt request generated Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7
Figure 13.16 Sample SCI Transmission Operation in Clock Synchronous Mode
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Section 13 Serial Communication Interface (SCI)
Initialization Start transmission
[1]
[1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. [3] Serial transmission continuation procedure: To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0. However, the TDRE flag is checked and cleared automatically when the DTC is initiated by a transmit data empty interrupt (TXI) request and writes data to TDR.
Read TDRE flag in SSR
[2]
No TDRE = 1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0
No All data transmitted? Yes [3]
Read TEND flag in SSR
No TEND = 1 Yes Clear TE bit in SCR to 0
Figure 13.17 Sample Serial Transmission Flowchart
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Section 13 Serial Communication Interface (SCI)
13.6.4
Serial Data Reception (Clock Synchronous Mode)
Figure 13.18 shows an example of SCI operation for reception in clock synchronous mode. In serial reception, the SCI operates as described below. 1. The SCI performs internal initialization in synchronization with a synchronization clock input or output, starts receiving data, and stores the receive data in RSR. 2. If an overrun error (when reception of the next data is completed while the RDRF flag is still set to 1) occurs, the ORER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. Receive data is not transferred to RDR. The RDRF flag remains to be set to 1. 3. If reception finishes successfully, the RDRF bit in SSR is set to 1, and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is generated. Because the RXI interrupt routine reads the receive data transferred to RDR before reception of the next receive data has finished, continuous reception can be enabled.
Synchronization clock Serial data RDRF ORER RXI interrupt request generated RDR data read and RDRF flag cleared to 0 in RXI interrupt service routine 1 frame RXI interrupt request generated ERI interrupt request generated by overrun error Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7
Figure 13.18 Example of SCI Receive Operation in Clock Synchronous Mode Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the ORER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 13.19 shows a sample flowchart for serial data reception.
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Section 13 Serial Communication Interface (SCI)
Initialization Start reception
[1]
[1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] [3] Receive error processing: If a receive error occurs, read the ORER flag in SSR, and after performing the appropriate error processing, clear the ORER flag to 0. Transfer cannot be resumed if the ORER flag is set to 1. [4] SCI status check and receive data read: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. [5] Serial reception continuation procedure: To continue serial reception, before the MSB (bit 7) of the current frame is received, reading the RDRF flag, reading RDR, and clearing the RDRF flag to 0 should be finished. However, the RDRF flag is cleared automatically when the DTC is initiated by a receive data full interrupt (RXI) and reads data from RDR.
Read ORER flag in SSR
[2]
Yes ORER = 1 No [3] Error processing (Continued below) Read RDRF flag in SSR [4]
No RDRF = 1 Yes Read receive data in RDR and clear RDRF flag in SSR to 0
No All data received? Yes Clear RE bit in SCR to 0 [5]
[3]
Error processing
Overrun error processing
Clear ORER flag in SSR to 0
Figure 13.19 Sample Serial Reception Flowchart
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Section 13 Serial Communication Interface (SCI)
13.6.5
Simultaneous Serial Data Transmission and Reception (Clock Synchronous Mode)
Figure 13.20 shows a sample flowchart for simultaneous serial transmit and receive operations. After initializing the SCI, the following procedure should be used for simultaneous serial data transmit and receive operations. To switch from transmit mode to simultaneous transmit and receive mode, after checking that the SCI has finished transmission and the TDRE and TEND flags in SSR are set to 1, clear the TE bit in SCR to 0. Then simultaneously set the TE and RE bits to 1 with a single instruction. To switch from receive mode to simultaneous transmit and receive mode, after checking that the SCI has finished reception, clear the RE bit to 0. Then after checking that the RDRF bit in SSR and receive error flags (ORER, FER, and PER) are cleared to 0, simultaneously set the TE and RE bits to 1 with a single instruction.
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Section 13 Serial Communication Interface (SCI)
Initialization Start transmission/reception
[1]
[1]
SCI initialization: The TxD pin is designated as the transmit data output pin, and the RxD pin is designated as the receive data input pin, enabling simultaneous transmit and receive operations. SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. Transition of the TDRE flag from 0 to 1 can also be identified by a TXI interrupt. Receive error processing: If a receive error occurs, read the ORER flag in SSR, and after performing the appropriate error processing, clear the ORER flag to 0. Transmission/reception cannot be resumed if the ORER flag is set to 1. SCI status check and receive data read: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt.
Read TDRE flag in SSR No TDRE = 1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0
[2]
[2]
[3]
Read ORER flag in SSR Yes [3] Error processing
ORER = 1 No
[4]
Read RDRF flag in SSR No RDRF = 1 Yes
[4]
[5] Serial transmission/reception continuation procedure: To continue serial transmission/ Read receive data in RDR, and reception, before the MSB (bit 7) of clear RDRF flag in SSR to 0 the current frame is received, finish reading the RDRF flag, reading RDR, and clearing the RDRF flag to 0. Also, No before the MSB (bit 7) of the current All data received? [5] frame is transmitted, read 1 from the TDRE flag to confirm that writing is Yes possible. Then write data to TDR and clear the TDRE flag to 0. However, the TDRE flag is checked Clear TE and RE bits in SCR to 0 and cleared automatically when the DTC is initiated by a transmit data empty interrupt (TXI) request and writes data to TDR. Similarly, the RDRF flag is cleared automatically when the DTC is initiated by a receive Note: When switching from transmit or receive operation to simultaneous data full interrupt (RXI) and reads transmit and receive operations, first clear the TE bit and RE bit to 0, data from RDR. then set both these bits to 1 simultaneously.
Figure 13.20 Sample Flowchart of Simultaneous Serial Transmission and Reception
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Section 13 Serial Communication Interface (SCI)
13.7
Smart Card Interface Description
The SCI supports the IC card (smart card) interface based on the ISO/IEC 7816-3 (Identification Card) standard as an enhanced serial communication interface function. Smart card interface mode can be selected using the appropriate register. 13.7.1 Sample Connection
Figure 13.21 shows a sample connection between the smart card and this LSI. This LSI communicates with the IC card using a single transmission line. When the SMIF bit in SCMR is set to 1, the TxD and RxD pins are interconnected inside the LSI, which makes the RxD pin function as an I/O pin. Pull up the data transmission line to Vcc using a resistor. Setting the RE and TE bits in SCR to 1 with the IC card not connected enables closed transmission/reception allowing self diagnosis. To supply the IC card with the clock pulses generated by the SCI, input the SCK pin output to the CLK pin of the IC card. A reset signal can be supplied via the output port of this LSI.
VCC TxD RxD SCK Rx (port) This LSI Main unit of the device to be connected
Data line Clock line Reset line
I/O CLK RST IC card
Figure 13.21 Pin Connection for Smart Card Interface 13.7.2 Data Format (Except in Block Transfer Mode)
Figure 13.22 shows the data transfer formats in smart card interface mode. * One frame contains 8-bit data and a parity bit in asynchronous mode. * During transmission, at least 2 etu (elementary time unit: time required for transferring one bit) is secured as a guard time after the end of the parity bit before the start of the next frame. * If a parity error is detected during reception, a low error signal is output for 1 etu after 10.5 etu has passed from the start bit. * If an error signal is sampled during transmission, the same data is automatically re-transmitted after two or more etu.
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Section 13 Serial Communication Interface (SCI)
In normal transmission/reception
Ds
D0
D1
D2
D3
D4
D5
D6
D7
Dp
Output from the transmitting station
When a parity error is generated
Ds
D0
D1
D2
D3
D4
D5
D6
D7
Dp
DE
Output from the transmitting station Output from the receiving station Start bit Data bits Parity bit Error signal
[Legend] Ds: D0 to D7: Dp: DE:
Figure 13.22 Data Formats in Normal Smart Card Interface Mode For communication with the IC cards of the direct convention and inverse convention types, follow the procedure below.
(Z) A Ds Z D0 Z D1 A D2 Z D3 Z D4 Z D5 A D6 A D7 Z Dp (Z) state
Figure 13.23 Direct Convention (SDIR = SINV = O/E = 0) For the direct convention type, logic levels 1 and 0 correspond to states Z and A, respectively, and data is transferred with LSB-first as the start character, as shown in figure 13.23. Therefore, data in the start character in the figure is H'3B. When using the direct convention type, write 0 to both the SDIR and SINV bits in SCMR. Write 0 to the O/E bit in SMR in order to use even parity, which is prescribed by the smart card standard.
(Z) A Ds Z D7 Z D6 A D5 A D4 A D3 A D2 A D1 A D0 Z Dp (Z) state
Figure 13.24 Inverse Convention (SDIR = SINV = O/E = 1)
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Section 13 Serial Communication Interface (SCI)
For the inverse convention type, logic levels 1 and 0 correspond to states A and Z, respectively and data is transferred with MSB-first as the start character, as shown in figure 13.24. Therefore, data in the start character in the figure is H'3F. When using the inverse convention type, write 1 to both the SDIR and SINV bits in SCMR. The parity bit is logic level 0 to produce even parity, which is prescribed by the smart card standard, and corresponds to state Z. Since the SINV bit of this LSI only inverts data bits D7 to D0, write 1 to the O/E bit in SMR to invert the parity bit in both transmission and reception. 13.7.3 Block Transfer Mode
Block transfer mode is different from normal smart card interface mode in the following respects. * If a parity error is detected during reception, no error signal is output. Since the PER bit in SSR is set by error detection, clear the bit before receiving the parity bit of the next frame. * During transmission, at least 1 etu is secured as a guard time after the end of the parity bit before the start of the next frame. * Since the same data is not re-transmitted during transmission, the TEND flag in SSR is set 11.5 etu after transmission start. * Although the ERS flag in block transfer mode displays the error signal status as in normal smart card interface mode, the flag is always read as 0 because no error signal is transferred.
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Section 13 Serial Communication Interface (SCI)
13.7.4
Receive Data Sampling Timing and Reception Margin
Only the internal clock generated by the internal baud rate generator can be used as a communication clock in smart card interface mode. In this mode, the SCI can operate using a basic clock with a frequency of 32, 64, 372, or 256 times the bit rate according to the BCP1 and BCP0 settings (the frequency is always 16 times the bit rate in normal asynchronous mode). At reception, the falling edge of the start bit is sampled using the internal basic clock in order to perform internal synchronization. Receive data is sampled at the 16th, 32nd, 186th and 128th rising edges of the basic clock pulses so that it can be latched at the center of each bit as shown in figure 13.25. The reception margin here is determined by the following formula.
M = (0.5 -
1 ) - (L - 0.5) F - 2N D - 0.5 (1 + F) x 100 [%] N
... Formula (1)
M: Reception margin (%) N: Ratio of bit rate to clock (N = 32, 64, 372, 256) D: Clock duty (D = 0 to 1.0) L: Frame length (L = 10) F: Absolute value of clock rate deviation
Assuming values of F = 0, D = 0.5, and N = 372 in formula (1), the reception margin is determined by the formula below.
M = (0.5 - 1/2 x 372) x 100 [%] = 49.866%
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Section 13 Serial Communication Interface (SCI)
372 clock cycles 186 clock cycles 0 Internal basic clock 185 371 0 185 371 0
Receive data (RxD)
Start bit
D0
D1
Synchronization sampling timing
Data sampling timing
Figure 13.25 Receive Data Sampling Timing in Smart Card Interface Mode (When Clock Frequency is 372 Times the Bit Rate) 13.7.5 Initialization
Before starting transmitting and receiving data, initialize the SCI using the following procedure. Initialization is also necessary before switching from transmission to reception and vice versa. 1. Clear the TE and RE bits in SCR to 0. 2. Clear the error flags ORER, ERS, and PER in SSR to 0. 3. Set the GM, BLK, O/E, BCP1, BCP0, CKS1, and CKS0 bits in SMR appropriately. Also set the PE bit to 1. 4. Set the SMIF, SDIR, and SINV bits in SCMR appropriately. When the SMIF bit is set to 1, the TxD and RxD pins are changed from port pins to SCI pins, placing the pins into high impedance state. 5. Set the value corresponding to the bit rate in BRR. 6. Set the CKE1 and CKE0 bits in SCR appropriately. Clear the TIE, RIE, TE, RE, MPIE, and TEIE bits to 0 simultaneously. When the CKE0 bit is set to 1, the SCK pin is allowed to output clock pulses. 7. Set the TIE, RIE, TE, and RE bits in SCR appropriately after waiting for at least 1 bit interval. Setting prohibited the TE and RE bits to 1 simultaneously except for self diagnosis.
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Section 13 Serial Communication Interface (SCI)
To switch from reception to transmission, first verify that reception has completed, and initialize the SCI. At the end of initialization, RE and TE should be set to 0 and 1, respectively. Reception completion can be verified by reading the RDRF flag or PER and ORER flags. To switch from transmission to reception, first verify that transmission has completed, and initialize the SCI. At the end of initialization, TE and RE should be set to 0 and 1, respectively. Transmission completion can be verified by reading the TEND flag. 13.7.6 Serial Data Transmission (Except in Block Transfer Mode)
Data transmission in smart card interface mode (except in block transfer mode) is different from that in normal serial communication interface mode in that an error signal is sampled and data is re-transmitted. Figure 13.26 shows the data re-transfer operation during transmission. 1. If an error signal from the receiving end is sampled after one frame of data has been transmitted, the ERS bit in SSR is set to 1. Here, an ERI interrupt request is generated if the RIE bit in SCR is set to 1. Clear the ERS bit to 0 before the next parity bit is sampled. 2. For the frame in which an error signal is received, the TEND bit in SSR is not set to 1. Data is re-transferred from TDR to TSR allowing automatic data retransmission. 3. If no error signal is returned from the receiving end, the ERS bit in SSR is not set to 1. In this case, one frame of data is determined to have been transmitted including re-transfer, and the TEND bit in SSR is set to 1. Here, a TXI interrupt request is generated if the TIE bit in SCR is set to 1. Writing transmit data to TDR starts transmission of the next data. Figure 13.28 shows a sample flowchart for transmission. All the processing steps are automatically performed using a TXI interrupt request to activate the DTC. In transmission, the TEND and TDRE flags in SSR are simultaneously set to 1, thus generating a TXI interrupt request when TIE in SCR is set. This activates the DTC by a TXI request thus allowing transfer of transmit data if the TXI interrupt request is specified as a source of DTC activation beforehand. The TDRE and TEND flags are automatically cleared to 0 at data transfer by the DTC. If an error occurs, the SCI automatically re-transmits the same data. During re-transmission, TEND remains as 0, thus not activating the DTC. Therefore, the SCI and DTC automatically transmit the specified number of bytes, including re-transmission in the case of error occurrence. However, the ERS flag is not automatically cleared; the ERS flag must be cleared by previously setting the RIE bit to 1 to enable an ERI interrupt request to be generated at error occurrence. When transmitting/receiving data using the DTC, be sure to set and enable it prior to making SCI settings. See section 7, Data Transfer Controller (DTC) for DTC settings.
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Section 13 Serial Communication Interface (SCI)
nth transfer frame
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE
Retransfer frame
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp (DE)
(n + 1) th transfer frame
Ds D0 D1 D2 D3 D4
TDRE
Transfer from TDR to TSR
TEND
[2]
Transfer from TDR to TSR
Transfer from TDR to TSR
[3]
FER/ERS
[1] [3]
Figure 13.26 Data Re-transfer Operation in SCI Transmission Mode Note that the TEND flag is set in different timings depending on the GM bit setting in SMR, which is shown in figure 13.27.
I/O data TXI (TEND interrupt)
Ds
D0
D1
D2
D3
D4
D5
D6
D7
Dp
DE
Guard time
12.5 etu
GM = 0
11.0 etu
GM = 1
[Legend] Ds: Start bit D0 to D7:Data bits Dp: Parity bit DE: Error signal etu: Element Time Unit (time taken to transfer one bit)
Figure 13.27 TEND Flag Set Timings during Transmission
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Section 13 Serial Communication Interface (SCI)
Start
Initialization Start transmission
ERS = 0? Yes
No
Error processing
No
TEND = 1? Yes
Write data to TDR and clear TDRE flag in SSR to 0
No
All data transmitted?
Yes No ERS = 0? Yes
Error processing
No TEND = 1? Yes
Clear TE bit in SCR to 0
End
Figure 13.28 Sample Transmission Flowchart
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Section 13 Serial Communication Interface (SCI)
13.7.7
Serial Data Reception (Except in Block Transfer Mode)
Data reception in smart card interface mode is identical to that in normal serial communication interface mode. Figure 13.29 shows the data re-transfer operation during reception. 1. If a parity error is detected in receive data, the PER bit in SSR is set to 1. Here, an ERI interrupt request is generated if the RIE bit in SCR is set to 1. Clear the PER bit to 0 before the next parity bit is sampled. 2. For the frame in which a parity error is detected, the RDRF bit in SSR is not set to 1. 3. If no parity error is detected, the PER bit in SSR is not set to 1. In this case, data is determined to have been received successfully, and the RDRF bit in SSR is set to 1. Here, an RXI interrupt request is generated if the RIE bit in SCR is set. Figure 13.30 shows a sample flowchart for reception. All the processing steps are automatically performed using an RXI interrupt request to activate the DTC. In reception, setting the RIE bit to 1 allows an RXI interrupt request to be generated when the RDRF flag is set to 1. This activates DTC by an RXI request thus allowing transfer of receive data if the RXI interrupt request is specified as a source of DTC activate beforehand. The RDRF flag is automatically cleared to 0 at data transfer by DTC. If an error occurs during reception, i.e., either the ORER or PER flag is set to 1, a transmit/receive error interrupt (ERI) request is generated and the error flag must be cleared. If an error occurs, DTC is not activated and receive data is skipped, therefore, the number of bytes of receive data specified in DTC are transferred. Even if a parity error occurs and PER is set to 1 in reception, receive data is transferred to RDR, thus allowing the data to be read. Note: For operations in block transfer mode, see section 13.4, Operation in Asynchronous Mode.
(n + 1) th transfer frame (DE) Ds D0 D1 D2 D3 D4
n th transfer frame
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE RDRF [2] PER [1]
Retransfer frame
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
[3]
[3]
Figure 13.29 Data Re-transfer Operation in SCI Reception Mode
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Section 13 Serial Communication Interface (SCI)
Start
Initialization
Start reception
ORER = 0 and PER = 0?
No
Yes
Error processing
No
RDRF = 1? Yes
Read data from RDR and clear RDRF flag in SSR to 0
No
All data received?
Yes
Clear RE bit in SCR to 0
Figure 13.30 Sample Reception Flowchart
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Section 13 Serial Communication Interface (SCI)
13.7.8
Clock Output Control
Clock output can be fixed using the CKE1 and CKE0 bits in SCR when the GM bit in SMR is set to 1. Specifically, the minimum width of a clock pulse can be specified. Figure 13.31 shows an example of clock output fixing timing when the CKE0 bit is controlled with GM = 1 and CKE1 = 0.
CKE0
SCK
Specified pulse width
Specified pulse width
Figure 13.31 Clock Output Fixing Timing At power-on and transitions to/from software standby mode, use the following procedure to secure the appropriate clock duty ratio. At Power-On: To secure the appropriate clock duty ratio simultaneously with power-on, use the following procedure. 1. Initially, port input is enabled in the high-impedance state. To fix the potential level, use a pull-up or pull-down resistor. 2. Fix the SCK pin to the specified output using the CKE1 bit in SCR. 3. Set SMR and SCMR to enable smart card interface mode. 4. Set the CKE0 bit in SCR to 1 to start clock output.
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Section 13 Serial Communication Interface (SCI)
At Transition from Smart Card Interface Mode to Software Standby Mode: 1. Set the port data register (DR) and data direction register (DDR) corresponding to the SCK pins to the values for the output fixed state in software standby mode. 2. Write 0 to the TE and RE bits in SCR to stop transmission/reception. Simultaneously, set the CKE1 bit to the value for the output fixed state in software standby mode. 3. Write 0 to the CKE0 bit in SCR to stop the clock. 4. Wait for one cycle of the serial clock. In the mean time, the clock output is fixed to the specified level with the duty ratio retained. 5. Make the transition to software standby mode. At Transition from Software Standby Mode to Smart Card Interface Mode: 1. Cancel software standby mode. 2. Write 1 to the CKE0 bit in SCR to start clock output. A clock signal with the appropriate duty ratio is then generated.
Software standby
Normal operation
Normal operation
[1] [2] [3]
[4] [5]
[1]
[2]
Figure 13.32 Clock Stop and Restart Procedure
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Section 13 Serial Communication Interface (SCI)
13.8
13.8.1
Interrupt Sources
Interrupts in Normal Serial Communication Interface Mode
Table 13.12 shows the interrupt sources in normal serial communication interface mode. A different interrupt vector is assigned to each interrupt source, and individual interrupt sources can be enabled or disabled using the enable bits in SCR. When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated. When the TEND flag in SSR is set to 1, a TEI interrupt request is generated. A TXI interrupt can activate the DTC to allow data transfer. The TDRE flag is automatically cleared to 0 at data transfer by the DTC. When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated. When the ORER, PER, or FER flag in SSR is set to 1, an ERI interrupt request is generated. An RXI interrupt can activate the DTC to allow data transfer. The RDRF flag is automatically cleared to 0 at data transfer by the DTC. A TEI interrupt is requested when the TEND flag is set to 1 while the TEIE bit is set to 1. If a TEI interrupt and a TXI interrupt are requested simultaneously, the TXI interrupt has priority for acceptance. However, note that if the TDRE and TEND flags are cleared simultaneously by the TXI interrupt routine, the SCI cannot branch to the TEI interrupt routine later. Table 13.12 SCI Interrupt Sources
Channel 3 Name ERI3 RXI3 TXI3 TEI3 1 ERI1 RXI1 TXI1 TEI1 Interrupt Source Receive error Receive data full Transmit data empty Transmit end Receive error Receive data full Transmit data empty Transmit end Interrupt Flag ORER, FER, PER RDRF TDRE TEND ORER, FER, PER RDRF TDRE TEND DTC Activation Not possible Possible Possible Not possible Not possible Possible Possible Not possible Low Priority High
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Section 13 Serial Communication Interface (SCI)
13.8.2
Interrupts in Smart Card Interface Mode
Table 13.13 shows the interrupt sources in smart card interface mode. A TEI interrupt request cannot be used in this mode. Table 13.13 SCI Interrupt Sources
Channel Name 3 ERI3 RXI3 TXI3 1 ERI1 RXI1 TXI1 Interrupt Source Receive error, error signal detection Receive data full Transmit data empty Receive error, error signal detection Receive data full Transmit data empty Interrupt Flag ORER, PER, ERS RDRF TEND ORER, PER, ERS RDRF TEND DTC Activation Not possible Possible Possible Not possible Possible Possible Low Priority High
Data transmission/reception using the DTC is also possible in smart card interface mode, similar to in the normal SCI mode. In transmission, the TEND and TDRE flags in SSR are simultaneously set to 1, thus generating a TXI interrupt request. This activates the DTC by a TXI interrupt request thus allowing transfer of transmit data if the TXI interrupt request is specified as a source of DTC activation beforehand. The TDRE and TEND flags are automatically cleared to 0 at data transfer by the DTC. If an error occurs, the SCI automatically re-transmits the same data. During retransmission, the TEND flag remains as 0, thus not activating the DTC. Therefore, the SCI and DTC automatically transmit the specified number of bytes, including re-transmission in the case of error occurrence. However, the ERS flag in SSR, which is set at error occurrence, is not automatically cleared; the ERS flag must be cleared by previously setting the RIE bit in SCR to 1 to enable an ERI interrupt request to be generated at error occurrence. When transmitting/receiving data using the DTC, be sure to set and enable the DTC prior to making SCI settings. For DTC settings, see section 7, Data Transfer Controller (DTC). In reception, an RXI interrupt request is generated when the RDRF flag in SSR is set to 1. This activates the DTC by an RXI interrupt request thus allowing transfer of receive data if the RXI interrupt request is specified as a source of DTC activation beforehand. The RDRF flag is automatically cleared to 0 at data transfer by the DTC. If an error occurs, the RDRF flag is not set but the error flag is set. Therefore, the DTC is not activated and an ERI interrupt request is issued to the CPU instead; the error flag must be cleared.
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Section 13 Serial Communication Interface (SCI)
13.9
13.9.1
Usage Notes
Module Stop Mode Setting
SCI operation can be disabled or enabled using the module stop control register. The initial setting is for SCI operation to be halted. Register access is enabled by clearing module stop mode. For details, see section 28, Power-Down Modes. 13.9.2 Break Detection and Processing
When framing error detection is performed, a break can be detected by reading the RxD pin value directly. In a break, the input from the RxD pin becomes all 0s, and so the FER flag in SSR is set, and the PER flag may also be set. Note that, since the SCI continues the receive operation even after receiving a break, even if the FER flag is cleared to 0, it will be set to 1 again. 13.9.3 Mark State and Break Sending
When the TE bit in SCR is 0, the TxD pin is used as an I/O port whose direction (input or output) and level are determined by DR and DDR of the port. This can be used to set the TxD pin to mark state (high level) or send a break during serial data transmission. To maintain the communication line at mark state until TE is set to 1, set both DDR and DR to 1. Since the TE bit is cleared to 0 at this point, the TxD pin becomes an I/O port, and 1 is output from the TxD pin. To send a break during serial transmission, first set DDR to 1 and DR to 0, and then clear the TE bit to 0. When the TE bit is cleared to 0, the transmitter is initialized regardless of the current transmission state, the TxD pin becomes an I/O port, and 0 is output from the TxD pin. 13.9.4 Receive Error Flags and Transmit Operations (Clock Synchronous Mode Only)
Transmission cannot be started when a receive error flag (ORER, FER, or RER) in SSR is set to 1, even if the TDRE flag in SSR is cleared to 0. Be sure to clear the receive error flags to 0 before starting transmission. Note also that the receive error flags cannot be cleared to 0 even if the RE bit in SCR is cleared to 0. 13.9.5 Relation between Writing to TDR and TDRE Flag
Data can be written to TDR irrespective of the TDRE flag status in SSR. However, if the new data is written to TDR when the TDRE flag is 0, that is, when the previous data has not been transferred to TSR yet, the previous data in TDR is lost. Be sure to write transmit data to TDR after verifying that the TDRE flag is set to 1.
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Section 13 Serial Communication Interface (SCI)
13.9.6
Restrictions on Using DTC
When the external clock source is used as a synchronization clock, update TDR by the DTC and wait for at least five clock cycles before allowing the transmit clock to be input. If the transmit clock is input within four clock cycles after TDR modification, the SCI may malfunction (figure 13.33). When using the DTC to read RDR, be sure to set the receive end interrupt source (RXI) as a DTC activation source.
SCK
t
TDRE LSB
Serial data
D0
D1
D2
D3
D4
D5
D6
D7
Note: When external clock is supplied, t must be more than four clock cycles.
Figure 13.33 Sample Transmission using DTC in Clock Synchronous Mode
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Section 13 Serial Communication Interface (SCI)
13.9.7
SCI Operations during Mode Transitions
Transmission: Before making the transition to module stop or software standby mode, stop all transmit operations (TE = TIE = TEIE = 0). TSR, TDR, and SSR are reset. The states of the output pins during each mode depend on the port settings, and the pins output a high-level signal after mode cancellation. If the transition is made during data transmission, the data being transmitted will be undefined. To transmit data in the same transmission mode after mode cancellation, set TE to 1, read SSR, write to TDR, clear TDRE in this order, and then start transmission. To transmit data in a different transmission mode, initialize the SCI first. Figure 13.34 shows a sample flowchart for mode transition during transmission. Figures 13.35 and 13.36 show the pin states during transmission. Before making the transition from the transmission mode using DTC transfer to module stop or software standby mode, stop all transmit operations (TE = TIE = TEIE = 0). Setting TE and TIE to 1 after mode cancellation generates a TXI interrupt request to start transmission using the DTC.
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Section 13 Serial Communication Interface (SCI)
Transmission
All data transmitted? Yes Read TEND flag in SSR
No
[1]
TEND = 1 Yes TE = 0 [2]
No
[1] Data being transmitted is lost halfway. Data can be normally transmitted from the CPU by setting TE to 1, reading SSR, writing to TDR, and clearing TDRE to 0 after mode cancellation; however, if the DTC has been initiated, the data remaining in DTC RAM will be transmitted when TE and TIE are set to 1. [2] Also clear TIE and TEIE to 0 when they are 1.
Make transition to software standby mode etc. Cancel software standby mode etc.
[3]
[3] Module stop mode is included.
Change operating mode? Yes Initialization
No
TE = 1
Start transmission
Figure 13.34 Sample Flowchart for Mode Transition during Transmission
Transition to Software standby Transmission end software standby mode cancelled mode
Transmission start
TE bit SCK output pin TxD output pin
Port input/output Port input/output
High output
Start SCI TxD output
Stop
Port input/output Port
High output SCI TxD output
Port
Figure 13.35 Pin States during Transmission in Asynchronous Mode (Internal Clock)
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Section 13 Serial Communication Interface (SCI)
Transmission start
Transmission end
Transition to Software standby software standby mode cancelled mode
TE bit SCK output pin TxD output pin
Port input/output
Port input/output
Marking output SCI TxD output
Last TxD bit retained
Port input/output Port
High output* SCI TxD output
Port Note: Initialized in software standby mode
Figure 13.36 Pin States during Transmission in Clock Synchronous Mode (Internal Clock) Reception: Before making the transition to module stop or software standby mode, stop reception (RE = 0). RSR, RDR, and SSR are reset. If transition is made during data reception, the data being received will be invalid. To receive data in the same reception mode after mode cancellation, set RE to 1, and then start reception. To receive data in a different reception mode, initialize the SCI first. Figure 13.37 shows a sample flowchart for mode transition during reception.
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Section 13 Serial Communication Interface (SCI)
Reception
Read RDRF flag in SSR
RDRF = 1 Yes Read receive data in RDR
No
[1]
[1] Data being received will be invalid.
[2] Module stop mode is included. RE = 0 [2]
Make transition to software standby mode etc. Cancel software standby mode etc.
Change operating mode? Yes Initialization
No
RE = 1
Start reception
Figure 13.37 Sample Flowchart for Mode Transition during Reception
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Section 13 Serial Communication Interface (SCI)
13.9.8
Notes on Switching from SCK Pins to Port Pins
When SCK pins are switched to port pins after transmission has completed, pins are enabled for port output after outputting a low pulse of half a cycle as shown in figure 13.38.
Low pulse of half a cycle SCK/Port 1. Transmission end Data TE C/A CKE1 CKE0 Bit 6 Bit 7 2. TE = 0 3. C/A = 0 4. Low pulse output
Figure 13.38 Switching from SCK Pins to Port Pins To prevent the low pulse output that is generated when switching the SCK pins to the port pins, specify the SCK pins for input (pull up the SCK/port pins externally), and follow the procedure below with DDR = 1, DR = 1, C/A = 1, CKE1 = 0, CKE1 = 0, and TE = 1. 1. End serial data transmission 2. TE bit = 0 3. CKE1 bit = 1 4. C/A bit = 0 (switch to port output) 5. CKE1 bit = 0
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Section 13 Serial Communication Interface (SCI)
High output SCK/Port 1. Transmission end Data TE C/A 3. CKE1 = 1 CKE1 CKE0 5. CKE1 = 0 Bit 6 Bit 7 2. TE = 0 4. C/A = 0
Figure 13.39 Prevention of Low Pulse Output at Switching from SCK Pins to Port Pins
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Section 14 CRC Operation Circuit (CRC)
Section 14 CRC Operation Circuit (CRC)
This LSI has a cyclic redundancy check (CRC) operation circuit to enhance the reliability of data transfer in high-speed communications, etc. The CRC operation circuit detects errors in data blocks.
14.1
Features
The features of the CRC operation circuit are listed below. * CRC code generated for any desired data length in an 8-bit unit * CRC operation executed on eight bits in parallel * One of three generating polynomials selectable * CRC code generation for LSB-first or MSB-first communication selectable Figure 14.1 is a block diagram of the CRC operation circuit.
CRCCR
Internal bus
Control signal
CRCDIR
CRC code generation circuit
CRCDOR
[Legend] CRCCR: CRC control register CRCDIR: CRC data input register CRCDOR: CRC data output register
Figure 14.1 Block Diagram of CRC Operation Circuit
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Section 14 CRC Operation Circuit (CRC)
14.2
Register Descriptions
The CRC operation circuit has the following registers. * CRC control register (CRCCR) * CRC data input register (CRCDIR) * CRC data output register (CRCDOR) 14.2.1 CRC Control Register (CRCCR)
CRCCR initializes the CRC operation circuit, switches the operation mode, and selects the generating polynomial.
Bit 7 6 to 3 2 Bit Name DORCLR LMS Initial Value 0 All 0 0 R/W W R R/W Description CRCDOR Clear Setting this bit to 1 clears CRCDOR to H0000. Reserved The initial value should not be changed. CRC Operation Switch Selects CRC code generation for LSB-first or MSB-first communication. 0: Performs CRC operation for LSB-first communication. The lower byte (bits 7 to 0) is first transmitted when CRCDOR contents (CRC code) are divided into two bytes to be transmitted in two parts. 1: Performs CRC operation for MSB-first communication. The upper byte (bits 15 to 8) is first transmitted when CRCDOR contents (CRC code) are divided into two bytes to be transmitted in two parts. 1 0 G1 G0 0 0 R/W R/W CRC Generating Polynomial Select These bits select the polynomial. 00: Reserved 01: X + X + X + 1 10: X + X + X + 1 11: X + X + X + 1
16 12 5 16 15 2 8 2
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Section 14 CRC Operation Circuit (CRC)
14.2.2
CRC Data Input Register (CRCDIR)
CRCDIR is an 8-bit readable/writable register, to which the bytes to be CRC-operated are written. The result is obtained in CRCDOR. 14.2.3 CRC Data Output Register (CRCDOR)
CRCDOR is a 16-bit readable/writable register that contains the result of CRC operation when the bytes to be CRC-operated are written to CRCDIR after CRCDOR is cleared. When the CRC operation result is additionally written to the bytes to which CRC operation is to be performed, the CRC operation result will be H'0000 if the data contains no CRC error. When bits 1 and 0 in CRCCR are set to G1 = 0 and G0 = 1, respectively, the lower byte of this register contains the result.
14.3
CRC Operation Circuit Operation
The CRC operation circuit generates a CRC code for LSB-first/MSB-first communications. An 16 12 5 example in which a CRC code for hexadecimal data H'F0 is generated using the X + X + X + 1 polynomial with the G1 and G0 bits in CRCCR set to B'11 is shown below.
1. Write H'83 to CRCCR 7 CRCCR 1 0 0 0 0 0 0 11 CRCDIR 2. Write H'F0 to CRCDIR 7 1 1 1 1 0 0 0 00
CRCDOR clearing 7 CRCDORH CRCDORL 0 0 0 0 0 0 0 0 0 0 0 0 0 00 00 CRCDORH CRCDORL 7 1 1 1 0 1 0 1 0
CRC code generation 0 0 1 1 1 11 11
3. Read from CRCDOR CRC code = H'F78F 4. Serial transmission (LSB first) CRC code 7 1 1 F 1 1 0 1 7 1 0 1 7 1 0 8 0 0 1 1 F 1 0 1 7 1 1 F 1 1 0 0 0 0 Data 0 0 Output
Figure 14.2 LSB-First Data Transmission
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Section 14 CRC Operation Circuit (CRC)
1. Write H'87 to CRCCR 7 CRCCR 1 0 0 0 0 1 0 11
2. Write H'F0 to CRCDIR 7 CRCDIR 1 1 1 1 0 0 0 0 0
7 CRCDORH CRCDORL 0 0 0 0 0 0 0 0
CRCDOR clearing 0 0 0 0 0 00 00 CRCDORH CRCDORL
7 1 0 1 0 1 0 0 1
CRC code generation 0 1 1 1 1 1 1 1 1
3. Read from CRCDOR CRC code = H'EF1F 4. Serial transmission (MSB first) Data 7 Output 1 1 F 1 1 0 0 0 0 0 0 7 1 1 E 1 0 1 1 F 1 CRC code 0 1 7 0 0 1 0 1 1 1 F 1 0 1
Figure 14.3 MSB-First Data Transmission
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Section 14 CRC Operation Circuit (CRC)
1. Serial reception (LSB first) CRC code 7 1 1 F 1 1 0 1 7 1 0 1 7 1 0 8 0 0 1 1 F 1 0 1 7 1 1 F 1 1 0 0 0 0 Data 0 0 Input
2. Write H'83 to CRCCR 7 CRCCR 1 0 0 0 0 0 1 0 1
3. Write H'F0 to CRCDIR 7 CRCDIR 1 1 1 1 0 0 0 0 0
CRCDOR clearing 7 CRCDORH CRCDORL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRCDORH CRCDORL 7 1 1 1 0 1 0 1 0
CRC code generation 0 0 1 1 1 1 1 1 1
4. Write H'8F to CRCDIR 7 CRCDIR 1 0 0 0 1 1 1 0 1
5. Write H'F7 to CRCDIR 7 CRCDIR 1 1 1 1 0 1 1 0 1
CRC code generation 7 CRCDORH CRCDORL 0 1 0 1 0 1 0 1 0 0 0 1 0 1 0 0 1 CRCDORH CRCDORL 7 0 0 0 0 0 0 0 0
CRC code generation 0 0 0 0 0 0 0 0 0
6. Read from CRCDOR CRC code = H'0000 No error
Figure 14.4 LSB-First Data Reception
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Section 14 CRC Operation Circuit (CRC)
1. Serial reception (MSB first) Data 7 Input 1 1 F 1 1 0 0 0 0 0 0 7 1 1 E 1 0 1 1 F 1 CRC code 0 1 7 0 0 1 0 1 1 1 F 1 0 1
2. Write H'87 to CRCCR 7 CRCCR 1 0 0 0 0 1 1 0 1
3. Write H'F0 to CRCDIR 7 CRCDIR 1 1 1 1 0 0 0 0 0
CRCDOR clearing 7 CRCDORH CRCDORL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRCDORH CRCDORL 7 1 0 1 0 1 0 0 1
CRC code generation 0 1 1 1 1 1 1 1 1
4. Write H'EF to CRCDIR 7 CRCDIR 1 1 1 0 1 1 1 0 1
5. Write H'1F to CRCDIR 7 CRCDIR 0 0 0 1 1 1 1 0 1
CRC code generation 7 CRCDORH CRCDORL 0 0 0 0 0 0 1 0 1 0 1 0 1 0 0 1 0 CRCDORH CRCDORL 7 0 0 0 0 0 0 0 0
CRC code generation 0 0 0 0 0 0 0 0 0
6. Read from CRCDOR CRC code = H'0000 No error
Figure 14.5 MSB-First Data Reception
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Section 14 CRC Operation Circuit (CRC)
14.4
Note on CRC Operation Circuit
Note that the sequence to transmit the CRC code differs between LSB-first transmission and MSB-first transmission.
1. CRC code generation After specifying the operation method, write data to CRCDIR in the sequence of (1) (2) (3) (4). 7 0 CRCDIR (1) (2) (3) (4) CRC code generation 0 (5) (6)
7 CRCDORH CRCDORL 2. Transmission data (i) LSB-first transmission
CRC code 7 (5) 07 (6) 07 (4) 07 (3) 07 (2) 07 (1) 0 Output
(ii) MSB-first transmission CRC code 7 Output (1) 07 (2) 07 (3) 07 (4) 07 (5) 07 (6) 0
Figure 14.6 LSB-First and MSB-First Transmit Data
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Section 14 CRC Operation Circuit (CRC)
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Section 15 Serial Communication Interface with FIFO (SCIF)
Section 15 Serial Communication Interface with FIFO (SCIF)
This LSI has single-channel serial communication interface with FIFO buffers (SCIF) that supports asynchronous serial communication. The SCIF enables asynchronous serial communication with standard asynchronous communication LSIs such as a Universal Asynchronous Receiver/Transmitter (UART). The SCIF also has independent 16-stage FIFO buffers for transmission and reception to provide efficient high-speed continuous communication. In addition, the SCIF can be connected to the LPC interface for direct control from the LPC host.
15.1
Features
* Full-duplex communication: The transmitter and receiver are independent, enabling transmission and reception to be executed simultaneously. Both the transmitter and receiver use 16-stage FIFO buffering, enabling continuous transmission and continuous reception of serial data. * On-chip baud rate generator allows any bit rate to be selected * Modem control function * Data length: Selectable from 5, 6, 7, and 8 bits * Parity: Selectable from even parity, odd parity, and no parity * Stop bit length: Selectable from 1, 1.5, and 2 bits * Receive error detection: Parity, overrun, and framing errors * Break detection
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Section 15 Serial Communication Interface with FIFO (SCIF)
Figure 15.1 shows a block diagram of the SCIF.
Internal data bus
Bus interface
LPC interface
FIER FIIR FFCR FLCR FMCR FLSR FMSR FSCR
Modem controller
P25/RI P24/DCD P26/DSR P27/DTR P64/CTS P65/RTS
FTHR
Transmit FIFO (16 bytes) Register transmission/ reception control Transmission (1 byte)
FRBR FTSR P50/TxDF
SCIFCR
SCIF interrupt request
Receive FIFO (16 bytes) Reception (1 byte)
FRSR P51/RxDF
FDLH FDLL
System clock LCLK
Clock selection/ divider circuit
SCLK
Transfer clock
Baud rate generator
[Legend] FRSR: Receive shift register FTSR: Transmitter shift register FRBR: Receive buffer register FTHR: Transmitter holding register FDLH, FDLL: Divisor latch H, L FIER: Interrupt enable register FIIR: Interrupt identification register
FFCR: FLCR: FMCR: FLSR: FMSR: FSCR: SCIFCR:
FIFO control register Line control register Modem control register Line status register Modem status register Scratch pad register SCIF control register
Figure 15.1 Block Diagram of SCIF
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Section 15 Serial Communication Interface with FIFO (SCIF)
15.2
Input/Output Pins
Table 15.1 lists the SCIF input/output pins. Table 15.1 Pin Configuration
Pin Name TxDF RxDF RI DCD DSR DTR CTS RTS Port P50 P51 P25 P24 P26 P27 P64 P65 Input/Output Output Input Input Input Input Output Input Output Function Transmit data output Receive data input Ring indicator input Data carrier detect input Data set ready input Data terminal ready output Transmission permission input Transmission request output
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Section 15 Serial Communication Interface with FIFO (SCIF)
15.3
Register Descriptions
The SCIF has the following registers. The register configuration of the SCIF is shown below. Access to the registers is switched by the SCIFE bit in HICR5 and bit 3 in SUBMSTPBL. For details, see table 15.2. For the SCIF address registers H and L (SCIFADRH, SCIFADRL) and SERIRQ control register 4 (SIRQCR4), see section 19, LPC Interface (LPC). * Host interface control register 5 (HICR5) * Sub-chip module stop control register BL (SUBMSTPBL) * Receive buffer register (FRBR) * Transmitter holding register (FTHR) * Divisor latch L (FDLL) * Interrupt enable register (FIER) * Divisor latch H (FDLH) * Interrupt identification register (FIIR) * FIFO control register (FFCR) * Line control register (FLCR) * Modem control register (FMCR) * Line status register (FLSR) * Modem status register (FMSR) * Scratch pad register (FSCR) * SCIF control register (SCIFCR) * SCIF address register H (SCIFADRH) * SCIF address register L (SCIFADRL) * SERIRQ control register 4 (SIRQCR4) Table 15.2 Register Access
SCIFE Bit in HICR5 Bit 3 in SUBMSTPBL 0 SCIFCR Other than SCIFCR H8S CPU 2 access* H8S CPU 2 access* 0 1 Access disabled Access disabled 0 H8S CPU 2 access* LPC access*
1
1 1 Access disabled LPC access*
1
Notes: 1. When LPC access is set, writing from the H8S CPU is disabled. The read value is H'FF. 2. When H8S CPU access is set, writing from the LPC is disabled. The read value is H'00.
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Section 15 Serial Communication Interface with FIFO (SCIF)
15.3.1
Receive Shift Register (FRSR)
FRSR is a register that receives data and converts serial data input from the RxDF pin to parallel data. It stores the data in the order received from the LSB (bit 0). When one frame of serial data has been received, the data is transferred to FRBR. FRSR cannot be read from the CPU/LPC interface. 15.3.2 Receive Buffer Register (FRBR)
FRBR is an 8-bit read-only register that stores received serial data. It can read data correctly when the DR bit in FLSR is set. When the FIFO is disabled, the data in FRBR must be read before the next data is received. If new data is received before the remaining data is read, the data is overwritten, resulting in an overrun error. When this register is read with the FIFO enabled, the first buffer of the receive FIFO is read. When the receive FIFO becomes full, the subsequent receive data is lost, resulting in an overrun error.
Bit 7 to 0 Bit Name Bit 7 to bit 0 Initial Value All 0 R/W R Description Stores received serial data. The data is 16 bytes when the FIFO is enabled.
15.3.3
Transmitter Shift Register (FTSR)
FTSR is a register that converts parallel data from the TxDF pin to serial data and then transmits the serial data. When one frame transmission of serial data is completed, the next data is transferred from FTHR. The serial data is transmitted from the LSB (bit 0). FTSR cannot be written from the H8S CPU/LPC interface.
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Section 15 Serial Communication Interface with FIFO (SCIF)
15.3.4
Transmitter Holding Register (FTHR)
FTHR is an 8-bit write-only register that stores serial transmit data. It is accessible when the DLAB bit in FLCR is 0. Write transmit data while the THRE bit in FLCR is set to 1. Data can be written to FTHR when the THRE bit is set with the FIFO disabled. If data is written to FTHR when the THRE bit is not set, the data is overwritten. While the THRE bit is set with the FIFO enabled, up to 16 bytes of data can be written. If data is written with the FIFO full, the written data is lost.
Bit 7 to 0 Bit Name Bit 7 to bit 0 Initial Value R/W W Description Stores serial data to be transmitted. The data is 16 bytes when the FIFO is enabled.
15.3.5
Divisor Latch H, L (FDLH, FDLL)
The FDLH and FDLL are registers used to set the baud rate. They are accessible when the DLAB 16 bit in FLCR is 1. Frequency division ranging from 1 to (2 - 1) can be set with these registers. The frequency divider circuit stops when both of FDLH and FDLL are 0 (initial value). * FDLH
Bit 7 to 0 Bit Name Bit 7 to bit 0 Initial Value All 0 R/W R/W Description Upper 8 bits of divisor latch
* FDLL
Bit 7 to 0 Bit Name Bit 7 to bit 0 Initial Value All 0 R/W R/W Description Lower 8 bits of divisor latch
Baud rate = (Clock frequency input to baud rate generator) / (16 x divisor value)
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Section 15 Serial Communication Interface with FIFO (SCIF)
15.3.6
Interrupt Enable Register (FIER)
FIER is a register that enables or disables interrupts. It is accessible when the DLAB bit in FLCR is 0.
Bit 7 to 4 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The initial value should not be changed. 3 EDSSI 0 R/W Modem Status Interrupt Enable 0: Modem status interrupt disabled 1: Modem status interrupt enabled 2 ELSI 0 R/W Receive Line Status Interrupt Enable 0: Receive line status interrupt disabled 1: Receive line status interrupt enabled 1 ETBEI 0 R/W FTHR Empty Interrupt Enable 0: FTHR empty interrupt disabled 1: FTHR empty interrupt enabled 0 ERBFI 0 R/W Receive Data Ready Interrupt Enable A character timeout interrupt is included when the FIFO is enabled. 0: Receive data ready interrupt disabled 1: Receive data ready interrupt enabled
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Section 15 Serial Communication Interface with FIFO (SCIF)
15.3.7
Interrupt Identification Register (FIIR)
FIIR consists of bits that identify interrupt sources. For details, see table 15.3.
Bit 7 6 Bit Name FIFOE1 FIFOE0 Initial Value 0 0 R/W R R Description FIFO Enable 0, 1 These bits indicate the transmit/receive FIFO setting. 00: Transmit/receive FIFOs disabled 11: Transmit/receive FIFOs enabled 5, 4 All 0 R Reserved These bits are always read as 0. The initial value should not be changed. 3 2 1 INTID2 INTID1 INTID0 0 0 0 R R R Interrupt ID2, ID1, ID0 These bits Indicate the interrupt of the highest priority among the pending interrupts. 000: Modem status 001: FTHR empty 010: Receive data ready 011: Receive line status 110: Character timeout (when the FIFO is enabled) 0 INTPEND 1 R Interrupt Pending Indicates whether one or more interrupts are pending. 0: Interrupt pending 1: No interrupt pending
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Section 15 Serial Communication Interface with FIFO (SCIF)
Table 15.3 Interrupt Control Function
FIIR INTID 2 0 0 1 0 1 0 0 1 INTPEND Priority Type of Interrupt 1 0 1 (high) No interrupt Receive line status Interrupt Source None Setting/Clearing of Interrupt Clearing of Interrupt
Overrun error, FLSR read parity error, framing error, break interrupt FRBR read or receive FIFO is below trigger level.
0
1
0
0
2
Receive data ready Receive data remaining, FIFO trigger level
1
1
0
0
2
Character timeout No data is input to FRBR read (with FIFO enabled) or output from the receive FIFO for the 4-character time period while one or more characters remain in the receive FIFO. FTHR empty Modem status FTHR empty FIIR read or FTHR write
0 0
0 0
1 0
0 0
3 4 (low)
CTS, DSR, RI, DCD FMSR read
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Section 15 Serial Communication Interface with FIFO (SCIF)
15.3.8
FIFO Control Register (FFCR)
FFCR is a write-only register that controls transmit/receive FIFOs.
Bit 7 6 Bit Name RCVRTRIG1 RCVRTRIG0 Initial Value R/W Description 0 0 W W Receive FIFO Interrupt Trigger Level 1, 0 These bits set the trigger level of the receive FIFO interrupt. 00: 1 byte 01: 4 bytes 10: 8 bytes 11: 14 bytes 5, 4 3 DMAMODE 0 Reserved These bits cannot be modified. DMA Mode This bit is not supported. The initial value should not be changed. 2 XMITFRST 0 W Transmit FIFO Reset The transmit FIFO data is cleared when 1 is written. However, FTSR data is not cleared. This bit is automatically cleared. 1 RCVRFRST 0 W Receive FIFO Reset The receive FIFO data is cleared when 1 is written. However, FRSR data is not cleared. This bit is automatically cleared. 0 FIFOE 0 W FIFO Enable 0: Transmit/receive FIFOs disabled All bytes of these FIFOs are cleared. 1: Transmit/receive FIFOs enabled
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Section 15 Serial Communication Interface with FIFO (SCIF)
15.3.9
Line Control Register (FLCR)
FLCR sets formats of the transmit/receive data.
Bit 7 Bit Name DLAB Initial Value 0 R/W Description R/W Divisor Latch Address FDLL and FDLH are placed at the same addresses as the FRBR/FTHR and FIER addresses. This bit selects which register is to be accessed. 0: FRBR/FTHR and FIER access enabled 1: FDLL and FDLH access enabled 6 BREAK 0 R/W Break Control Generates a break by driving the serial output signal TxDF low. The break state is released by clearing this bit. 0: Break released 1: Break generated 5 STICK PARITY 0 R Stick Parity This bit is not supported in this LSI. This bit is always read as 0. The initial value should not be changed. 4 EPS 0 R/W Parity Select Selects even or odd parity when the PEN bit is 1. 0: Odd parity 1: Even parity 3 PEN 0 R/W Parity Enable Selects whether to add a parity bit for data transmission and whether to perform a parity check for data reception. 0: No parity bit added/parity check disabled 1: Parity bit added/parity check enabled
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Section 15 Serial Communication Interface with FIFO (SCIF)
Bit 2
Bit Name STOP
Initial Value 0
R/W R/W
Description Stop Bit Specifies the stop bit length for data transmission. For data reception, only the first stop bit is checked regardless of the setting. 0: 1 stop bit 1: 1.5 stop bits (data length: 5 bits) or 2 stop bits (data length: 6 to 8 bits)
1 0
CLS1 CLS0
0 0
R/W R/W
Character Length Select 0, 1 These bits specify transmit/receive character data length. 00: Data length is 5 bits 01: Data length is 6 bits 10: Data length is 7 bits 11: Data length is 8 bits
15.3.10 Modem Control Register (FMCR) FMCR controls output signals.
Bit 7 to 5 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The initial value should not be changed. 4 LOOP BACK 0 R/W Loopback Test The transmit data output is internally connected to the receive data input, and the transmit data output pin (RxDF) becomes 1. The receive data input pin is disconnected from external sources. The four modem control input pins (DSR, CTS, RI, and DCD) are disconnected from external sources, and the pins are internally connected to the four modem control output signals (DTR, RTS, OUT1, and OUT2), respectively. The transmit data is received immediately in loopback mode. Enabling/disabling of interrupts is set by the OUT2LOOP bit in SCIFCR and FIER. 0: Loopback function disabled 1: Loopback function enabled
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Section 15 Serial Communication Interface with FIFO (SCIF)
Bit 3
Bit Name OUT2
Initial Value 0
R/W R/W
Description OUT2 * Normal operation Enables or disables the SCIF interrupt. 0: Interrupt disabled 1: Interrupt enabled * Loopback test Internally connected to the DCD input pin.
2
OUT1
0
R/W
OUT1 * * Normal operation Loopback test No effect on operation Internally connected to the RI input pin.
1
RTS
0
R/W
Request to Send Controls the RTS output. 0: RTS output is high level 1: RTS output is low level
0
DTR
0
R/W
Data Terminal Ready Controls the DTR output. 0: DTR output is high level 1: DTR output is low level
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Section 15 Serial Communication Interface with FIFO (SCIF)
15.3.11 Line Status Register (FLSR) FLSR is a read-only register that indicates the status information of data transmission.
Bit 7 Bit Name RXFIFOERR Initial Value R/W 0 R Description Receive FIFO Error Indicates that at least one data error (parity error, framing error, or break interrupt) has occurred when the FIFO is enabled. 0: No receive FIFO error [Clearing condition] When FRBR is read or FLSR is read while there is no remaining data that could cause an error after an FIFO clear. 1: A receive FIFO error [Setting condition] When at least one data error (parity error, framing error, or break interrupt) has occurred in the FIFO 6 TEMT 1 R Transmitter Empty Indicates whether transmit data remains. * When the FIFO is disabled 0: Transmit data remains in FTHR or FTSR. [Clearing condition] Transmit data is written to FTHR. 1: No transmit data remains in FTHR and FTSR. [Setting condition] When no transmit data remains in FTHR and FTSR. * When the FIFO is enabled 0: Transmit data remains in the transmit FIFO or FTSR. [Clearing condition] Transmit data is written to FTHR. 1: No transmit data remains in the transmit FIFO and FTSR. [Setting condition] When no transmit data remains in the transmit FIFO and FTSR
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Section 15 Serial Communication Interface with FIFO (SCIF)
Bit 5
Bit Name THRE
Initial Value R/W 1 R
Description FTHR Empty Indicates that FTHR is ready to accept new data for transmission. * When the FIFO is enabled 0: Transmit data of one or more bytes remains in the transmit FIFO. [Clearing condition] Transmit data is written to FTHR. 1: No transmit data remains in the transmit FIFO. [Setting condition] When the transmit FIFO becomes empty * When the FIFO is disabled 0: Transmit data remains in FTHR. [Clearing condition] Transmit data is written to FTHR 1: No transmit data in FTHR [Setting condition] When data transfer from FTHR to FTSR is completed
4
BI
0
R
Break Interrupt Indicates detection of the receive data break signal. When the FIFO is enabled, a break interrupt occurs in any receive data in the FIFO, and this bit is set when the receive data is in the first FIFO buffer. Reception of the next data starts after the input receive data becomes mark and a valid start bit is received. 0: Break signal not detected [Clearing condition] FLSR read 1: Break signal detected [Setting condition] When input receive data stays at space (low level) for a reception time exceeding the length of one frame
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Section 15 Serial Communication Interface with FIFO (SCIF)
Bit 3
Bit Name FE
Initial Value R/W 0 R
Description Framing Error Indicates that the stop bit of the receive data is invalid. When the FIFO is enabled, this error occurs in any receive data in the FIFO, and this bit is set when the receive data is in the first FIFO buffer. The UART attempts resynchronization after a framing error occurs. The UART, which assumes that the framing error is due to the next start bit, samples the start bit and treats it as a start bit. 0: No framing error [Clearing condition] FLSR read 1: A framing error [Setting condition] Invalid stop bit in the receive data
2
PE
0
R
Parity Error This bit indicates a parity error in the receive data when the PEN bit in FLCR is 1. When the FIFO is enabled, this error occurs in any receive data in the FIFO, and this bit is set when the receive data is in the first FIFO buffer. 0: No parity error [Clearing condition] FLSR read If this bit is set during an overrun error, read FLSR twice. 1: A parity error [Setting condition] Detection of parity error in receive data
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Section 15 Serial Communication Interface with FIFO (SCIF)
Bit 1
Bit Name OE
Initial Value R/W 0 R
Description Overrun Error Indicates occurrence of an overrun error. * When the FIFO is disabled When reception of the next data has been completed without the receive data in FRBR having been read, an overrun error occurs and the previous data is lost. * When the FIFO is enabled When the FIFO is full and reception of the next data has been completed, an overrun error occurs. The FIFO data is retained, but the last received data is lost. 0: No overrun error [Clearing condition] FLSR read 1: An overrun error [Setting condition] Occurrence of an overrun error
0
DR
0
R
Data Ready Indicates that receive data is stored in FRBR or the FIFO. 0: No receive data [Clearing condition] FRBR is read or all of the FIFO data is read. 1: Receive data remains. [Setting condition] Reception of data
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Section 15 Serial Communication Interface with FIFO (SCIF)
15.3.12 Modem Status Register (FMSR) FMSR is a read-only register that indicates the status of or a change in the modem control pins.
Bit 7 6 5 4 3 Bit Name DCD RI DSR CTS DDCD Initial Value R/W 0 0 0 0 0 R R R R R Description Data Carrier Detect Indicates the inverted state of the DCD input pin. Ring Indicator Indicates the inverted state of the RI input pin. Data Set Ready Indicates the inverted state of the DSR input pin. Clear to Send Indicates the inverted state of the CTS input pin. Delta Data Carrier Indicator Indicates a change in the DCD input signal after the DDCD bit is read. 0: No change in the DCD input signal after FMSR read [Clearing condition] FMSR read 1: A change in the DCD input signal after FMSR read [Setting condition] A change in the DCD input signal 2 TERI 0 R Trailing Edge Ring Indicator Indicates a rise in the RI input signal after the TERI bit is read. 0: No change in the RI input signal after FMSR read [Clearing condition] FMSR read 1: A rise in the RI input signal after FMSR read [Setting condition] A rise in the RI input pin
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Section 15 Serial Communication Interface with FIFO (SCIF)
Bit 1
Bit Name DDSR
Initial Value R/W 0 R
Description Delta Data Set Ready Indicator Indicates a change in the DSR input signal after the DDSR bit is read. 0: No change in the DSR input signal after FMSR read [Clearing condition] FMSR read 1: A change in the DSR input signal after FMSR read [Setting condition] A change in the DSR input signal
0
DCTS
0
R
Delta Clear to Send Indicator Indicates a change in the CTS input signal after the DCTS bit is read. 0: No change in the CTS input signal after FMSR read [Clearing condition] FMSR read 1: A change in the CTS input signal after FMSR read [Setting condition] A change in the CTS input signal
15.3.13 Scratch Pad Register (FSCR) FSCR is not used for SCIF control, but is used to temporarily store program data.
Bit 7 to 0 Bit Name Bit 7 to bit 0 Initial Value R/W All 0 R/W Description Temporarily stores program data.
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Section 15 Serial Communication Interface with FIFO (SCIF)
15.3.14 SCIF Control Register (SCIFCR) SCIFCR controls SCIF operations, and is accessible only from the CPU.
Bit 7 6 Bit Name SCIFOE1 SCIFOE0 Initial Value R/W 0 0 R/W R/W Description These bits enable or disable PORT output of the SCIF. The PORT function differs according to the combination with the SCIF bit in HICR5 of the LPC. For details, see table 15.4. 5 4 OUT2LOOP 0 0 R/W R/W Reserved Do not change the initial value. Enables or disables interrupts during a loopback test. 0: Interrupt enabled 1: Interrupt disabled 3 2 CKSEL1 CKSEL0 0 0 R/W R/W These bits select the clock (SCLK) to be input to the baud rate generator. 00: LCLK divided by 18 01: System clock divided by 11 10: Reserved for LCLK (not selectable) 11: Reserved for system clock (not selectable) 1 SCIFRST 0 R/W Resets the baud rate generator, FRSR, and FTSR. 0: Normal operation 1: Reset 0 REGRST 0 R/W Resets registers (except SCIFCR) accessible from the H8S CPU or LPC interface. 0: Normal operation 1: Reset
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Section 15 Serial Communication Interface with FIFO (SCIF)
Table 15.4 SCIF Output Setting
Bit SCIFE in HICR5 SCIFOE1 SCIFOE0 P65 pin P27 pin P50 pin 0 PORT PORT PORT 0 1 PORT PORT PORT 0 RTS DTR TxDF 0 1 1 PORT PORT TxDF 0 RTS DTR TxDF 0 1 PORT PORT TxDF 0 RTS DTR TxDF 1 1 1 PORT PORT TxDF
Note: P51, P24 to P26, and P64 are input to the SCIF even when the outputs on the P27, P50, and P65 pins are set to PORT.
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Section 15 Serial Communication Interface with FIFO (SCIF)
15.4
15.4.1
Operation
Baud Rate
The SCIF includes a baud rate generator and can set the desired baud rate using registers FDLH, FDLL, and the CKSEL bit in SCIFCR. Table 15.5 shows an example of baud rate settings. Table 15.5 Example of Baud Rate Settings
00 CKSEL1, CKSEL0 Baud rate 50 75 110 300 600 1200 1800 2400 4800 9600 14400 19200 38400 57600 115200 LCLK (33 MHz) divided by 18 FDLH, FDLL (Hex) 0900 0600 0417 0180 00C0 0060 0040 0030 0018 000C 0008 0006 0003 0002 0001 Error (%) -0.54% -0.54% -0.51% -0.54% -0.54% -0.54% -0.54% -0.54% -0.54% -0.54% -0.54% -0.54% -0.54% -0.54% -0.54% 01 System Clock (34 MHz) divided by 11 FDLH, FDLL (Hex) H'0F18 H'0A10 H'06DC H'0284 H'0142 H'00A1 H'006B H'0050 H'0028 H'0014 H'000D H'000A H'0005 H'0003 H'0002 Error (%) -0.01% -0.01% 0.01% -0.01% -0.01% -0.01% 0.30% 0.62% 0.62% 0.62% 0.62% 0.62%
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Section 15 Serial Communication Interface with FIFO (SCIF)
15.4.2
Operation in Asynchronous Communication
Figure 15.2 illustrates the typical format for asynchronous serial communication. One frame consists of a start bit (low level), followed by transmit/receive data (LSB-first: from the least significant bit), a parity bit, and a stop bit (high level). In asynchronous serial communication, the transmission line is usually held high in the mark state (high level). The SCIF monitors the transmission line, and when it detects the space state (low level), recognizes a start bit and starts serial communication. Inside the SCIF, the transmitter and receiver are independent units, enabling full-duplex communication. Both of the transmitter and receiver also have a 16-stage FIFO buffered structure so that data can be read or written during transmission or reception, enabling continuous data transmission and reception.
Idle state (mark state)
1
Serial data
1
0
Start bit 1 bit
D0
D1
D2
D3
D4
D5
D6
D7
0/1
Parity bit 1 bit or none
1
1
Stop bit
Transmit/receive data 5, 6, 7, or 8 bits
1, 1.5, or 2 bits
One unit of transfer data (character or frame)
Figure 15.2 Data Format in Serial Transmission/Reception (Example with 8-Bit Data, Parity and 2 Stop Bits)
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Section 15 Serial Communication Interface with FIFO (SCIF)
15.4.3 (1)
Initialization of the SCIF
Initialization of the SCIF
Use an example of the flowchart in figure 15.3 to initialize the SCIF before transmitting or receiving data.
Start initialization
Clear module stop
[1] Select an input clock with the CKSEL1 and CKSEL0 bits in SCIFCR. Set the SCIF input/ output pins with the SCIFOE1 and SCIFOE0 bits in SCIFCR. [1] [2] Set the DLAB bit in FLCR to 1 to enable access to FDLL and FDLH. [3] The initial value of FDLL and FDLH is 0. Set a value within the range from 1 to 65535. [4] Clear the DLAB bit in FLCR to 0 to disable access to FDLL and FDLH. [5] Select parity with the EPS and PEN bits in FLCR, and set the stop bit with the STOP bit in FLCR. Then, set the data length with the CLS1 and CLS0 bits in FLCR.
Set SCIFCR
Set DLAB bit in FLCR to 1
[2]
Set FDLH and FDLL
[3] [4]
Clear DLAB bit in FLCR to 0
Set data transfer format in FLCR
[5]
FIFOs used?
Yes
Set FIFOE bit in FFCR to 1
[6] [7]
No
Set receive FIFO trigger level in FFCR
Set XMITFRST and RCVRFRST bits in FFCR to 1 to reset FIFOs
[8]
[6] When FIFOs are used, set the FIFOE bit in FFCR to 1.
Set interrupt enable bits in FIER
[9]
[7] Set the receive FIFO trigger level with the RCVRTRIG1 and RCVRTRIG0 bits in FFCR. [8] Set the XMITFRST and RCVRFRST bits in FFCR to 1 to reset the FIFOs. [9] Enable or disable an interrupt with the EDSSI, ELSI, ETBEI, and ERBFI bits in FIER and the OUT2 bit in FMCR.
End of Initialization
Figure 15.3 Example of Initialization Flowchart
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Section 15 Serial Communication Interface with FIFO (SCIF)
(2)
Serial Data Transmission
Figure 15.4 shows an example of the data transmission flowchart.
Initialization
Start transmission
Read THRE flag in FLSR
[1]
[1] Confirm that the THRE flag in FLSR is 1, and write transmit data to FTHR. When FIFOs are used, write 1-byte to 16-byte transmit data. When the OUT2 bit in FMCR and the ETBEI bit in FIER are set to 1, an FTHR empty interrupt occurs. When data is written to FTHR, it is transferred automatically to FTSR. The data is then transmitted from the TxDF pin in the order of the start bit, transmit data, parity bit, and stop bit. [2] Read the TEMT flag in FLSR, and confirm that TEMT is set to 1 to ensure that all transmit data has been transmitted. [3] To output a break at the end of serial transmission, set the BREAK bit in FLCR to 1. After completion of the break time, clear the BREAK bit in FLCR to 0 to clear the break.
THRE = 1?
No
Yes
Write transmit data to FTHR
No
All data written
Yes
Read TEMT flag in FLSR
[2]
TEMT = 1
No
Yes
Break output
No
[3]
Yes
Set BREAK bit in FLCR to 1
Break time completed
Yes
Clear BREAK bit in FLCR to 0
(End of transmission or transmission standby)
Figure 15.4 Example of Data Transmission Flowchart
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Section 15 Serial Communication Interface with FIFO (SCIF)
(3)
Serial Data Reception
Figure 15.5 shows an example of the data reception flowchart.
Initialization
[1]
Confirm that the DR flag in FLSR is 1 to ensure that receive data is in the buffer. When the OUT2 bit in FMCR and the ERBFI bit in FIER are set to 1, a
Start reception
[2]
receive data ready interrupt occurs. Read the RXFIFOERR, BI, FE, PE, and OE flags in FLSR to ensure that no error has occurred. If an error has occurred, perform error processing. When the OUT2 bit in FMCR and the ELSI bit in FIER are
Read DR flag in FLSR
[1]
No DR = 1
[3]
set to 1, a receive line status interrupt occurs. Read the receive data in FRBR. Check the DR flag in FLSR. When the DR flag is cleared to 0 and all data has been read, data reception is complete.
Yes
Read RXFIFOERR, BI, PE and OE flag in FLSR
[2]
[4]
RXFIFOERR = 1, BI = 1, FE = 1, PE = 1, or OE = 1 No
Yes
Error processing
[3]
Read FRBR
Read DR flag in FLSR
[4]
No
DR = 0
Yes
No
All data read
Yes
(End of reception or reception standby)
Figure 15.5 Example of Data Reception Flowchart
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Section 15 Serial Communication Interface with FIFO (SCIF)
15.4.4
Data Transmission/Reception with Flow Control
The following shows examples of data transmission/reception for flow control using CTS and RTS. (1) Initialization
Figure 15.6 shows an example of the initialization flowchart.
Start initialization Clear module stop
[1] Select an input clock with the CKSEL1 and CKSEL0 bits in SCIFCR. Set the SCIF input/output pins with the SCIFOE1 and SCIFOE0 bits in SCIFCR. [2] Set the DLAB bit in FLCR to 1 to enable access to FDLL and FDLH. [3] The initial value of FDLL and FDLH is 0. Set a value within the range from 1 to 65535. [4] Clear the DLAB bit in FLCR to 0 to disable access to FDLL and FDLH. [5] Select parity with the EPS and PEN bits in FLCR, and set the stop bit with the STOP bit in FLCR. Then, set the data length with the CLS1 and CLS0 bits in FLCR. Set the FIFOE bit in FFCR to 1 to enable the FIFO. [6] Set the receive FIFO trigger level with the RCVRTRIG1 and RCVRTRIG0 bits in FFCR. Select the best trigger level to prevent an overflow of the receive FIFO. [7] Set the EDSSI and ERBFI bits in FIER to 1 to enable a modem status interrupt and receive data ready interrupt. [8] Set the RTS bit in FMCR to 1.
Set SCIFCR
[1]
Set DLAB bit in FLCR to 1
[2]
Set FDLH and FDLL
[3] [4]
Clear DLAB bit in FLCR to 0
Set data transfer format in FLCR
[5]
Set FIFO with FFCR
[6]
Set interrupt enable bits in FIER
[7]
Set RTS bit in FMCR to 1
[8]
(Transmission/reception standby flow)
Figure 15.6 Example of Initialization Flowchart
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Section 15 Serial Communication Interface with FIFO (SCIF)
(2)
Data Transmission/Reception Standby
Figure 15.7 shows an example of the data transmission/reception standby flowchart.
Initialization
[1] When a receive data ready interrupt occurs, go to the reception flow. [2] When transmit data exists, go to the transmission flow.
Receive data ready interrupt?
Yes [1]
No Yes Transmit data exists?
[2]
(Reception flow)
No
(Transmission flow)
Figure 15.7 Example of Data Transmission/Reception Standby Flowchart
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Section 15 Serial Communication Interface with FIFO (SCIF)
(3)
Data Transmission
Figure 15.8 shows an example of the data transmission flowchart.
[1] Confirm that the CTS flag in FMSR is 1. Transmission/reception standby [2] Confirm that the THRE flag in FLSR is 1 to ensure that the transmit FIFO is empty. [1] [3] Write up to 16 bytes of transmit data in the transmit FIFO. If the transmit data is 17 bytes or more, return to step [2] to write transmit data in the transmit FIFO again. [4] When all of the data has been written, go to the transmission/reception standby flow.
Read CTS flag in FMSR
CTS = 1 Yes
No
Read THRE flag in FLSR [2] THRE = 1 Yes i0 No
Write transmit data to transmit FIFO
[3]
ii+1 Yes All data written Yes (End of transmission or transmission standby) No i < 16? [4] No
Figure 15.8 Example of Data Transmission Flowchart
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Section 15 Serial Communication Interface with FIFO (SCIF)
(4)
Suspension of Data Transmission
Figure 15.9 shows an example of the data transmission suspension flowchart.
[1] Read the DCTS flag in FMSR in the modem status change interrupt processing routine. If the DCTS flag is set to 1, the transmission suspension processing starts. [2] Suspend data write to the transmit FIFO.
DCTS = 1
Yes
Modem status change interrupt
Read DCTS flag in FMSR
[1]
No
[3] Set the XMITFRST bit in FFCR to 1.
(Other processing)
[2]
Suspend data write to transmit FIFO
[4] Prepare for retransmission of data and go to the transmission flow.
Set XMITFRST bit in FFCR to 1
[3]
Prepare for retransmission
[4]
(Transmission flow)
Figure 15.9 Example of Data Transmission Suspension Flowchart
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Section 15 Serial Communication Interface with FIFO (SCIF)
(5)
Data Reception
Figure 15.10 shows an example of the data reception flowchart.
Receive data ready interrupt
[1] When data is received, a receive data ready interrupt occurs. Go to the data reception flow by using this interrupt trigger. [1] [2] Confirm that the BI, FE, PE, and OE flags in FLSR are all cleared. If any one of these flags is set to 1, perform error processing. [3] Read the receive FIFO. [4] Check the DR flag in FLSR. When the DR flag is cleared and all of the data has been read, data reception is complete.
Read FLSR
BI = 1, FE = 1, PE = 1, or OE = 1
No
Yes
Error processing
[2]
Read receive FIFO
Read FLSR
[3]
DR = 0
[4]
(Transmission/reception standby flow)
Figure 15.10 Example of Data Reception Flowchart
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Section 15 Serial Communication Interface with FIFO (SCIF)
(6)
Suspension of Data Reception
Figure 15.11 shows an example of the data reception suspension flowchart.
[1] When data is received at a trigger level higher than the receive FIFO trigger level specified in the initialization flow, a receive FIFO trigger level interrupt occurs. [2] Clear the RTS bit in FMCR to 0. Read receive FIFO [3] [3] Read the receive FIFO until the DR flag is cleared to 0. [4] Set the RTS bit in FMCR to 1, and then go to the transmission/reception standby flow. No
Receive FIFO trigger level interrupt
[1]
Clear RTS bit in FMCR to 0
[2]
Read FLSR
DR = 0 Yes Set RTS bit in FMCR to 1
[4]
(Transmission/reception standby flow)
Figure 15.11 Example of Data Reception Suspension Flowchart
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Section 15 Serial Communication Interface with FIFO (SCIF)
15.4.5
Data Transmission/Reception Through the LPC Interface
As shown in table 15.2, setting the SCIFE bit in HICR5 to 1 allows registers (except SCIFCR) to be accessed from the LPC interface. The initial setting of SCIFCR by the CPU and setting of the SCIFE bit in HICR5 to 1 enable the flow settings for initialization and data transmission/reception shown in figures 15.3 to 15.5 to be made from the LPC interface. Table 15.6 shows the correspondence between LPC interface I/O address and access to the SCIF registers. For details of the LPC interface settings, see section 19, LPC interface (LPC). Table 15.6 Correspondence Between LPC Interface I/O Address and the SCIF Registers
LPC Interface I/O Address Bits 15 to 3 SCIFADR (bits 15 to 3) Bit 2 0 Bit 1 0 Bit 0 0 R/W R W R/W SCIFADR (bits 15 to 3) 0 0 1 R/W R/W SCIFADR (bits 15 to 3) 0 1 0 R W SCIFADR (bits 15 to 3) SCIFADR (bits 15 to 3) SCIFADR (bits 15 to 3) SCIFADR (bits 15 to 3) SCIFADR (bits 15 to 3) 0 1 1 1 1 1 0 0 1 1 1 0 1 0 1 R/W R/W R R R/W Condition FLCR[7] = 0 FLCR[7] = 0 FLCR[7] = 1 FLCR[7] = 0 FLCR[7] = 1 SCIF Register FRBR FTHR FDLL FIER FDLH FIIR FFCR FLCR FMCR FLSR FMSR FSCR
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Section 15 Serial Communication Interface with FIFO (SCIF)
Table 15.7 shows the register states related to data transmission/reception through the LPC interface. Table 15.7 Register States
Register SCIFADRH SCIFADRL HICR5 SIRQCR4 Bits 15 to 8 Bits 7 to 0 SCIFE Bits 7 to 4 SCSIRQ3 SCSIRQ2 SCSIRQ1 SCSIRQ0 System Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized LPC Reset Retained Retained Retained Retained Retained Retained Retained Retained LPC Shutdown LPC Abort Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
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Section 15 Serial Communication Interface with FIFO (SCIF)
15.5
Interrupt Sources
Table 15.8 lists the interrupt sources. A common interrupt vector is assigned to each interrupt source. When the LPC uses the SCIF, the LPC does not request any interrupts to be sent to the H8S CPU. The SERIRQ signal of the LPC interface transmits an interrupt request to the host. Table 15.8 Interrupt Sources
Interrupt Name Receive line status Receive data ready Character timeout (when FIFO is enabled) FTHR empty Modem status Interrupt Source Overrun error, parity error, framing error, break interrupt Acceptance of receive data, FIFO trigger level No data is input to or output from the receive FIFO for the 4character time period while one or more characters remain in the receive FIFO. FTHR empty CTS, DSR, RI, DCD Low Priority High
Table 15.9 shows the interrupt source, vector address, and interrupt priority. Table 15.9 Interrupt Source, Vector Address, and Interrupt Priority
Interrupt Origin of Interrupt Source SCIF Interrupt Name SCIF (SCIF interrupt) Vector Number 82 Vector Address H'000148
ICR ICRC7
15.6
15.6.1
Usage Note
Power-Down Mode When LCLK is Selected for SCLK
To switch to software standby mode when LCLK divided by 18 has been selected for SCLK, use the shutdown function of the LPC interface to stop LCLK.
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Section 15 Serial Communication Interface with FIFO (SCIF)
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Section 16 Serial Pin Multiplexed Modes
Section 16 Serial Pin Multiplexed Modes
Three serial communication I/F modules (SCIF, SCI_1 and SCI_3) can be configured for five types of COM port assignments and internal connections (serial pin multiplexed modes) in this LSI. Two registers are provided for controlling the serial pin multiplexed modes: serial multiplexed mode register 0 (SMR0) and serial multiplexed mode register 1 (SMR1).
16.1
Features
Internal connection of serial modules to COM ports can be configured to make a software bridge for IPMI applications. * Five serial pin multiplexed modes Mode 0: Each COM port is used for its respective serial communication module: COM1 for SCIF, COM2 for SCI_1 and COM3 for SCI_3 (default mode) Mode 1: COM1 snoop mode with use of SCI_1 and internal registers Mode 2: SCIF-and-SCI_1 bridge mode in which internal registers provide software flow control. Mode 3: COM port switched mode in which COM1 is connected to SCI_1 and COM2 is connected to SCIF. Internal registers provide flow control for SCI_1. Mode 4: SCIF-and-SCI_3 bridge mode providing the same functionality as mode 3. Please refer to section 13, Serial Communication Interface (SCI) for details on SCI_1 and SCI_3, and section 15, Serial Communication Interface with FIFO (SCIF), for details on SCIF.
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Section 16 Multiplex Mode
16.2
Input/Output Pins
Table 16.1 lists input/output pins involved in serial pin multiplexed modes. Table 16.1 Pin Configuration
Module SCIF Symbol TxDF RxDF RI DCD DSR DTR CTS RTS I/O Output Input Input Input Input Output Input Output Function Transmit data Receive data Ring Indicator detect Data carrier detect Data set ready Data terminal ready Transmission permission Transmission request Port Pin P50 P51 P25 P24 P26 P27 P64 P65
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Section 16 Serial Pin Multiplexed Modes
16.3
Register Descriptions
Two registers are provided for serial pin multiplexed modes. Serial multiplexed mode register 0 (SMR0) enables or disables the serial pin multiplexing function, selects a serial pin multiplexed mode out of 5 modes, and provides bits for port monitoring. Serial multiplexed mode register 1 (SMR1) provides bits for port monitoring and controls outputs on the relevant port pins. * Serial multiplexed mode register 0 (SMR0) * Serial multiplexed mode register 1 (SMR1) 16.3.1 Serial Multiplexed Mode Register 0 (SMR0)
Initial Value 0
Bit 7 6 5 4
Bit Name DCD1 RI1 DSR1 SME
R/W R R R R/W
Description Monitors the state of the DCD line in modes 1, 3, and 4. Monitors the state of the RI line in modes 1, 3, and 4. Monitors the state of the DSR line in modes 1, 3, and 4. Serial Pin Multiplex Enable 0: Pin multiplexing disabled 1: Pin multiplexing enabled
3
0
R
Reserved This bit is always read as 0. The write value should always be 0.
2 1 0
SM2 SM1 SM0
0 0 0
R/W R/W R/W
Serial Pin Multiplexed Mode Select These bits select a serial pin multiplexed mode. This selection is only enabled when SME bit is 1. 000: Serial multiplexed mode 0 001: Serial multiplexed mode 1 010: Serial multiplexed mode 2 011: Serial multiplexed mode 3 100: Serial multiplexed mode 4 101: Reserved (Do not modify) 110: Reserved (Do not modify) 111: Reserved (Do not modify)
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Section 16 Multiplex Mode
16.3.2
Serial Multiplexed Mode Register 1 (SMR1)
SMR1 is a register that monitors the port and controls the port output. In mode 2, this register monitors the status of the RTS pin of SCIF.
Bit 7 6 Bit Name CTS1 DTR1 Initial Value 1 R/W R R/W Description Monitors the state of the CTS pin of COM1 in mode 1. Monitors the state of the RTS pin of SCIF in mode 2. Controls the output on the DTR pin of COM1 in modes 3 and 4. 0: 0 is output 1: 1 is output 5 RTS1 1 R/W Controls the output on the RTS pin of COM1. Controls the input on the CTS pin of SCIF in mode 2. 0: 0 is output 1: 1 is output 4 3 2 CTS3 RTS3 1 R R R/W Monitors the state of the RTS pin input of SCIF in mode 4. Reserved Controls the output on the CTS pin of SCIF. 0: 0 is output 1: 1 is output 1,0 R/W Reserved
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Section 16 Serial Pin Multiplexed Modes
16.4
16.4.1
Operation of Serial Pin Multiplexed Modes
Serial Pin Multiplexed Mode 0 (Default; SMR0 Register [bits SM2, SM1, SM0] = [0 0 0])
This mode is the default configuration and each COM port is used for its respective serial communication module: COM1 works with SCIF, COM2 with SCI_1, and COM3 with SCI_3. DCD, RI, DSR, DTR, CTS, RTS, RxDF, and TxDF of SCIF are connected to the corresponding pins of COM1. Tx/Rx of COM1 are tied across to RxDF/TxDF (cross connection). RxD1 and TxD1 of SCI_1 are cross-connected to COM2. RxD3 and TxD3 of SCI_3 are crossconnected to COM3. Figure 16.1 illustrates the pin connection in serial pin multiplexed mode 0.
COM1
COM2
COM3
DCD RI DSR DTR CTS RTS Rx Tx
Rx
Rx P86 RxD3
Tx
P24 P25 P26 P27 P64 P65 P51 P50
P53
P52
DCD RI DSR DTR CTS RTS RxDF TxDF
RxD1
TxD1
SCIF BMC (H8S)
SCI_1
SCI_3
Figure 16.1 Serial Pin Multiplexed Mode 0
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TxD3
P87
Tx
Section 16 Multiplex Mode
16.4.2
Serial Pin Multiplexed Mode 1 (SMR0 Register [bits SM2, SM1, SM0] = [0 0 1])
This mode is "COM1 snoop mode" with use of SCI_1 and internal registers. DCD, RI, DSR, DTR, CTS, RTS, RxDF and TxDF of SCIF are connected to COM1. RxD1 of SCI_1 is connected to RxDF of SCIF internally and TxD1 of SCI_1 is unused. So, COM2 is not available (N/A) and Rx of COM2 is fixed at 1. RxD3 and TxD3 of SCI_3 are cross-connected to COM3. The pin states of DCD, RI, and DSR of COM1 are reflected in bits DCD1, RI1, and DSR1 of the SMR0 register. The pin state of CTS of COM1 is reflected in bit CTS1 of the SMR1 register. Figure 16.2 illustrates the pin connection in serial pin multiplexed mode 1.
DCD RI DSR DTR CTS RTS Rx Tx
SMR0 DCD1 RI1 DSR1
COM1
SMR1 CTS1 DTR1 RTS1 CTS3 RTS3
COM2
COM3
Rx
Rx P86 RxD3
Tx
P24 P25 P26 P27 P64 P65 P51 P50
P53
DCD RI DSR DTR CTS RTS RxDF TxDF
RxD1
TxD1
P52
SCIF BMC (H8S)
SCI_1
SCI_3
Figure 16.2 Serial Pin Multiplexed Mode 1
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TxD3
P87
Tx
Section 16 Serial Pin Multiplexed Modes
16.4.3
Serial Pin Multiplexed Mode 2 (SMR0 Register [bits SM2, SM1, SM0] = [0 1 0])
In this mode, SCIF and SCI_1 are internally connected. COM1 is not available (N/A) and DTR/RTS/Rx of COM1 are fixed at 1. DCD, RI, DSR, DTR, CTS, RTS, RxDF, and TxDF of SCIF are disconnected from COM1. DCD/RI/DSR of SCIF is fixed at 1, and RxDF/TxDF of SCIF are cross-connected to TxD1/RxD1 of SCI_1 internally. COM2 is not available (N/A) and Rx of COM2 is fixed at 1. RxD3 and TxD3 of SCI_3 are connected to Tx and Rx of COM3. The value written to bit RTS1 of the SMR1 register is reflected in the CTS input of SCIF. The state of RTS of SCIF is reflected in bit CTS1 of the SMR1 register. Figure 16.3 illustrates the pin connection in serial pin multiplexed mode 2.
SMR0 DCD1 RI1 DSR1
SMR1 CTS1 DTR1 RTS1 CTS3 RTS3
COM3
Rx P53 P52 P86 RxD3 RxD1 TxD1
SCI_1
P24 P25 P26 P27 P64 P65 P51 P50
1
1
1 Open
DCD RI DSR DTR CTS RTS RxDF TxDF
SCIF BMC (H8S)
SCI_3
Figure 16.3 Serial Pin Multiplexed Mode 2
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TxD3
P87
Tx
Section 16 Multiplex Mode
16.4.4
Serial Pin Multiplexed Mode 3 (SMR0 Register [bits SM2, SM1, SM0] = [0 1 1])
This mode enables the use of COM2 by SCIF and COM1 by SCI_1. Since SCI_1 doesn't use any hardware pins for flow control, emulation is possible using the internal registers. Tx/Rx of COM1 are connected to RxD1/TxD1 of SCI_1, and other COM1 port signals are controlled or monitored through bits in the internal registers. RxDF/TxDF of SCIF are connected to Tx/Rx of COM2 and other SCIF signals are not used. DCD/RI/DSR/CTS of SCIF are fixed at 1. RxD3 and TxD3 of SCI_3 are connected to Tx and Rx of COM3. The states of DCD/RI/DSR of COM1 are reflected in bits DCD1/RI1/DSR1 of the SMR0 register, and CTS of COM1 is reflected in bit CTS1 of the SMR1 register. The values written to bits DTR1/RTS1 of the SMR1 register are output to DTR/RTS of COM1. Figure 16.4 illustrates the pin connection in serial pin multiplexed mode 3.
SMR0 DCD1 RI1 DSR1 COM1 SMR1 CTS1 DTR1 RTS1 CTS3 RTS3 COM2 COM3
DCD RI DSR DTR CTS RTS Rx Tx
Rx
Rx P86 RxD3
Tx
P24 P25 P26 P27 P64 P65 P51 P50
P53
P52
1
1
1 Open 1 Open
DCD RI DSR DTR CTS RTS RxDF TxDF
RxD1
TxD1
SCIF BMC (H8S)
SCI_1
SCI_3
Figure 16.4 Serial Pin Multiplexed Mode 3
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TxD3
P87
Tx
Section 16 Serial Pin Multiplexed Modes
16.4.5
Serial Pin Multiplexed Mode 4 (SMR0 Register [bits SM2, SM1, SM0] = [1 0 0])
Mode 4 provides the same function as mode 3, but the data lines of SCI_3 and SCIF are crossconnected. RxD1/TxD1 of SCI_1 are connected to Tx/Rx of COM1, and internal register bits emulate other signals of COM1. DCD/RI/DSR/CTS of SCIF are fixed at 1. COM2 is not available (N/A) and Rx for COM2 is fixed at 1. COM3 is not available (N/A) and Rx for COM3 is fixed at 1. RxD3/TxD3 of SCI_3 are cross-connected to TxDF/RxDF of SCIF internally. The states of DCD/RI/DSR of COM1 are reflected in bits DCD1/RI1/DSR1 of the SMR0 register, and CTS of COM1 is reflected to CTS1 bit of SMR1 register. The values written to bits DTR1/RTS1 of the SMR1 register are output to DTR/RTS of COM1. The value written to bit RTS3 of SMR1 is reflected in CTS of SCIF, and the state of RTS of SCIF is reflected in bit CTS3 of SMR1, allowing SCI_3 and SCIF to communicate each other with virtual flow control. Figure 16.5 illustrates the pin connection in serial pin multiplexed mode 4.
DCD RI DSR DTR CTS RTS Rx Tx
SMR0 DCD1 RI1 DSR1
COM1
SMR1 CTS1 DTR1 RTS1 CTS3 RTS3
COM2
COM3
Rx
Rx P86 RxD3
Tx
P24 P25 P26 P27 P64 P65 P51 P50
P53
P52
1
1
1 Open
DCD RI DSR DTR CTS RTS RxDF TxDF
RxD1
TxD1
SCIF BMC (H8S)
SCI_1
SCI_3
Figure 16.5 Serial Pin Multiplexed Mode 4
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TxD3
P87
Tx
Section 16 Multiplex Mode
16.5
(a) (b)
Serial Port Pin Configuration
SME = 1: SCI (SCIF) with serial pin multiplexed mode enabled SME = 0: SCI (SCIF) with serial pin multiplexed mode disabled
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Section 17 Synchronous Serial Communication Unit (SSU)
Section 17 Synchronous Serial Communication Unit (SSU)
This LSI has synchronous serial communication unit (SSU) channels. The SSU has master mode in which this LSI outputs clocks as a master device for synchronous serial communication and slave mode in which clocks are input from an external device for synchronous serial communication. Synchronous serial communication can be performed with devices having different clock polarity and clock phase. Figure 17.1 is a block diagram of the SSU.
17.1
Features
* Choice of SSU mode and clock synchronous mode * Choice of master mode and slave mode * Choice of standard mode and bidirectional mode * Synchronous serial communication with devices with different clock polarity and clock phase * Choice of 8/16/32-bit width of transmit/receive data * Full-duplex communication capability The shift register is incorporated, enabling transmission and reception to be executed simultaneously. * Consecutive serial communication * Choice of LSB-first or MSB-first transfer * Choice of clock sources /4, /8, /16, /32, /64, /128, /256, or an external clock * Five interrupt sources Transmit-end, transmit-data-register-empty, receive-data-full, overrun-error, and conflict error * Module stop mode can be set.
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Section 17 Synchronous Serial Communication Unit (SSU)
Figure 17.1 shows a block diagram of the SSU.
Module data bus
Bus interface
Internal data bus
SSCRH SSTDR 0 SSTDR 1 SSTDR 2 SSTDR 3 SSRDR 0 SSRDR 1 SSRDR 2 SSRDR 3 SSCRL SSMR SSER SSSR Control circuit
OEI CEI RXI TXI TEI
SSTRSR
Shiftout Shiftin
Clock Clock selector
/4 /8 /16 /32 /64 /128 /256
Selector
SSI [Legend] SSCRH: SSCRL: SSCR2: SSMR: SSER: SSSR: SSTDR0 to SSTDR3: SSRDR0 to SSRDR3: SSTRSR:
SSO
SCS
SSCK (External clock)
SS control register H SS control register L SS control register 2 SS mode register SS enable register SS status register SS transmit data registers 0 to 3 SS receive data registers 0 to 3 SS shift register
Figure 17.1 Block Diagram of SSU
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Section 17 Synchronous Serial Communication Unit (SSU)
17.2
Input/Output Pins
Table 17.1 shows the SSU pin configuration. Table 17.1 Pin Configuration
Pin Name SSCK SSI SSO SCS I/O I/O I/O I/O I/O Function SSU clock input/output SSU data input/output SSU data input/output SSU chip select input/output
17.3
Register Descriptions
The SSU has the following registers. * SS control register H (SSCRH) * SS control register L (SSCRL) * SS mode register (SSMR) * SS enable register (SSER) * SS status register (SSSR) * SS control register 2 (SSCR2) * SS transmit data register 0 (SSTDR0) * SS transmit data register 1 (SSTDR1) * SS transmit data register 2 (SSTDR2) * SS transmit data register 3 (SSTDR3) * SS receive data register 0 (SSRDR0) * SS receive data register 1 (SSRDR1) * SS receive data register 2 (SSRDR2) * SS receive data register 3 (SSRDR3) * SS shift register (SSTRSR)
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Section 17 Synchronous Serial Communication Unit (SSU)
17.3.1
SS Control Register H (SSCRH)
SSCRH specifies master/slave device selection, bidirectional mode enable, SSO pin output value selection, SSCK pin selection, and SCS pin selection.
Bit 7 Bit Name MSS Initial Value 0 R/W R/W Description Master/Slave Device Select Selects that this module is used in master mode or slave mode. When master mode is selected, transfer clocks are output from the SSCK pin. When the CE bit in SSSR is set, this bit is automatically cleared. 0: Slave mode is selected. 1: Master mode is selected. 6 BIDE 0 R/W Bidirectional Mode Enable Selects that both serial data input pin and output pin are used or one of them is used. However, transmission and reception are not performed simultaneously when bidirectional mode is selected. For details, section 17.4.3, Relationship between Data Input/Output Pins and Shift Register. 0: Standard mode (two pins are used for data input and output) 1: Bidirectional mode (one pin is used for data input and output) 5 0 R/W Reserved This bit is always read as 0. The initial value should not be changed.
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Section 17 Synchronous Serial Communication Unit (SSU)
Bit 4
Bit Name SOL
Initial Value 0
R/W R/W
Description Serial Data Output Value Select The serial data output retains its level of the last bit after completion of transmission. The output level before or after transmission can be specified by setting this bit. When specifying the output level, use the MOV instruction after clearing the SOLP bit to 0. Since writing to this bit during data transmission causes malfunctions, this bit should not be changed. 0: Serial data output is changed to low. 1: Serial data output is changed to high.
3
SOLP
1
R/W
SOL Bit Write Protect When changing the output level of serial data, set the SOL bit to 1 or clear the SOL bit to 0 after clearing the SOLP bit to 0 using the MOV instruction. 0: Output level can be changed by the SOL bit 1: Output level cannot be changed by the SOL bit. This bit is always read as 1.
2
SCKS
0
R/W
SSCK Pin Select Selects that the SSCK pin functions as a port or a serial clock pin. When the SSCK pin is used as a serial clock pin, this bit must be set to 1. 0: Functions as an I/O port. 1: Functions as a serial clock.
1 0
CSS1 CSS0
0 0
R/W R/W
SCS Pin Select Select that the SCS pin functions as a port or SCS input or output. However, when MSS = 0, the SCS pin functions as an input pin regardless of the CSS1 and CSS0 settings. 00: I/O port 01: Function as SCS input 10: Function as SCS automatic input/output (function as SCS input before and after transfer and output a low level during transfer) 11: Function as SCS automatic output (outputs a high level before and after transfer and outputs a low level during transfer)
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Section 17 Synchronous Serial Communication Unit (SSU)
17.3.2
SS Control Register L (SSCRL)
SSCRL selects operating mode, software reset, and transmit/receive data length.
Bit 7 Bit Name Initial Value 0 R/W R/W Description Reserved This bit is always read as 0. The initial value should not be changed. 6 SSUMS 0 R/W Selects transfer mode from SSU mode and clock synchronous mode. 0: SSU mode 1: Clock synchronous mode 5 SRES 0 R/W Software Reset Setting this bit to 1 forcibly resets the SSU internal sequencer. After that, this bit is automatically cleared. The ORER, TEND, TDRE, RDRF, and CE bits in SSSR and the TE and RE bits in SSER are also initialized. Values of other bits for SSU registers are held. To stop transfer, set this bit to 1 to reset the SSU internal sequencer. 4 to 2 All 0 R/W Reserved These bits are always read as 0. The initial value should not be changed. 1 0 DATS1 DATS0 0 0 R/W R/W Transmit/Receive Data Length Select Select serial data length. 00: 8 bits 01: 16 bits 10: 32 bits 11: Setting prohibited
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Section 17 Synchronous Serial Communication Unit (SSU)
17.3.3
SS Mode Register (SSMR)
SSMR selects the MSB first/LSB first, clock polarity, clock phase, and clock rate of synchronous serial communication.
Bit 7 Bit Name MLS Initial Value 0 R/W R/W Description MSB First/LSB First Select Selects that the serial data is transmitted in MSB first or LSB first. 0: LSB first 1: MSB first Clock Polarity Select Selects the SSCK clock polarity. 0: High output in idle mode, and low output in active mode 1: Low output in idle mode, and high output in active mode Clock Phase Select (Only for SSU Mode) Selects the SSCK clock phase. 0: Data changes at the first edge. 1: Data is latched at the first edge. Reserved These bits are always read as 0. The initial value should not be changed. Transfer Clock Rate Select Select the transfer clock rate (prescaler division rate) when an internal clock is selected. 000: Reserved 100: /32 001: /4 101: /64 010: /8 110: /128 011: /16 111: /256
6
CPOS
0
R/W
5
CPHS
0
R/W
4, 3
All 0
R/W
2 1 0
CKS2 CKS1 CKS0
0 0 0
R/W R/W R/W
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Section 17 Synchronous Serial Communication Unit (SSU)
17.3.4
SS Enable Register (SSER)
SSER performs transfer/receive control of synchronous serial communication and setting of interrupt enable.
Bit 7 6 5, 4 Bit Name TE RE Initial Value 0 0 All 0 R/W R/W R/W R/W Description Transmit Enable When this bit is set to 1, transmission is enabled. Receive Enable When this bit is set to 1, reception is enabled. Reserved These bits are always read as 0. The initial value should not be changed. 3 TEIE 0 R/W Transmit End Interrupt Enable When this bit is set to 1, a TEI interrupt request is enabled. 2 TIE 0 R/W Transmit Interrupt Enable When this bit is set to 1, a TXI interrupt request is enabled. 1 RIE 0 R/W Receive Interrupt Enable When this bit is set to 1, an RXI interrupt request and an OEI interrupt request are enabled. 0 CEIE 0 R/W Conflict Error Interrupt Enable When this bit is set to 1, a CEI interrupt request is enabled.
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Section 17 Synchronous Serial Communication Unit (SSU)
17.3.5
SS Status Register (SSSR)
SSSR is a status flag register for interrupts.
Bit 7 Bit Name Initial Value 0 R/W Description Reserved This bit is always read as 0. The initial value should not be changed. Overrun Error If the next data is received while RDRF = 1, an overrun error occurs, indicating abnormal termination. SSRDR stores 1-frame receive data before an overrun error occurs and loses data to be received later. While ORER = 1, consecutive serial reception cannot be continued. Serial transmission cannot be continued, either. [Setting condition] When one byte of the next reception is completed with RDRF = 1 [Clearing condition] When writing 0 after reading ORER = 1 Reserved These bits are always read as 0. The initial value should not be changed. Transmit End [Setting condition] * When the last bit of transmit data is transmitted while the TENDSTS bit in SSCR2 is cleared to 0 and the TDRE bit is set to 1 * After the last bit of transmit data is transmitted while the TENDSTS bit in SSCR2 is set to 1 and the TDRE bit is set to 1 [Clearing conditions] * When writing 0 after reading TEND = 1 * When writing data to SSTDR
6
ORER
0
R/W
5, 4
All 0
R/W
3
TEND
1
R
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Section 17 Synchronous Serial Communication Unit (SSU)
Bit 2
Bit Name TDRE
Initial Value 1
R/W R/W
Description Transmit Data Empty Indicates whether or not SSTDR contains transmit data. [Setting conditions] * When the TE bit in SSER is 0 * When data is transferred from SSTDR to SSTRSR and SSTDR is ready to be written to. [Clearing conditions] * When writing 0 after reading TDRE = 1 * When writing data to SSTDR with TE = 1 Receive Data Register Full Indicates whether or not SSRDR contains receive data. [Setting condition] * When receive data is transferred from SSTRSR to SSRDR after successful serial data reception [Clearing conditions] * When writing 0 after reading RDRF = 1 * When reading receive data from SSRDR Conflict/Incomplete Error Indicates that a conflict error has occurred when 0 is externally input to the SCS pin with SSUMS = 0 (SSU mode) and MSS = 1 (master mode). If the SCS pin level changes to 1 with SSUMS = 0 (SSU mode) and MSS = 0 (slave mode), an incomplete error occurs because it is determined that a master device has terminated the transfer. Data reception does not continue while the CE bit is set to 1. Serial transmission also does not continue. Reset the SSU internal sequencer by setting the SRES bit in SSCRL to 1 before resuming transfer after incomplete error. [Setting condition] * When a low level is input to the SCS pin in master mode (the MSS bit in SSCRH is set to 1) * When the SCS pin is changed to 1 during transfer in slave mode (the MSS bit in SSCRH is cleared to 0) [Clearing condition] * When writing 0 after reading CE = 1
1
RDRF
0
R/W
0
CE
0
R/W
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Section 17 Synchronous Serial Communication Unit (SSU)
17.3.6
SS Control Register 2 (SSCR2)
SSCR2 is a register that enables/disables the open-drain outputs of the SSO, SSI, SSCK, and SCS pins, selects the assert timing of the SCS pin, data output timing of the SSO pin, and set timing of the TEND bit.
Bit 7 Bit Name SDOS Initial Value 0 R/W R/W Description Serial Data Pin Open Drain Select Selects whether the serial data output pin is used as a CMOS or an NMOS open drain output. Pins to output serial data differ according to the register setting. For details, 14.4.3, Relationship between Data Input/Output Pins and Shift Register. 0: CMOS output 1: NMOS open drain output 6 SSCKOS 0 R/W SSCK Pin Open Drain Select Selects whether the SSCK pin is used as a CMOS or an NMOS open drain output. 0: CMOS output 1: NMOS open drain output 5 SCSOS 0 R/W SCS Pin Open Drain Select Selects whether the SCS pin is used as a CMOS or an NMOS open drain output. 0: CMOS output 1: NMOS open drain output 4 TENDSTS 0 R/W Selects the timing of setting the TEND bit (valid in SSU and master mode). 0: Sets the TEND bit when the last bit is being transmitted 1: Sets the TEND bit after the last bit is transmitted
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Section 17 Synchronous Serial Communication Unit (SSU)
Bit 3
Bit Name SCSATS
Initial Value 0
R/W R/W
Description Selects the assertion timing of the SCS pin (valid in SSU and master mode). 0: Min. values of tLEAD and tLAG are 1/2 x tSUcyc 1: Min. values of tLEAD and tLAG are 3/2 x tSUcyc
2
SSODTS
0
R/W
Selects the data output timing of the SSO pin (valid in SSU and master mode) 0: While BIDE = 0, MSS = 1, and TE = 1 or while BIDE = 1, TE = 1, and RE = 0, the SSO pin outputs data 1: While BIDE = 0, MSS = 1, and TE = 1 or while BIDE = 1, TE = 1, and RE = 0, the SSO pin outputs data while the SCS pin is driven low
1, 0
All 0
R/W
Reserved These bits are always read as 0. The initial value should not be changed.
17.3.7
SS Transmit Data Registers 0 to 3 (SSTDR0 to SSTDR3)
SSTDR is an 8-bit register that stores transmit data. When 8-bit data length is selected by bits DATS1 and DATS0 in SSCRL, SSTDR0 is valid. When 16-bit data length is selected, SSTDR0 and SSTDR1 are valid. When 32-bit data length is selected, SSTDR0 to SSTDR3 are valid. When the SSU detects that SSTRSR is empty, it transfers the transmit data written in SSTDR to SSTRSR and starts serial transmission. If the next transmit data has already been written to SSTDR during serial transmission, the SSU performs consecutive serial transmission. Although SSTDR can always be read from or written to by the CPU and DMAC, to achieve reliable serial transmission, write transmit data to SSTDR after confirming that the TDRE bit in SSSR is set to 1.
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Section 17 Synchronous Serial Communication Unit (SSU)
17.3.8
SS Receive Data Registers 0 to 3 (SSRDR0 to SSRDR3)
SSRDR is an 8-bit register that stores receive data. When 8-bit data length is selected by bits DATS1 and DATS0 in SSCRL, SSRDR0 is valid. When 16-bit data length is selected, SSRDR0 and SSRDR1 are valid. When 32-bit data length is selected, SSRDR0 to SSRDR3 are valid. When the SSU has received 1-byte data, it transfers the received serial data from SSTRSR to SSRDR where it is stored. After this, SSTRSR is ready for reception. Since SSTRSR and SSRDR function as a double buffer in this way, consecutive receive operations can be performed. Read SSRDR after confirming that the RDRF bit in SSSR is set to 1. SSRDR is a read-only register, therefore, cannot be written to by the CPU. 17.3.9 SS Shift Register (SSTRSR)
SSTRSR is a shift register that transmits and receives serial data. When data is transferred from SSTDR to SSTRSR, bit 0 of transmit data is bit 0 in the SSTDR contents (MLS = 0: LSB first communication) and is bit 7 in the SSTDR contents (MLS = 1: MSB first communication). The SSU transfers data from the LSB (bit 0) in SSTRSR to the SSO pin to perform serial data transmission. In reception, the SSU sets serial data that has been input via the SSI pin in SSTRSR from the LSB (bit 0). When 1-byte data has been received, the SSTRSR contents are automatically transferred to SSRDR. SSTRSR cannot be directly accessed by the CPU.
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Section 17 Synchronous Serial Communication Unit (SSU)
17.4
17.4.1
Operation
Transfer Clock
A transfer clock can be selected from eight internal clocks and an external clock. When using this module, set the SCKS bit in SSCRH to 1 to select the SSCK pin as a serial clock. When the MSS bit in SSCRH is 1, an internal clock is selected and the SSCK pin is used as an output pin. When transfer is started, the clock with the transfer rate set by bits CKS2 to CKS0 in SSMR is output from the SSCK pin. When MSS = 0, an external clock is selected and the SSCK pin is used as an input pin. 17.4.2 Relationship of Clock Phase, Polarity, and Data
The relationship of clock phase, polarity, and transfer data depends on the combination of the CPOS and CPHS bits in SSMR. Figure 17.2 shows the relationship. When SSUMS = 1, the CPHS setting is invalid although the CPOS setting is valid. Setting the MLS bit in SSMR selects that MSB or LSB first communication. When MLS = 0, data is transferred from the LSB to the MSB. When MLS = 1, data is transferred from the MSB to the LSB.
(1) When CPHS = 0 SCS SSCK (CPOS = 0) SSCK (CPOS = 1) SSI, SSO (2) When CPHS = 1 SCS SSCK (CPOS = 0) SSCK (CPOS = 1) SSI, SSO Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
Figure 17.2 Relationship of Clock Phase, Polarity, and Data
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Section 17 Synchronous Serial Communication Unit (SSU)
17.4.3
Relationship between Data Input/Output Pins and Shift Register
The connection between data input/output pins and the SS shift register (SSTRSR) depends on the combination of the MSS and BIDE bits in SSCRH and the SSUMS bit in SSCRL. Figure 17.3 shows the relationship. The SSU transmits serial data from the SSO pin and receives serial data from the SSI pin when operating with BIDE = 0 and MSS = 1 (standard, master mode) (see figure 17.3 (1)). The SSU transmits serial data from the SSI pin and receives serial data from the SSO pin when operating with BIDE = 0 and MSS = 0 (standard, slave mode) (see figure 17.3 (2)). The SSU transmits and receives serial data from the SSO pin regardless of master or slave mode when operating with BIDE = 1 (bidirectional mode) (see figures 17.3 (3) and (4)). However, even if both the TE and RE bits are set to 1, transmission and reception are not performed simultaneously. Either the TE or RE bit must be selected. The SSU transmits serial data from the SSO pin and receives serial data from the SSI pin when operating with SSUMS = 1. The SSCK pin outputs the internal clock when MSS = 1 and function as an input pin when MSS = 0 (see figures 17.3 (5) and (6)).
(1) When SSUMS = 0, BIDE = 0 (standard mode), MSS = 1, TE = 1, and RE = 1 SSCK Shift register (SSTRSR) SSO SSI (4) When SSUMS = 0, BIDE = 1 (bidirectional mode), MSS = 1, and either TE or RE = 1 SSCK Shift register (SSTRSR) SSO SSI (5) When SSUMS = 1 and MSS = 1 SSCK Shift register (SSTRSR) SSO SSI
(2) When SSUMS = 0, BIDE = 0 (standard mode), MSS = 0, TE = 1, and RE = 1 SSCK Shift register (SSTRSR) SSO SSI (3) When SSUMS = 0, BIDE = 1 (bidirectional mode), MSS = 0, and either TE or RE = 1 SSCK Shift register (SSTRSR) SSO SSI (6) When SSUMS = 1 and MSS = 0 SSCK Shift register (SSTRSR) SSO SSI
Figure 17.3 Relationship between Data Input/Output Pins and the Shift Register
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Section 17 Synchronous Serial Communication Unit (SSU)
17.4.4
Communication Modes and Pin Functions
The SSU switches the input/output pin (SSI, SSO, SSCK, and SCS) functions according to the communication modes and register settings. When a pin is used as an input pin, set the corresponding bit in the input buffer control register (ICR) to 1. The relationship of communication modes and input/output pin functions are shown in tables 17.2 to 17.4. Table 17.2 Communication Modes and Pin States of SSI and SSO Pins
Communication Mode SSU communication mode Register Setting SSUMS 0 BIDE 0 MSS 0 TE 0 1 RE 1 0 1 1 0 1 1 0 1 SSU (bidirectional) 0 communication mode 1 0 0 1 1 0 1 Clock synchronous 1 communication mode 0 0 0 1 1 0 1 0 1 0 1 1 0 1 [Legend] : Not used as SSU pin (can be used as I/O port) 1 0 1 SSI Output Output Input Input Input Input Input Input Pin State SSO Input Input Output Output Input Output Input Output Output Output Output Output
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Section 17 Synchronous Serial Communication Unit (SSU)
Table 17.3 Communication Modes and Pin States of SSCK Pin
Communication Mode SSU communication mode Register Setting SSUMS 0 MSS 0 SCKS 0 1 1 0 1 Clock synchronous 1 communication mode 0 0 1 1 [Legend] : Not used as SSU pin (can be used as I/O port) 0 1 Pin State SSCK Input Output Input Output
Table 17.4 Communication Modes and Pin States of SCS Pin
Communication Mode SSU communication mode Register Setting SSUMS 0 MSS 0 1 CSS1 x 0 0 1 1 Clock synchronous 1 communication mode x x CSS0 x 0 1 0 1 x Pin State SCS Input Input Automatic input/output Output
[Legend] x: Don't care : Not used as SSU pin (can be used as I/O port)
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Section 17 Synchronous Serial Communication Unit (SSU)
17.4.5
SSU Mode
In SSU mode, data communications are performed via four lines: clock line (SSCK), data input line (SSI or SSO), data output line (SSI or SSO), and chip select line (SCS). In addition, the SSU supports bidirectional mode in which a single pin functions as data input and data output lines. (1) Initial Settings in SSU Mode
Figure 17.4 shows an example of the initial settings in SSU mode. Before data transfer, clear both the TE and RE bits in SSER to 0 to set the initial values. Note: Before changing operating modes and communications formats, clear both the TE and RE bits to 0. Although clearing the TE bit to 0 sets the TDRE bit to 1, clearing the RE bit to 0 does not change the values of the RDRF and ORER bits and SSRDR. Those bits retain the previous values.
Start setting initial values
Clear TE and RE bits in SSER to 0
[1] When the pin is used as an input. [2] Specify master/slave mode selection, bidirectional mode enable, SSO pin output value selection, SSCK pin selection, and SCS pin selection. [3] Selects SSU mode and specify transmit/receive data length. [4] Specify MSB first/LSB first selection, clock polarity selection, clock phase selection, and transfer clock rate selection.
[1]
Set a bit in ICR to 1
[2]
Specify MSS, BIDE, SOL, SCKS, CSS1, and CSS0 bits in SSCRH
[3]
Clear SSUMS in SSCRH to 0 and specify bits DATS1 and DATS0
[5] Enables/disables interrupt request to the CPU.
[4]
Specify MLS, CPOS, CPHS, CKS2, CKS1, and CKS0 bits in SSMR
[5]
Specify TEIE, TIE, RIE, and CEIE bits in SSER
End
Figure 17.4 Example of Initial Settings in SSU Mode
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Section 17 Synchronous Serial Communication Unit (SSU)
(2)
Data Transmission
Figure 17.5 shows an example of transmission operation, and figure 17.6 shows a flowchart example of data transmission. When transmitting data, the SSU operates as shown below. In master mode, the SSU outputs a transfer clock and data. In slave mode, when a low level signal is input to the SCS pin and a transfer clock is input to the SSCK pin, the SSU outputs data in synchronization with the transfer clock. Writing transmit data to SSTDR after the TE bit is set to 1 clears the TDRE bit in SSSR to 0, and the SSTDR contents are transferred to SSTRSR. After that, the SSU sets the TDRE bit to 1 and starts transmission. At this time, if the TIE bit in SSER is set to 1, a TXI interrupt is generated. When 1-frame data has been transferred with TDRE = 0, the SSTDR contents are transferred to SSTRSR to start the next frame transmission. When the 8th bit of transmit data has been transferred with TDRE = 1, the TEND bit in SSSR is set to 1 and the state is retained. At this time, if the TEIE bit is set to 1, a TEI interrupt is generated. After transmission, the output level of the SSCK pin is fixed high when CPOS = 0 and low when CPOS = 1. While the ORER bit in SSSR is set to 1, transmission is not performed. Check that the ORER bit is cleared to 0.
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Section 17 Synchronous Serial Communication Unit (SSU)
(1) When 8-bit data length is selected (SSTDR0 is valid) with CPOS = 0 and CPHS = 0 SCS SSCK SSO
Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
1 frame
1 frame
SSTDR0 (LSB first transmission)
SSTDR0 (MSB first transmission)
TDRE TEND LSI operation generated User operation Data written to SSTDR0
TXI interrupt TEI interrupt generated TXI interrupt generated Data written to SSTDR0 TEI interrupt generated
(2) When 16-bit data length is selected (SSTDR0 and SSTDR1 are valid) with CPOS = 0 and CPHS = 0 SCS SSCK SSO (LSB first) SSO (MSB first) TDRE TEND LSI operation TXI interrupt generated User operation Data written to SSTDR0 and SSTDR1
TEI interrupt generated
Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
1 frame
SSTDR1
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5
SSTDR0
Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SSTDR0
SSTDR1
(3) When 32-bit data length is selected (SSTDR0, SSTDR1, SSTDR2, and SSTDR3 are valid) with CPOS = 0 and CPHS = 0 SCS SSCK SSO (LSB first) SSO (MSB first) TDRE TEND LSI operation TXI interrupt generated TEI interrupt generated User operation Data written to SSTDR0, SSTDR1, SSTDR2, and SSTDR3
Bit 0 to Bit 7 Bit 0 to Bit 7 Bit 0 to Bit 7 Bit 0 to Bit 7
1 frame
SSTDR3 Bit 7 to Bit 0
SSTDR2 Bit 7 to Bit 0
SSTDR1 Bit 7 to Bit 0
SSTDR0 Bit 7 to Bit 0
SSTDR0
SSTDR1
SSTDR2
SSTDR3
Figure 17.5 Example of Transmission Operation (SSU Mode)
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Section 17 Synchronous Serial Communication Unit (SSU)
Start [1] Initial setting TE = 1 (transmission enabled) [2] Read TDRE in SSSR TDRE = 1? Yes Write transmit data to SSTDR TDRE automatically cleared
Data transferred from SSTDR to SSTRSR
[1] Initial setting: Specify the transmit data format. [2] Check that the SSU state and write transmit data: Write transmit data to SSTDR after reading and confirming that the TDRE bit is 1. The TDRE bit is automatically cleared to 0 and transmission is started by writing data to SSTDR. No [3] Procedure for consecutive data transmission: To continue data transmission, confirm that the TDRE bit is 1 meaning that SSTDR is ready to be written to. After that, data can be written to SSTDR. The TDRE bit is automatically cleared to 0 by writing data to SSTDR. [4] Procedure for data transmission end: To end data transmission, confirm that the TEND bit is cleared to 0. After completion of transmitting the last bit, clear the TE bit to 0.
Set TDRE to 1 to start transmission [3]
Consecutive data transmission?
Yes
No Read TEND in SSSR TEND = 1? Yes Clear TEND to 0 Confirm that TEND is cleared to 0 [4] One bit time quantum elapsed? Yes Clear TE in SSER to 0 End transmission Note: Hatching boxes represent SSU internal operations. No No
Figure 17.6 Flowchart Example of Data Transmission (SSU Mode)
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Section 17 Synchronous Serial Communication Unit (SSU)
(3)
Data Reception
Figure 17.7 shows an example of reception operation, and figure 17.8 shows a flowchart example of data reception. When receiving data, the SSU operates as shown below. After setting the RE bit to 1 and dummy-reading SSRDR, the SSU starts data reception. In master mode, the SSU outputs a transfer clock and receives data. In slave mode, when a low level signal is input to the SCS pin and a transfer clock is input to the SSCK pin, the SSU receives data in synchronization with the transfer clock. When 1-frame data has been received, the RDRF bit in SSSR is set to 1 and the receive data is stored in SSRDR. At this time, if the RIE bit in SSER is set to 1, an RXI interrupt is generated. The RDRF bit is automatically cleared to 0 by reading SSRDR. When the RDRF bit has been set to 1 at the 8th rising edge of the transfer clock, the ORER bit in SSSR is set to 1. This indicates that an overrun error (OEI) has occurred. At this time, data reception is stopped. While the ORER bit in SSSR is set to 1, reception is not performed. To resume the reception, clear the ORER bit to 0.
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Section 17 Synchronous Serial Communication Unit (SSU)
(1) When 8-bit data length is selected (SSRDR0 is valid) with CPOS = 0 and CPHS = 0 SCS 1 frame 1 frame
SSCK SSI
Bit Bit Bit Bit Bit Bit Bit Bit 0 1 2 3 4 5 6 7
SSTDR0 (LSB first transmission)
Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0
SSTDR0 (MSB first transmission)
RDRF LSI operation User operation Dummy-read SSRDR0
RXI interrupt generated RXI interrupt generated
Read SSRDR0
(2) When 16-bit data length is selected (SSRDR0 and SSRDR1 are valid) with CPOS = 0 and CPHS = 0 SCS 1 frame
SSCK SSI (LSB first) SSI (MSB first)
Bit Bit Bit Bit Bit Bit Bit Bit 0 1 2 3 4 5 6 7
SSRDR1
Bit Bit Bit Bit Bit Bit Bit Bit 0 1 2 3 4 5 6 7
SSRDR0
Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0
SSRDR0
Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0
SSRDR1
RDRF LSI operation User operation Dummy-read SSRDR0 and SSRDR1
RXI interrupt generated
(3) When 32-bit data length is selected (SSRDR0, SSRDR1, SSRDR2, and SSRDR3 are valid) with CPOS = 0 and CPHS = 0 SCS
SSCK SSI (LSB first) SSI (MSB first) RDRF LSI operation User operation Dummy-read SSRDR0 RXI interrupt generated
Bit 0 to Bit Bit 7 0 to Bit Bit 7 0 to Bit 7 Bit 0 to Bit 7
SSRDR3
SSRDR2
SSRDR1
SSRDR0
Bit 7
to
Bit Bit 0 7
to
Bit 0
Bit 7
to
Bit Bit 0 7
to
Bit 0
SSRDR0
SSRDR1
SSRDR2
SSRDR3
Figure 17.7 Example of Reception Operation (SSU Mode)
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Section 17 Synchronous Serial Communication Unit (SSU)
Start [1] [1] Initial setting RE = 1 (reception started) [2] Dummy-read SSRDR [2] Initial setting: Specify the receive data format. Start reception: When SSRDR is dummy-read with RE = 1, reception is started.
Read SSSR No RDRF = 1? Yes ORER = 1? No [4] Consecutive data reception? Yes Read received data in SSRDR RDRF automatically cleared No Yes [3]
[3], [6] Receive error processing: When a receive error occurs, execute the designated error processing after reading the ORER bit in SSSR. After that, clear the ORER bit to 0. While the ORER bit is set to 1, transmission or reception is not resumed. [4] To continue single reception: When continuing single reception, wait for time of tSUcyc while the RDRF flag is set to 1 and then read receive data in SSRDR. The next single reception starts after reading receive data in SSRDR. To complete reception: To complete reception, read receive data after clearing the RE bit to 0. When reading SSRDR without clearing the RE bit, reception is resumed.
[5]
[5]
RE = 0 Read receive data in SSRDR End reception
[6]
Overrun error processing Clear ORER in SSSR End reception
Note: Hatching boxes represent SSU internal operations.
Figure 17.8 Flowchart Example of Data Reception (SSU Mode) (4) Data Transmission/Reception
Figure 17.9 shows a flowchart example of simultaneous transmission/reception. The data transmission/reception is performed combining the data transmission and data reception as mentioned above. The data transmission/reception is started by writing transmit data to SSTDR with TE = RE = 1.
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Section 17 Synchronous Serial Communication Unit (SSU)
Before switching transmission mode (TE = 1) or reception mode (RE = 1) to transmission/reception mode (TE = RE = 1), clear the TE and RE bits to 0. When starting the transfer, confirm that the TEND, RDRF, and ORER bits are cleared to 0 before setting the TE or RE bit to 1.
Start [1] Initial setting Transmission/reception started (TE = 1, RE = 1) [2] Read TDRE in SSSR. TDRE = 1? Yes Write transmit data to SSTDR TDRE automatically cleared Data transferred from SSTDR to SSTRSR TDRE set to 1 to start transmission Read SSSR [3] No RDRF = 1? Yes ORER = 1? No Read receive data in SSRDR RDRF automatically cleared Consecutive data transmission/reception? No Clear TEND in SSSR to 0 Clear TE and RE in SSER to 0 Yes [5] Yes [4] No
[1] Initial setting: Specify the transmit/receive data format. [2] Check the SSU state and write transmit data: Write transmit data to SSTDR after reading and confirming that the TDRE bit in SSSR is 1. The TDRE bit is automatically cleared to 0 and transmission/ reception is started by writing data to SSTDR. [3] Check the SSU state: Read SSSR confirming that the RDRF bit is 1. A change of the RDRF bit (from 0 to 1) can be notified by RXI interrupt. [4] Receive error processing: When a receive error occurs, execute the designated error processing after reading the ORER bit in SSSR. After that, clear the ORER bit to 0. While the ORER bit is set to 1, transmission or reception is not resumed. [5] Procedure for consecutive data transmission/reception: To continue serial data transmission/reception, confirm that the TDRE bit is 1 meaning that SSTDR is ready to be written to. After that, data can be written to SSTDR. The TDRE bit is automatically cleared to 0 by writing data to SSTDR.
Error processing
End transmission/reception Note: Hatching boxes represent SSU internal operations.
Figure 17.9 Flowchart Example of Simultaneous Transmission/Reception (SSU Mode)
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Section 17 Synchronous Serial Communication Unit (SSU)
17.4.6
SCS Pin Control and Conflict Error
When bits CSS1 and CSS0 in SSCRH are specified to B'10 and the SSUMS bit in SSCRL is cleared to 0, the SCS pin functions as an input (Hi-Z) to detect a conflict error. The arbitration detection period is from setting the MSS bit in SSCRH to 1 to starting serial transfer and after transfer ends. When a low level signal is input to the SCS pin within the period, a conflict error occurs. At this time, the CE bit in SSSR is set to 1 and the MSS bit is cleared to 0. Note: While the CE bit is set to 1, transmission or reception is not resumed. Clear the CE bit to 0 before resuming the transmission or reception.
External input to SCS Internal-clocked SCS MSS Internal signal for transfer enable CE Data written to SSTDR (Hi-Z) Conflict error detection period Worst time for internally clocking SCS
SCS output
Figure 17.10 Conflict Error Detection Timing (Before Transfer)
SCS (Hi-Z)
MSS Internal signal for transfer enable CE Transfer end Conflict error detection period
Figure 17.11 Conflict Error Detection Timing (After Transfer End)
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Section 17 Synchronous Serial Communication Unit (SSU)
17.4.7
Clock Synchronous Communication Mode
In clock synchronous communication mode, data communications are performed via three lines: clock line (SSCK), data input line (SSI), and data output line (SSO). (1) Initial Settings in Clock Synchronous Communication Mode
Figure 17.12 shows an example of the initial settings in clock synchronous communication mode. Before data transfer, clear both the TE and RE bits in SSER to 0 to set the initial values. Note: Before changing operating modes and communications formats, clear both the TE and RE bits to 0. Although clearing the TE bit to 0 sets the TDRE bit to 1, clearing the RE bit to 0 does not change the values of the RDRF and ORER bits and SSRDR. Those bits retain the previous values.
Start setting initial values
Clear TE and RE bits in SSER to 0
[1] When the pin is used as an input. [2] Specify master/slave mode selection and SSCK pin selection. [3] Selects clock synchronous communication mode and specify transmit/receive data length. [4] Specify clock polarity selection and transfer clock rate selection.
[1]
Set a bit in ICR to 1
[2]
Specify MSS and SCKS in SSCRH
[3]
Set SSUMS in SSCRL to 1 and specify bits DATS1 and DATS0
[5] Enables/disables interrupt request to the CPU.
[4]
Specify CPOS, CKS2, CKS1, and CKS0 bits in SSMR
[5]
Specify TEIE, TIE, RIE, and CEIE bits in SSER
End
Figure 17.12 Example of Initial Settings in Clock Synchronous Communication Mode
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Section 17 Synchronous Serial Communication Unit (SSU)
(2)
Data Transmission
Figure 17.13 shows an example of transmission operation, and figure 17.14 shows a flowchart example of data transmission. When transmitting data in clock synchronous communication mode, the SSU operates as shown below. In master mode, the SSU outputs a transfer clock and data. In slave mode, when a transfer clock is input to the SSCK pin, the SSU outputs data in synchronization with the transfer clock. Writing transmit data to SSTDR after the TE bit is set to 1 clears the TDRE bit in SSSR to 0, and the SSTDR contents are transferred to SSTRSR. After that, the SSU sets the TDRE bit to 1 and starts transmission. At this time, if the TIE bit in SSER is set to 1, a TXI interrupt is generated. When 1-frame data has been transferred with TDRE = 0, the SSTDR contents are transferred to SSTRSR to start the next frame transmission. When the 8th bit of transmit data has been transferred with TDRE = 1, the TEND bit in SSSR is set to 1 and the state is retained. At this time, if the TEIE bit is set to 1, a TEI interrupt is generated. While the ORER bit in SSSR is set to 1, transmission is not performed. Check that the ORER bit is cleared to 0.
SSCK
SSO
Bit 0
Bit 1 1 frame
Bit 7
Bit 0
Bit 1 1 frame
Bit 7
TDRE
TEND
LSI operation User operation
TXI interrupt generated Data written to SSTDR Data written to SSTDR
TXI interrupt generated
TEI interrupt generated
Figure 17.13 Example of Transmission Operation (Clock Synchronous Communication Mode)
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Section 17 Synchronous Serial Communication Unit (SSU)
Start [1] Initial setting TE = 1 (transmission enabled) [2] Read TDRE in SSSR TDRE = 1? Yes Write transmit data to SSTDR TDRE automatically cleared
Data transferred from SSTDR to SSTRSR
[4][1] Initial setting: Specify the transmit data format. [2] Check that the SSU state and write transmit data: Write transmit data to SSTDR after reading and confirming that the TDRE bit is 1. The TDRE bit is automatically cleared to 0 and transmission is started by writing data to SSTDR. No [3] Procedure for consecutive data transmission: To continue data transmission, confirm that the TDRE bit is 1 meaning that SSTDR is ready to be written to. After that, data can be written to SSTDR. The TDRE bit is automatically cleared to 0 by writing data to SSTDR. [4] Procedure for data transmission end: To end data transmission, confirm that the TEND bit is cleared to 0. After completion of transmitting the last bit, clear the TE bit to 0.
Set TDRE to 1 to start transmission [3]
Consecutive data transmission?
Yes
No Read TEND in SSSR TEND = 1? Yes Clear TEND to 0 Confirm that TEND is cleared to 0 [4] One bit time quantum elapsed? Yes Clear TE in SSER to 0 End transmission Note: Hatching boxes represent SSU internal operations. No No
Figure 17.14 Flowchart Example of Transmission Operation (Clock Synchronous Communication Mode)
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Section 17 Synchronous Serial Communication Unit (SSU)
(3)
Data Reception
Figure 17.15 shows an example of reception operation, and figure 17.16 shows a flowchart example of data reception. When receiving data, the SSU operates as shown below. After setting the RE bit in SSER to 1, the SSU starts data reception. In master mode, the SSU outputs a transfer clock and receives data. In slave mode, when a transfer clock is input to the SSCK pin, the SSU receives data in synchronization with the transfer clock. When 1-frame data has been received, the RDRF bit in SSSR is set to 1 and the receive data is stored in SSRDR. At this time, if the RIE bit is set to 1, an RXI interrupt is generated. The RDRF bit is automatically cleared to 0 by reading SSRDR. When the RDRF bit has been set to 1 at the 8th rising edge of the transfer clock, the ORER bit in SSSR is set to 1. This indicates that an overrun error (OEI) has occurred. At this time, data reception is stopped. While the ORER bit in SSSR is set to 1, reception is not performed. To resume the reception, clear the ORER bit to 0.
SSCK
SSO
Bit 0 1 frame
Bit 7
Bit 0 1 frame
Bit 7
Bit 0
Bit 7
RDRF LSI operation User operation Dummy-read SSRDR
RXI interrupt generated
RXI interrupt generated Read data from SSRDR
RXI interrupt generated Read data from SSRDR
Figure 17.15 Example of Reception Operation (Clock Synchronous Communication Mode)
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Section 17 Synchronous Serial Communication Unit (SSU)
Start [1] [2] Initial setting RE = 1 (reception started)
[1]
Initial setting: Specify the receive data format. Start reception: When setting the RE bit to 1, reception is started.
[2]
Read SSSR No RDRF = 1?
[3], [5] Receive error processing: When a receive error occurs, execute the designated error processing after reading the ORER bit in SSSR. After that, clear the ORER bit to 0. While the ORER bit is set to 1, transmission or reception is not resumed. [4] To complete reception: To complete reception, read receive data after clearing the RE bit to 0. When reading SSRDR without clearing the RE bit, reception is resumed.
Yes ORER = 1? No
Consecutive data reception?
Yes [3]
No
Yes Read received data in SSRDR RDRF automatically cleared
[4]
RE = 0 Read receive data in SSRDR End reception
[5]
Overrun error processing Clear ORER in SSSR End reception
Note: Hatching boxes represent SSU internal operations.
Figure 17.16 Flowchart Example of Data Reception (Clock Synchronous Communication Mode) (4) Data Transmission/Reception
Figure 17.17 shows a flowchart example of simultaneous transmission/reception. The data transmission/reception is performed combining the data transmission and data reception as mentioned above. The data transmission/reception is started by writing transmit data to SSTDR with TE = RE = 1.
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Section 17 Synchronous Serial Communication Unit (SSU)
Before switching transmission mode (TE = 1) or reception mode (RE = 1) to transmission/reception mode (TE = RE = 1), clear the TE and RE bits to 0. When starting the transfer, confirm that the TEND, RDRF, and ORER bits are cleared to 0 before setting the TE or RE bits to 1.
Start [1] Initial setting Transmission/reception started (TE = 1, RE = 1) [2] Read TDRE in SSSR. TDRE = 1? Yes Write transmit data to SSTDR TDRE automatically cleared Data transferred from SSTDR to SSTRSR TDRE set to 1 to start transmission Read SSSR [3] No RDRF = 1? Yes ORER = 1? No Read receive data in SSRDR RDRF automatically cleared Consecutive data transmission/reception? No Clear TEND in SSSR to 0 Clear TE and RE in SSER to 0 Yes [5] Yes [4] No
[1] Initial setting: Specify the transmit/receive data format. [2] Check the SSU state and write transmit data: Write transmit data to SSTDR after reading and confirming that the TDRE bit in SSSR is 1. The TDRE bit is automatically cleared to 0 and transmission is started by writing data to SSTDR. [3] Check the SSU state: Read SSSR confirming that the RDRF bit is 1. A change of the RDRF bit (from 0 to 1) can be notified by RXI interrupt. [4] Receive error processing: When a receive error occurs, execute the designated error processing after reading the ORER bit in SSSR. After that, clear the ORER bit to 0. While the ORER bit is set to 1, transmission or reception is not resumed. [5] Procedure for consecutive data transmission/reception: To continue serial data transmission/reception, confirm that the TDRE bit is 1 meaning that SSTDR is ready to be written to. After that, data can be written to SSTDR. The TDRE bit is automatically cleared to 0 by writing data to SSTDR.
Error processing
End transmission/reception Note: Hatching boxes represent SSU internal operations.
Figure 17.17 Flowchart Example of Simultaneous Transmission/Reception (Clock Synchronous Communication Mode)
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Section 17 Synchronous Serial Communication Unit (SSU)
17.5
Interrupt Requests
The SSU interrupt requests are an overrun error, a conflict error, a receive data register full, transmit data register empty, and a transmit end interrupts. Of these interrupt sources, a receive data register full, a transmit data register empty, and a transmit end interrupts can activate the DTC for data transfer. Since both an overrun error and a conflict error interrupts are allocated to the SSERI vector address, and both a transmit data register empty and a transmit end interrupts are allocated to the SSTXI vector address, the interrupt source should be decided by their flags. Table 17.5 lists the interrupt sources. When an interrupt condition shown in table 17.5 is satisfied, an interrupt is requested. Clear the interrupt source by CPU or DTC data transfer. Table 17.5 Interrupt Sources
Abbreviation Interrupt Source SSERI Overrun error Conflict error SSRXI SSTXI Receive data register full Transmit data register empty Transmit end Symbol OEI CEI RXI TXI TEI Interrupt Condition (RIE = 1) * (ORER = 1) (CEIE = 1) * (CE = 1) (RIE = 1) * (RDRF = 1) (TIE = 1) * (TDRE = 1) (TEIE = 1) * (TEND = 1)
DTC Activation
Yes Yes Yes
17.6
17.6.1
Usage Note
Setting of Module Stop Mode
The SSU can be enabled/disabled by the module stop control register setting and is disabled by the initial value. Canceling module stop mode enables to access the SSU registers. For details, see section 28, Power-Down Modes.
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Section 17 Synchronous Serial Communication Unit (SSU)
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Section 18 I2C Bus Interface (IIC)
Section 18 I C Bus Interface (IIC)
This LSI has six-channels of I C bus interface (IIC). The I C bus interface conforms to and 2 provides a subset of the Philips I C bus (inter-IC bus) interface functions. However, the register 2 configuration that controls the I C bus differs partly from the Philips configuration.
2 2
2
18.1
2
Features
* Selection of addressing format or non-addressing format I C bus format: addressing format with acknowledge bit, for master/slave operation Clocked synchronous serial format: non-addressing format without acknowledge bit, for master operation only * Conforms to Philips I C bus interface (I C bus format)
2 2
* Two ways of setting slave address (I C bus format)
2
* Start and stop conditions generated automatically in master mode (I C bus format)
2
* Selection of acknowledge output levels when receiving (I C bus format)
2
* Automatic loading of acknowledge bit when transmitting (I C bus format)
2
* Wait function in master mode (I C bus format)
2
A wait can be inserted by driving the SCL pin low after data transfer, excluding acknowledgement. The wait can be cleared by clearing the interrupt flag. * Wait function (I C bus format)
2
A wait request can be generated by driving the SCL pin low after data transfer. The wait request is cleared when the next transfer becomes possible. * Interrupt sources Data transfer end (including when a transition to transmit mode with I C bus format occurs, when ICDR data is transferred, or during a wait state)
2
Address match: when any slave address matches or the general call address is received in 2 slave receive mode with I C bus format (including address reception after loss of master arbitration) Arbitration loss Start condition detection (in master mode) Stop condition detection (in slave mode) * Selection of 32 internal clocks (in master mode) * Direct bus drive
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Section 18 I2C Bus Interface (IIC)
Pins SCL0 to SCL5 and SDA0 to SDA5 (normally NMOS push-pull outputs) function as NMOS open-drain outputs when the bus drive function is selected. Figure 18.1 shows a block diagram of the I C bus interface. Figure 18.2 shows an example of I/O 2 pin connections to external circuits. Since I C bus interface I/O pins are different in structure from normal port pins, they have different specifications for permissible applied voltages. For details, see section 31, Electrical Characteristics.
2
ICXR
SCL
PS
Clock control
ICCR
Noise canceler
ICMR
Bus state decision circuit Arbitration decision circuit
ICSR
Internal data bus
ICDRT ICDRS ICDRR
SDA
Output data control circuit
Noise canceler Address comparator
SAR, SARX
[Legend] ICCR: ICMR: ICSR: ICDR: ICXR: SAR: SARX: PS: bus control register I2C bus mode register 2C bus status register I I2C bus data register I2C bus extended control register Slave address register Slave address register X Prescaler I2C
Interrupt generator
Interrupt generator
Figure 18.1 Block Diagram of I C Bus Interface
2
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Section 18 I2C Bus Interface (IIC)
VCC
VDD
VCC
SCL SCL in SCL out SDA
SCL
SDA
SDA in SDA out (Master) This LSI
SCL SDA
SCL in SCL out
SCL in SCL out
SDA in SDA out (Slave 1)
2
SDA in SDA out (Slave 2)
Figure 18.2 I C Bus Interface Connections (Example: This LSI as Master)
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SCL SDA
Section 18 I2C Bus Interface (IIC)
18.2
Input/Output Pins
2
Table 18.1 summarizes the input/output pins used by the I C bus interface. Table 18.1 Pin Configuration
Channel 0 Symbol* SCL0 SDA0 1 SCL1 SDA1 2 SCL2 SDA2 3 SCL3 SDA3 4 SCL4 SDA4 5 Note: * SCL5 SDA5 Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Function Clock input/output pin of channel IIC_0 Data input/output pin of channel IIC_0 Clock input/output pin of channel IIC_1 Data input/output pin of channel IIC_1 Clock input/output pin of channel IIC_2 Data input/output pin of channel IIC_2 Clock input/output pin of channel IIC_3 Data input/output pin of channel IIC_3 Clock input/output pin of channel IIC_4 Data input/output pin of channel IIC_4 Clock input/output pin of channel IIC_5 Data input/output pin of channel IIC_5
In the text, the channel subscript is omitted, and only SCL and SDA are used.
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Section 18 I2C Bus Interface (IIC)
18.3
2
Register Descriptions
The I C bus interface has the following registers. Registers ICDR and SARX and registers ICMR and SAR are allocated to the same addresses. Accessible registers differ depending on the ICE bit in ICCR. When the ICE bit is cleared to 0, SAR and SARX can be accessed, and when the ICE bit is set to 1, ICMR and ICDR can be accessed. * I C bus data register (ICDR)
2
* Slave address register (SAR) * Second slave address register (SARX) * I C bus mode register (ICMR)
2 2 2 2 2 2
* I C bus transfer rate select register (IICX3) * I C bus control register (ICCR) * I C bus status register (ICSR) * I C bus extended control register (ICXR) * I C SMbus control register (ICSMBCR) 18.3.1 I C Bus Data Register (ICDR)
2
ICDR is an 8-bit readable/writable register that is used as a transmit data register when transmitting and a receive data register when receiving. ICDR is divided internally into a shift register (ICDRS), receive buffer (ICDRR), and transmit buffer (ICDRT). Data transfers among the three registers are performed automatically in accordance with changes in the bus state, and they affect the status of internal flags such as ICDRE and ICDRF. In master transmit mode with the I C bus format, writing transmit data to ICDR should be performed after start condition detection. When the start condition is detected, previous write data is ignored. In slave transmit mode, writing should be performed after the slave addresses match and the TRS bit is automatically changed to 1. If IIC is in transmit mode (TRS = 1) and the next data is in ICDRT (the ICDRE flag is 0), data is transferred automatically from ICDRT to ICDRS, following transmission of one frame of data using ICDRS. When the ICDRE flag is 1 and the next transmit data writing is waited, data is transferred automatically from ICDRT to ICDRS by writing to ICDR. If IIC is in receive mode (TRS = 0), no data is transferred from ICDRT to ICDRS. Note that data should not be written to ICDR in receive mode. Reading receive data from ICDR is performed after data is transferred from ICDRS to ICDRR.
2
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Section 18 I2C Bus Interface (IIC)
If IIC is in receive mode and no previous data remains in ICDRR (the ICDRF flag is 0), data is transferred automatically from ICDRS to ICDRR, following reception of one frame of data using ICDRS. If additional data is received while the ICDRF flag is 1, data is transferred automatically from ICDRS to ICDRR by reading from ICDR. In transmit mode, no data is transferred from ICDRS to ICDRR. Always set IIC to receive mode before reading from ICDR. If the number of bits in a frame, excluding the acknowledge bit, is less than eight, transmit data and receive data are stored differently. Transmit data should be written justified toward the MSB side when MLS = 0 in ICMR, and toward the LSB side when MLS = 1. Receive data bits should be read from the LSB side when MLS = 0, and from the MSB side when MLS = 1. ICDR can be written to and read from only when the ICE bit is set to 1 in ICCR. The initial value of ICDR is undefined. 18.3.2 Slave Address Register (SAR)
SAR sets the slave address and selects the communication format. When the LSI is in slave mode 2 with the I C bus format selected, if the FS bit is set to 0 and the upper 7 bits of SAR match the upper 7 bits of the first frame received after a start condition, the LSI operates as the slave device specified by the master device. SAR can be accessed only when the ICE bit in ICCR is cleared to 0.
Bit 7 6 5 4 3 2 1 0 Bit Name SVA6 SVA5 SVA4 SVA3 SVA2 SVA1 SVA0 FS 0 R/W Format Select Selects the communication format together with the FSX bit in SARX. Refer to table 18.2. This bit should be set to 0 when general call address recognition is performed. Initial Value All 0 R/W R/W Description Slave Addresses 6 to 0 Set a slave address.
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Section 18 I2C Bus Interface (IIC)
18.3.3
Second Slave Address Register (SARX)
SARX sets the second slave address and selects the communication format. In slave mode, transmit/receive operations by the DTC are possible when the received address matches the 2 second slave address. When the LSI is in slave mode with the I C bus format selected, if the FSX bit is set to 0 and the upper 7 bits of SARX match the upper 7 bits of the first frame received after a start condition, the LSI operates as the slave device specified by the master device. SARX can be accessed only when the ICE bit in ICCR is cleared to 0.
Bit 7 6 5 4 3 2 1 0 Bit Name SVAX6 SVAX5 SVAX4 SVAX3 SVAX2 SVAX1 SVAX0 FSX 1 R/W Format Select X Selects the communication format together with the FS bit in SAR. Refer to table 18.2. Initial Value All 0 R/W R/W Description Second Slave Addresses 6 to 0 Set the second slave address.
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Section 18 I2C Bus Interface (IIC)
Table 18.2 Transfer Format
SAR FS 0 SARX FSX 0 Operating Mode I C bus format * * 1
2 2
SAR and SARX slave addresses recognized General call address recognized SAR slave address recognized SARX slave address ignored General call address recognized SAR slave address ignored SARX slave address recognized General call address ignored SAR and SARX slave addresses ignored General call address ignored
I C bus format * * *
1
0
I C bus format * * *
2
1
Clocked synchronous serial format * *
* I C bus format: addressing format with acknowledge bit
2
* Clocked synchronous serial format: non-addressing format without acknowledge bit, for master mode only
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Section 18 I2C Bus Interface (IIC)
18.3.4
I C Bus Mode Register (ICMR)
2
ICMR sets the communication format and transfer rate. It can only be accessed when the ICE bit in ICCR is set to 1.
Bit 7 Bit Name MLS Initial Value 0 R/W R/W Description MSB-First/LSB-First Select 0: MSB-first 1: LSB-first Set this bit to 0 when the I C bus format is used. 6 WAIT 0 R/W Wait Insertion Bit This bit is valid only in master mode with the I C bus format. 0: Data and the acknowledge bit are transferred consecutively with no wait inserted. 1: After the fall of the clock for the final data bit (8th clock), the IRIC flag is set to 1 in ICCR, and a wait state begins (with SCL at the low level). When the IRIC flag is cleared to 0 in ICCR, the wait ends and the acknowledge bit is transferred. For details, refer to section 18.4.7, IRIC Setting Timing and SCL Control. 5 4 3 CKS2 CKS1 CKS0 All 0 R/W Transfer Clock Select These bits are used only in master mode. These bits select the required transfer clock rate, together with bits IICX5 (channel 5), IICX4 (channel 4), and IICX3 (channel 3) in the IICX3 register and bits IICX2 (channel 2), IICX1 (channel 1), and IICX0 (channel 0) in the STCR register. Refer to table 18.3.
2 2
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Section 18 I2C Bus Interface (IIC)
Bit 2 1 0
Bit Name BC2 BC1 BC0
Initial Value All 0
R/W R/W
Description Bit Counter These bits specify the number of bits to be transferred next. Bit BC2 to BC0 settings should be made during an interval between transfer frames. If bits BC2 to BC0 are set to a value other than B'000, the setting should be made while the SCL line is low. The bit counter is initialized to B'000 when a start condition is detected. The value returns to B'000 at the end of a data transfer. I C Bus Format B'000: 9 bits B'001: 2 bits B'010: 3 bits B'011: 4 bits B'100: 5 bits B'101: 6 bits B'110: 7 bits B'111: 8 bits
2
Clocked Synchronous Serial Mode B'000: 8 bits B'001: 1 bits B'010: 2 bits B'011: 3 bits B'100: 4 bits B'101: 5 bits B'110: 6 bits B'111: 7 bits
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Section 18 I2C Bus Interface (IIC)
18.3.5
I C Bus Transfer Rate Select Register (IICX3)
2
IICX3 selects the IIC transfer rate clock and sets the transfer rate of IIC channel 3.
Bit 7 to 4 Bit Name Initial Value R/W Description Reserved These bits cannot be modified. The read values are undefined. 3 TCSS 0 R/W Transfer Rate Clock Source Select This bit selects a clock rate to be applied to the I C bus transfer rate. 0: /2 1: /4 2 1 0 IICX5 IICX4 IICX3 0 0 0 R/W R/W R/W IIC Transfer Rate Select 5, 4, 3 These bits are used to control IIC_5 to IIC_3 operation. These bits select the transfer rate in master mode, together with the CKS2 to CKS0 bits in ICMR. For the transfer rate, see table 18.3.
2
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Section 18 I2C Bus Interface (IIC)
Table 18.3 I C bus Transfer Rate (1) * TCSS = 0
STCR/ IICX3 IICXn 0 Bit 5 CKS2 0 ICMR Bit 4 CKS1 0 Bit 3 CKS0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Clock
/28 /40 /48 /64 /80 /100 /112 /128 /56 /80 /96 /128 /160 /200 /224 /256 = 20 MHz
2
Transfer Rate
= 25 MHz = 34 MHz
714.3 kHz* 500.0 kHz* 416.7 kHz* 312.5 kHz 250.0 kHz 200.0 kHz 178.6 kHz 156.3 kHz 357.1 kHz 250.0 kHz 208.3 kHz 156.3 kHz 125.0 kHz 100.0 kHz 89.3 kHz 78.1 kHz
892.9 kHz* 625.0 kHz* 520.8 kHz* 390.6 kHz 312.5 kHz 250.0 kHz 223.2 kHz 195.3 kHz 446.4 kHz* 312.5 kHz 260.4 kHz 195.3 kHz 156.3 kHz 125.0 kHz 111.6 kHz 97.7 kHz
1214.3 kHz* 850.0 kHz* 708.3 kHz* 531.3 kHz* 425.0 kHz* 340.0 kHz 303.6 kHz 265.6 kHz 607.1 kHz* 425.0 kHz* 354.2 kHz 265.6 kHz 212.5 kHz 170.0 kHz 151.8 kHz 132.8 kHz
2
Note:
*
The correct operation cannot be guaranteed since the value is outside the I C bus interface specifications (high-speed mode: max. 400 kHz). (n = 0 to 5)
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Section 18 I2C Bus Interface (IIC)
Table 18.3 I C bus Transfer Rate (2) * TCSS = 1
STCR/ IICX3 IICXn 0 Bit 5 CKS2 0 ICMR Bit 4 CKS1 0 Bit 3 CKS0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Clock
/56 /80 /96 /128 /160 /200 /224 /256 /112 /160 /190 /256 /320 /400 /448 /512 = 20 MHz
2
Transfer Rate
= 25 MHz = 34 MHz
357.1 kHz 250.0 kHz 208.3 kHz 156.3 kHz 125.0 kHz 100.0 kHz 89.3 kHz 78.1 kHz 178.6 kHz 125.0 kHz 104.2 kHz 78.1 kHz 62.5 kHz 50.0 kHz 44.6 kHz 39.1 kHz
446.4 kHz* 312.5 kHz 260.4 kHz 195.3 kHz 156.3 kHz 125.0 kHz 111.6 kHz 97.7 kHz 223.2 kHz 156.3 kHz 130.2 kHz 97.7 kHz 78.1 kHz 62.5 kHz 55.8 kHz 48.8 kHz
607.1 kHz* 425.0 kHz* 345.2 kHz 265.6 kHz 212.5 kHz 170.0 kHz 151.8 kHz 132.8 kHz 303.6 kHz 212.5 kHz 177.1 kHz 132.8 kHz 106.3 kHz 85.0 kHz 75.9 kHz 66.4 kHz
2
Note:
*
The correct operation cannot be guaranteed since the value is outside the I C bus interface specifications (high-speed mode: max. 400 kHz). (n = 0 to 5)
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Section 18 I2C Bus Interface (IIC)
18.3.6
I C Bus Control Register (ICCR)
2
2
ICCR controls the I C bus interface and performs interrupt flag confirmation.
Bit 7 Bit Name ICE Initial Value 0 R/W R/W Description I C Bus Interface Enable 0: I C bus interface modules are stopped and I C bus interface module internal state is initialized. SAR and SARX can be accessed. 1: I C bus interface modules can perform transfer and reception, they are connected to the SCL and SDA pins, 2 and the I C bus can be driven. ICMR and ICDR can be accessed. 6 IEIC 0 R/W I C Bus Interface Interrupt Enable 0: Disables interrupts from the I C bus interface to the CPU. 1: Enables interrupts from the I C bus interface to the CPU. 5 4 MST TRS 0 0 R/W R/W Master/Slave Select Transmit/Receive Select 00: Slave receive mode 01: Slave transmit mode 10: Master receive mode 11: Master transmit mode Both these bits will be cleared by hardware when they 2 lose in a bus contention in master mode of the I C bus 2 format. In slave receive mode with I C bus format, the R/W bit in the first frame immediately after the start condition automatically sets these bits in receive mode or transmit mode by hardware. Modification of the TRS bit during transfer is deferred until transfer is completed, and the changeover is made after completion of the transfer.
2 2 2 2 2 2 2
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Section 18 I2C Bus Interface (IIC)
Bit 5 4
Bit Name MST TRS
Initial Value 0 0
R/W R/W R/W
Description [MST clearing conditions] (1) When 0 is written by software (2) When lost in bus contention in I C bus format master mode [MST setting conditions] (1) When 1 is written by software (for MST clearing condition 1) (2) When 1 is written in MST after reading MST = 0 (for MST clearing condition 2) [TRS clearing conditions] (1) When 0 is written by software (except for TRS setting condition 3) (2) When 0 is written in TRS after reading TRS = 1 (for TRS setting condition 3) (3) When lost in bus contention in I C bus format master mode [TRS setting conditions] (1) When 1 is written by software (except for TRS clearing condition 3) (2) When 1 is written in TRS after reading TRS = 0 (for TRS clearing condition 3) (3) When 1 is received as the R/W bit after the first frame 2 address matching in I C bus format slave mode
2 2
3
ACKE
0
R/W
Acknowledge Bit Decision Selection 0: The value of the acknowledge bit is ignored, and continuous transfer is performed. The value of the received acknowledge bit is not indicated by the ACKB bit in ICSR, which is always 0. 1: If the acknowledge bit is 1, continuous transfer is halted. Depending on the receiving device, the acknowledge bit may be significant, in indicating completion of processing of the received data, for instance, or may be fixed at 1 and have no significance.
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Section 18 I2C Bus Interface (IIC)
Bit 2 0
Bit Name BBSY SCP
Initial Value 0 1
R/W R/W* W
Description Bus Busy Start Condition/Stop Condition Prohibit In master mode * * Writing 0 in BBSY and 0 in SCP: A stop condition is issued Writing 1 in BBSY and 0 in SCP: A start condition and a restart condition are issued Writing to the BBSY flag is disabled.
In slave mode *
[BBSY setting condition] * When the SDA level changes from high to low under the condition of SCL = high, assuming that the start condition has been issued. When the SDA level changes from low to high under the condition of SCL = high, assuming that the stop condition has been issued.
2
[BBSY clearing conditions] *
To issue a start/stop condition, use the MOV instruction. The I C bus interface must be set in master transmit mode before the issue of a start condition. Set MST to 1 and TRS to 1 before writing 1 in BBSY and 0 in SCP. The BBSY flag can be read to check whether the I C bus (SCL, SDA) is busy or free. Note: * Even if the BBSY bit is written to, the value of the flag does not change.
2
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Section 18 I2C Bus Interface (IIC)
Bit 1
Bit Name IRIC
Initial Value R/W 0
Description
2
R/(W)* I C Bus Interface Interrupt Request Flag 2 Indicates that the I C bus interface has issued an interrupt request to the CPU. IRIC is set at different times depending on the FS bit in SAR and the WAIT bit in ICMR. See section 18.4.7, IRIC Setting Timing and SCL Control. The conditions under which IRIC is set also differ depending on the setting of the ACKE bit in ICCR. [Setting conditions] 2 I C bus format master mode: * When a start condition is detected in the bus line state after a start condition is issued (when the ICDRE flag is set to 1 because of first frame transmission) * When a wait is inserted between the data and acknowledge bit when the WAIT bit is 1 (fall of the 8th transmit/receive clock) At the end of data transfer (rise of the 9th transmit/receive clock) When a slave address is received after bus mastership is lost
* * *
If 1 is received as the acknowledge bit (when the ACKB bit in ICSR is set to 1) when the ACKE bit is 1 * When the AL flag is set to 1 after bus mastership is lost while the ALIE bit is 1 2 I C bus format slave mode: * When the slave address (SVA or SVAX) matches (when the AAS or AASX flag in ICSR is set to 1) and at the end of data transfer up to the subsequent retransmission start condition or stop condition detection (rise of the 9th clock) * When the general call address is detected (when the 0 is received for R/W bit, and ADZ flag in ICSR is set to 1) and at the end of data reception up to the subsequent retransmission start condition or stop condition detection (rise of the 9th receive clock) * When 1 is received as an acknowledge bit while the ACKE bit is 1 (when the ACKB bit is set to 1) * When a stop condition is detected while the STOPIM bit is 0 (when the STOP or ESTP flag in ICSR is set to 1)
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Section 18 I2C Bus Interface (IIC)
Bit 1
Bit Name IRIC
Initial Value 0
R/W
1
Description
R/(W)* At the end of data transfer in clock synchronous serial format (rise of the 8th transmit/receive clock) When a start condition is detected with serial format selected When a condition occurs in which the ICDRE or ICDRF flag is set to 1. * When a start condition is detected in transmit mode (when a start condition is detected and the ICDRE flag is set to 1) When transmitting the data in the ICDR register buffer (when data is transferred from ICDRT to ICDRS in transmit mode and the ICDRE flag is set to 1, or data is transferred from ICDRS to ICDRR in receive mode and the ICDRF flag is set to 1.) When 0 is written in IRIC after reading IRIC = 1 When ICDR is accessed by DTC * (This may not be a clearing condition. For details, see the description of the DTC operation on the next page.
*
[Clearing conditions] * *
Note:
*
Only 0 can be written to clear the flag.
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Section 18 I2C Bus Interface (IIC)
When the DTC is used, IRIC is cleared automatically and transfer can be performed continuously without CPU intervention. When, with the I C bus format selected, IRIC is set to 1 and an interrupt is generated, other flags must be checked in order to identify the source that set IRIC to 1. Although each source has a corresponding flag, caution is needed at the end of a transfer. When the ICDRE or ICDRF flag is set, the IRTR flag may or may not be set. The IRTR flag (the DTC start request flag) is not set at the end of a data transfer up to detection of a retransmission 2 start condition or stop condition after a slave address (SVA) or general call address match in I C bus format slave mode. Even when the IRIC flag and IRTR flag are set, the ICDRE or ICDRF flag may not be set. The IRIC and IRTR flags are not cleared at the end of the specified number of transfers in continuous transfer using the DTC. The ICDRE or ICDRF flag is cleared, however, since the specified number of ICDR reads or writes have been completed. Tables 18.4 and 18.5 show the relationship between the flags and the transfer states.
2
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Section 18 I2C Bus Interface (IIC)
Table 18.4 Flags and Transfer States (Master Mode)
MST 1 TRS 1
BBSY ESTP STOP IRTR AASX
AL 0
AAS 0
ADZ 0
ACKB
ICDRF
ICDRE
State Idle state (flag clearing required) Start condition detected Wait state Transmission end (ACKE=1 and ACKB=1) Transmission end with ICDRE=0 ICDR write with the above state Transmission end with ICDRE=1 ICDR write with the above state or after start condition detected Automatic data transfer from ICDRT to ICDRS with the above state Reception end with ICDRF=0 ICDR read with the above state Reception end with ICDRF=1 ICDR read with the above state Automatic data transfer from ICDRS to ICDRR with the above state Arbitration lost Stop condition detected
0
0
0
0
0
0
0
1 1 1
1 1
1 1 1
0 0 0
0 0 0
1
0 0 0
0 0 0
0 0 0
0 0 0
0 1

1
1
1
1
0
0
1
0
0
0
0
0
1
1 1
1 1
1 1
0 0
0 0

0 0
0 0
0 0
0 0
0 0

0 1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
0
0
1
0
0
0
0
0
1
1 1 1 1 1
0 0 0 0 0
1 1 1 1 1
0 0 0 0 0
0 0 0 0 0
1 1
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0

1 0 1 0 1

0 1
0
1 0
0 0
0 0

0 0
1 0
0 0
0 0

0
[Legend] 0: 0-state retained 0: Cleared to 0
1: 1-state retained 1: Set to 1
: Previous state retained
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Section 18 I2C Bus Interface (IIC)
Table 18.5 Flags and Transfer States (Slave Mode)
MST 0 TRS 0
BBSY ESTP STOP IRTR AASX
AL 0
AAS 0
ADZ 0
ACKB
ICDRF
ICDRE
State Idle state (flag clearing required) Start condition detected SAR match in first frame (SARXSAR) General call address match in first frame (SARXH'00) SAR match in first frame (SARSARX) Transmission end (ACKE=1 and ACKB=1) Transmission end with ICDRE=0 ICDR write with the above state Transmission end with ICDRE=1 ICDR write with the above state Automatic data transfer from ICDRT to ICDRS with the above state Reception end with ICDRF=0 ICDR read with the above state
0
0
0
0
0
0
0
0 0
0 1/0 *1 0
1 1
0 0
0 0
0 0
0 0
0
0 1
0 0
0 0
1
1 1
0
1
0
0
0
0
1
1
0
1
1
0
1/0 *1 1
1
0
0
1
1
0
0
0
1
1
0
1
0
0

0
1
0
1
1
0
0
1/0 *1
0
0
1
0
1
1
0
0
0
0
0
0
0
0
1
1
0
0

0
0
1
0
1
1
0
0
0
0
0
0
0
0
1
1
0
0
1/0 *2
0
0
0
0
1
0 0
0 0
1 1
0 0
0 0
1/0 *2

0
0
0

1 0

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Section 18 I2C Bus Interface (IIC)
MST 0 TRS 0 AL AAS ADZ State Reception end with ICDRF=1 ICDR read with the above state Automatic data transfer from ICDRS to ICDRR with the above state Stop condition detected
BBSY
ESTP
STOP
IRTR
AASX
ACKB
ICDRF
ICDRE
1
0
0
1
0
0
1
0
0
0
0
0
0
0
0
1
0
0
1/0 *2
0
0
0
1
0
0
1/0 *3
0/1 3 *

0
[Legend] 0: 0-state retained 1: 1-state retained : Previous state retained 0: Cleared to 0 1: Set to 1 Notes: 1. Set to 1 when 1 is received as a R/W bit following an address. 2. Set to 1 when the AASX bit is set to 1. 3. When ESTP=1, STOP is 0, or when STOP=1, ESTP is 0.
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Section 18 I2C Bus Interface (IIC)
18.3.7
I C Bus Status Register (ICSR)
2
ICSR consists of status flags. Refer to tables 18.4 and 18.5 as well.
Bit 7 Bit Name ESTP Initial Value 0 R/W Description This bit is valid in I C bus format slave mode. [Setting condition] When a stop condition is detected during frame transfer. [Clearing conditions] * * 6 STOP 0 When 0 is written in ESTP after reading ESTP = 1 When the IRIC flag in ICCR is cleared to 0
2 2
R/(W)* Error Stop Condition Detection Flag
R/(W)* Normal Stop Condition Detection Flag This bit is valid in I C bus format slave mode. [Setting condition] When a stop condition is detected after frame transfer is completed. [Clearing conditions] * * When 0 is written in STOP after reading STOP = 1 When the IRIC flag is cleared to 0
5
IRTR
0
R/(W)* I C Bus Interface Continuous Transfer Interrupt Request Flag Indicates that the I C bus interface has issued an interrupt request to the CPU, and the source is completion of reception/transmission of one frame in continuous transmission/reception for which DTC activation is possible. When the IRTR flag is set to 1, the IRIC flag is also set to 1 at the same time. [Setting conditions] I C bus format slave mode: *
2 2 2
2
When the ICDRE or ICDRF flag in ICDR is set to 1 when AASX = 1
I C bus format master mode or clocked synchronous serial format mode: * * * When the ICDRE or ICDRF flag is set to 1 When 0 is written after reading IRTR = 1 When the IRIC flag is cleared to 0 while ICE is 1
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[Clearing conditions]
Section 18 I2C Bus Interface (IIC)
Bit 4
Bit Name AASX
Initial Value 0
R/W
Description In I C bus format slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits SVAX6 to SVAX0 in SARX. [Setting condition] When the second slave address is detected in slave receive mode and FSX = 0 in SARX [Clearing conditions] * * * When 0 is written in AASX after reading AASX = 1 When a start condition is detected In master mode
2
R/(W)* Second Slave Address Recognition Flag
3
AL
0
R/(W)* Arbitration Lost Flag Indicates that arbitration was lost in master mode. [Setting conditions] When ALSL=0 * * If the internal SDA and SDA pin disagree at the rise of SCL in master transmit mode If the internal SCL line is high at the fall of SCL in master mode If the internal SDA and SDA pin disagree at the rise of SCL in master transmit mode If the SDA pin is driven low by another device before 2 the I C bus interface drives the SDA pin low, after the start condition instruction was executed in master transmit mode When ICDR is written to (transmit mode) or read from (receive mode) When 0 is written in AL after reading AL = 1
When ALSL=1 * *
[Clearing conditions] * *
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Section 18 I2C Bus Interface (IIC)
Bit 2
Bit Name AAS
Initial Value 0
R/W
Description
2
R/(W)* Slave Address Recognition Flag In I C bus format slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits SVA6 to SVA0 in SAR, or if the general call address (H'00) is detected. [Setting condition] When the slave address or general call address (one frame including a R/W bit is H'00) is detected in slave receive mode and FS = 0 in SAR [Clearing conditions] * * * When ICDR is written to (transmit mode) or read from (receive mode) When 0 is written in AAS after reading AAS = 1 In master mode
2
1
ADZ
0
R/(W)* General Call Address Recognition Flag In I C bus format slave receive mode, this flag is set to 1 if the first frame following a start condition is the general call address (H'00). [Setting condition] When the general call address (one frame including a R/W bit is H'00) is detected in slave receive mode and FS = 0 or FSX = 0 [Clearing conditions] * * * When ICDR is written to (transmit mode) or read from (receive mode) When 0 is written in ADZ after reading ADZ = 1 In master mode
If a general call address is detected while FS=1 and FSX=0, the ADZ flag is set to 1; however, the general call address is not recognized (AAS flag is not set to 1).
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Section 18 I2C Bus Interface (IIC)
Bit 0
Bit Name ACKB
Initial Value 0
R/W R/W
Description Acknowledge Bit Stores acknowledge data. Transmit mode: [Setting condition] When 1 is received as the acknowledge bit when ACKE=1 in transmit mode [Clearing conditions] * * When 0 is received as the acknowledge bit when ACKE=1 in transmit mode When 0 is written to the ACKE bit
Receive mode: 0: Returns 0 as acknowledge data after data reception 1: Returns 1 as acknowledge data after data reception When this bit is read, the value loaded from the bus line (returned by the receiving device) is read in transmission (when TRS = 1). In reception (when TRS = 0), the value set by internal software is read. When this bit is written, acknowledge data that is returned after receiving is rewritten regardless of the TRS value. If the ICSR register bit is written using bit-manipulation instructions, the acknowledge data should be re-set since the acknowledge data setting is rewritten by the ACKB bit reading value. Write the ACKE bit to 0 to clear the ACKB flag to 0, before transmission is ended and a stop condition is issued in master mode, or before transmission is ended and SDA is released to issue a stop condition by a master device. Note: * Only 0 can be written to clear the flag.
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Section 18 I2C Bus Interface (IIC)
18.3.8
I C Bus Extended Control Register (ICXR)
2
2
ICXR enables or disables the I C bus interface interrupt generation and continuous receive operation, and indicates the status of receive/transmit operations.
Bit 7 Bit Name STOPIM Initial Value 0 R/W R/W Description Stop Condition Interrupt Source Mask Enables or disables the interrupt generation when the stop condition is detected in slave mode. 0: Enables IRIC flag setting and interrupt generation when the stop condition is detected (STOP = 1 or ESTP = 1) in slave mode. 1: Disables IRIC flag setting and interrupt generation when the stop condition is detected. 6 HNDS 0 R/W Handshake Receive Operation Select Enables or disables continuous receive operation in receive mode. 0: Enables continuous receive operation 1: Disables continuous receive operation When the HNDS bit is cleared to 0, receive operation is performed continuously after data has been received successfully while ICDRF flag is 0. When the HNDS bit is set to 1, SCL is fixed to the low level after data has been received successfully while ICDRF flag is 0; thus disabling the next data to be transferred. The bus line is released and next receive operation is enabled by reading the receive data in ICDR.
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Section 18 I2C Bus Interface (IIC)
Bit 5
Bit Name ICDRF
Initial Value 0
R/W R
Description Receive Data Read Request Flag Indicates the ICDR (ICDRR) status in receive mode. 0: Indicates that the data has been already read from ICDR (ICDRR) or ICDR is initialized. 1: Indicates that data has been received successfully and transferred from ICDRS to ICDRR, and the data is ready to be read out. [Setting conditions] * When data is received successfully and transferred from ICDRS to ICDRR.
(1) When data is received successfully while ICDRF = 0 (at the rise of the 9th clock pulse). (2) When ICDR is read successfully in receive mode after data was received while ICDRF = 1. [Clearing conditions] * * When ICDR (ICDRR) is read. When 0 is written to the ICE bit.
When ICDRF is set due to the condition (2) above, ICDRF is temporarily cleared to 0 when ICDR (ICDRR) is read; however, since data is transferred from ICDRS to ICDRR immediately, ICDRF is set to 1 again. Note that ICDR cannot be read successfully in transmit mode (TRS = 1) because data is not transferred from ICDRS to ICDRR. Be sure to read data from ICDR in receive mode (TRS = 0).
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Section 18 I2C Bus Interface (IIC)
Bit 4
Bit Name ICDRE
Initial Value 0
R/W R
Description Transmit Data Write Request Flag Indicates the ICDR (ICDRT) status in transmit mode. 0: Indicates that the data has been already written to ICDR (ICDRT) or ICDR is initialized. 1: Indicates that data has been transferred from ICDRT to ICDRS and is being transmitted, or the start condition has been detected or transmission has been completed, thus allowing the next data to be written to. [Setting conditions] * * When the start condition is detected from the bus line 2 state in I C bus format or serial format. When data is transferred from ICDRT to ICDRS. 1. When data is transmitted completely while ICDRE = 0 (at the rise of the 9th clock pulse). 2. When data is written to ICDR completely in transmit mode after data was transmitted while ICDRE = 1. [Clearing conditions] * * * When data is written to ICDR (ICDRT). When the stop condition is detected in I C bus format or serial format. When 0 is written to the ICE bit.
2 2
Note that if the ACKE bit is set to 1 in I C bus format thus enabling acknowledge bit decision, ICDRE is not set when data is transmitted completely while the acknowledge bit is 1. When ICDRE is set due to the condition (2) above, ICDRE is temporarily cleared to 0 when data is written to ICDR (ICDRT); however, since data is transferred from ICDRT to ICDRS immediately, ICDRF is set to 1 again. Do not write data to ICDR when TRS = 0 because the ICDRE flag value is invalid during the time.
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Section 18 I2C Bus Interface (IIC)
Bit 3
Bit Name ALIE
Initial Value 0
R/W R/W
Description Arbitration Lost Interrupt Enable Enables or disables IRIC flag setting and interrupt request when arbitration is lost. 0: Disables interrupt request when arbitration is lost. 1: Enables interrupt request when arbitration is lost.
2
ALSL
0
R/W
Arbitration Lost Condition Select Selects the condition under which arbitration is lost. 0: If the SDA pin state disagrees with the data that I C bus interface outputs at the rise of SCL and the SCL pin is driven low by another device. 1: If the SDA pin state disagrees with the data that I C bus interface outputs at the rise of SCL and the SDA line is driven low by another device in idle state or after the start condition instruction was executed.
2 2
1 0
FNC1 FNC0
0 0
R/W R/W
Function Bit These bits cancel some restrictions on usage. For details, refer to section 18.6, Usage Notes. 00: Restrictions on operation remaining in effect 01: Setting prohibited 10: Setting prohibited 11: Restrictions on operation canceled
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Section 18 I2C Bus Interface (IIC)
18.3.9
I C SMBus Control Register (ICSMBCR)
2
ICSMBCR is used to support the System Management Bus (SMBus) specifications. To support the SMBus specification, SDA output data hold time should be specified in the range of 300 ns to 1000 ns. Table 18.7 shows the relationship between the ICSMBCR setting and output data hold time. When the SMBus is not supported, the initial value should not be changed. ICSMBCR is enabled to access when bit MSTP4 is cleared to 0.
Bit 7 6 5 4 3 2 1 0 Bit Name SMB5E SMB4E SMB3E SMB2E SMB1E SMB0E FSEL1 FSEL0 Initial Value 0 0 0 0 0 00 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description SMBus Enable These bits enable/disable to support the SMBus, in combination with bits FSEL1 and FSEL0. Bits SMB5E, SMB4E, SMB3E, SMB2E, SMB1E, and SMB0E control IIC_5, IIC_4, IIC_3, IIC_2, IIC_1, and IIC_0, respectively. 0: Disables to support the SMBus 1: Enables to support the SMBus Frequency Selection These bits must be specified to match the system clock frequency in order to support the SMBus. For details of the setting, see table 18.6.
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Section 18 I2C Bus Interface (IIC)
Table 18.6 Output Data Hold Time
Output Data Hold Time (ns) SMBnE 0 FSEL1 FSEL0 Min./Max. Min. Max. 1 0 0 Min. Max. 1 Min. Max. 1 0 Min. Max. 1 Min. Max. = 20 MHz 100* 150* 150* 250* 200* 350 300 550 500 950 = 25 MHz 80* 120* 120* 200* 160* 280* 240* 440 400 760 = 34 MHz 59* 88* 88* 147* 118* 206* 176* 324 294* 559
Notes: *
n = 0 to 5 Since the value is outside the SMBus specification, it should not be set.
Table 18.7 ISCMBCR Setting
System Clock 20 MHz 20 to 34 MHz n = 0 to 5 SMBnE 1 1 FSEL1 1 1 FSEL0 0 1
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Section 18 I2C Bus Interface (IIC)
18.4
18.4.1
2
Operation
I C Bus Data Format
2 2
The I C bus interface has an I C bus format and a serial format. The I C bus formats are addressing formats with an acknowledge bit. These are shown in figures 18.3 (a) and (b). The first frame following a start condition always consists of 9 bits. The serial format is a non-addressing format with no acknowledge bit. This is shown in figure 18.4. Figure 18.5 shows the I C bus timing. The symbols used in figures 18.3 to 18.5 are explained in table 18.8.
(a) FS = 0 or FSX = 0 S 1 SLA 7 1 (b) Start condition retransmission FS = 0 or FSX = 0 S 1 SLA 7 1 R/W 1 A 1 DATA n1 m1 A/A 1 S 1 SLA 7 1 R/W 1 A 1 DATA n2 m2 Upper row: Transfer bit count (n1, n2 = 1 to 8) Lower row: Transfer frame count (m1, m2 = from 1) A/A 1 P 1 R/W 1 A 1 DATA n A 1 m A/A 1 P 1 Transfer bit count (n = 1 to 8) Transfer frame count (m = from 1)
2 2
Figure 18.3 I C Bus Data Formats (I C Bus Formats)
FS=1 and FSX=1 S 1 DATA 8 1 DATA n m P 1 Transfer bit count (n = 1 to 8) Transfer frame count (m = from 1)
2
2
Figure 18.4 I C Bus Data Formats (Serial Formats)
2
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Section 18 I2C Bus Interface (IIC)
SDA
SCL 1-7 S SLA 8 R/W 9 A 1-7 DATA
2
8
9 A
1-7 DATA
8
9 A/A P
Figure 18.5 I C Bus Timing Table 18.8 I C Bus Data Format Symbols
Symbol S SLA R/W A Description Start condition. The master device drives SDA from high to low while SCL is high Slave address. The master device selects the slave device. Indicates the direction of data transfer: from the slave device to the master device when R/W is 1, or from the master device to the slave device when R/W is 0 Acknowledge. The receiving device drives SDA low to acknowledge a transfer. (The slave device returns acknowledge in master transmit mode, and the master device returns acknowledge in master receive mode.) Transferred data. The bit length of transferred data is set with the BC2 to BC0 bits in ICMR. The MSB first or LSB first is switched with the MLS bit in ICMR. Stop condition. The master device drives SDA from low to high while SCL is high
2
DATA P
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Section 18 I2C Bus Interface (IIC)
18.4.2
Initialization
Initialize the IIC by the procedure shown in figure 18.6 before starting transmission/reception of data.
Start initialization Set MSTP4 = 0 (IIC_0) MSTP3 = 0 (IIC_1) MSTP2 = 0 (IIC_2, IIC_3) MSTP0 = 0 (IIC_4, IIC_5) (MSTPCRL) Set IICE = 1 in STCR Set ICE = 0 in ICCR Set SAR and SARX Set ICE = 1 in ICCR Set ICSR Set STCR and IICX3 Set ICMR Set ICXR Set ICCR << Start transmit/receive operation >>
Cancel module stop mode
Enable the CPU accessing to the IIC control register and data register Enable SAR and SARX to be accessed Set the first and second slave addresses and IIC communication format (SVA6 to SVA0, FS, SVAX6 to SVAX0, and FSX) Enable ICMR and ICDR to be accessed Use SCL/SDA pin as an IIC port Set acknowledge bit (ACKB) Set transfer rate (IICX and TCSS) Set communication format, wait insertion, and transfer rate (MLS, WAIT, CKS2 to CKS0) Enable interrupt (STOPIM, HNDS, ALIE, ALSL, FNC1, and FNC0) Set interrupt enable, transfer mode, and acknowledge decision (IEIC, MST, TRS, and ACKE)
Figure 18.6 Sample Flowchart for IIC Initialization Note: Be sure to modify the ICMR register after transmit/receive operation has been completed. If the ICMR register is modified during transmit/receive operation, bit counter BC2 to BC0 will be modified erroneously, thus causing incorrect operation. 18.4.3
2
Master Transmit Operation
In I C bus format master transmit mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal.
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Section 18 I2C Bus Interface (IIC)
Figure 18.7 shows the sample flowchart for the operations in master transmit mode.
Start Initialize IIC [1] Initialization
Read BBSY in ICCR No [2] Test the status of the SCL and SDA lines. BBSY = 0? Yes Set MST = 1 and TRS = 1 in ICCR Set BBSY =1 and SCP = 0 in ICCR Read IRIC in ICCR [5] Wait for a start condition generation No IRIC = 1? Yes Write transmit data in ICDR Clear IRIC in ICCR [6] Set transmit data for the first byte (slave address + R/W). (After writing to ICDR, clear IRIC continuously.) [7] Wait for 1 byte to be transmitted. [3] Select master transmit mode.
[4] Start condition issuance
Read IRIC in ICCR No IRIC = 1? Yes Read ACKB in ICSR ACKB = 0? Yes Transmit mode? Yes Write transmit data in ICDR Clear IRIC in ICCR Read IRIC in ICCR No No
[8] Test the acknowledge bit transferred from the slave device.
Master receive mode
[9] Set transmit data for the second and subsequent bytes. (After writing to ICDR, clear IRIC immediately.) [10] Wait for 1 byte to be transmitted.
No
IRIC = 1? Yes Read ACKB in ICSR [11] Determine end of transfer
No
End of transmission? (ACKB = 1?)
Yes Clear IRIC in ICCR Set BBSY = 0 and SCP = 0 in ICCR End [12] Stop condition issuance
Figure 18.7 Sample Flowchart for Operations in Master Transmit Mode
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Section 18 I2C Bus Interface (IIC)
The transmission procedure and operations by which data is sequentially transmitted in synchronization with ICDR (ICDRT) write operations, are described below. 1. Initialize the IIC as described in section 18.4.2, Initialization. 2. Read the BBSY flag in ICCR to confirm that the bus is free. 3. Set bits MST and TRS to 1 in ICCR to select master transmit mode. 4. Write 1 to BBSY and 0 to SCP in ICCR. This changes SDA from high to low when SCL is high, and generates the start condition. 5. Then the IRIC and IRTR flags are set to 1. If the IEIC bit in ICCR has been set to 1, an interrupt request is sent to the CPU. 6. Write the data (slave address + R/W) to ICDR. With the I C bus format (when the FS bit in SAR or the FSX bit in SARX is 0), the first frame data following the start condition indicates the 7-bit slave address and transmit/receive direction (R/W). To determine the end of the transfer, the IRIC flag is cleared to 0. After writing to ICDR, clear IRIC continuously so no other interrupt handling routine is executed. If the time for transmission of one frame of data has passed before the IRIC clearing, the end of transmission cannot be determined. The master device sequentially sends the transmission clock and the data written to ICDR. The selected slave device (i.e. the slave device with the matching slave address) drives SDA low at the 9th transmit clock pulse and returns an acknowledge signal. 7. When one frame of data has been transmitted, the IRIC flag is set to 1 at the rise of the 9th transmit clock pulse. After one frame has been transmitted, SCL is automatically fixed low in synchronization with the internal clock until the next transmit data is written. 8. Read the ACKB bit in ICSR to confirm that ACKB is cleared to 0. When the slave device has not acknowledged (ACKB bit is 1), operate step [12] to end transmission, and retry the transmit operation. 9. Write the transmit data to ICDR. As indicating the end of the transfer, the IRIC flag is cleared to 0. Perform the ICDR write and the IRIC flag clearing sequentially, just as in step [6]. Transmission of the next frame is performed in synchronization with the internal clock. 10. When one frame of data has been transmitted, the IRIC flag is set to 1 at the rise of the 9th transmit clock pulse. After one frame has been transmitted, SCL is automatically fixed low in synchronization with the internal clock until the next transmit data is written. 11. Read the ACKB bit in ICSR. Confirm that the slave device has been acknowledged (ACKB bit is 0). When there is still data to be transmitted, go to step [9] to continue the next transmission operation. When the slave device has not acknowledged (ACKB bit is set to 1), operate step [12] to end transmission.
2
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Section 18 I2C Bus Interface (IIC)
12. Clear the IRIC flag to 0. Write 0 to ACKE in ICCR, to clear received ACKB contents to 0. Write 0 to BBSY and SCP in ICCR. This changes SDA from low to high when SCL is high, and generates the stop condition.
Start condition generation SCL (master output) SDA (master output) SDA (slave output) ICDRE 1 Bit 7 2 Bit 6 3 Bit 5 4 Bit 4 5 Bit 3 6 Bit 2 7 Bit 1 8 Bit 0 R/W [7] A 9 1 Bit 7 2 Bit 6
Slave address [5]
Data 1
IRIC
Interrupt request
Interrupt request
IRTR
ICDRT
Address + R/W
Data 1
ICDRS
Address + R/W
Data 1
Note: Do not set ICDR during this period.
User processing
[4] BBSY set to 1 and [6] ICDR write SCP cleared to 0 (start condition issuance)
[6] IRIC clear
[9] ICDR write
[9] IRIC clear
Figure 18.8 Operation Timing Example in Master Transmit Mode (MLS = WAIT = 0)
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Section 18 I2C Bus Interface (IIC)
Stop condition issuance SCL (master output) 8 9 1 Bit 7 [7] A 2 Bit 6 3 Bit 5 4 Bit 4 5 Bit 3 6 Bit 2 7 Bit 1 8 Bit 0 [10] A 9
SDA Bit 0 (master output) Data 1 SDA (slave output) ICDRE
Data 2
IRIC
IRTR
ICDR
Data 1
Data 2
User processing
[9] ICDR write
[9] IRIC clear
[11] ACKB read
[12] BBSY set to 1 and SCP cleared to 0 (Stop condition issuance) [12] IRIC clear
Figure 18.9 Stop Condition Issuance Operation Timing Example in Master Transmit Mode (MLS = WAIT = 0) 18.4.4
2
Master Receive Operation
In I C bus format master receive mode, the master device outputs the receive clock, receives data, and returns an acknowledge signal. The slave device transmits data. The master device transmits data containing the slave address and R/W (1: read) in the first frame following the start condition issuance in master transmit mode, selects the slave device, and then switches the mode for receive operation.
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Section 18 I2C Bus Interface (IIC)
Receive Operation Using the HNDS Function (HNDS = 1): Figure 18.10 shows the sample flowchart for the operations in master receive mode (HNDS = 1).
Master receive mode Set TRS = 0 in ICCR Set ACKB = 0 in ICSR Set HNDS = 1 in ICXR Clear IRIC in ICCR [1] Select receive mode.
Last receive? No Read ICDR Read IRIC in ICCR No IRIC = 1? Yes Clear IRIC in ICCR
Yes
[2] Start receiving. The first read is a dummy read. [5] Read the receive data (for the second and subsequent read)
[3] Wait for 1 byte to be received. (Set IRIC at the rise of the 9th clock for the receive frame)
[4] Clear IRIC.
Set ACKB = 1 in ICSR Read ICDR Read IRIC in ICCR No IRIC = 1? Yes Clear IRIC in ICCR Set TRS = 1 in ICCR Read ICDR Set BBSY = 0 and SCP = 0 in ICCR End
[6] Set acknowledge data for the last reception. [7] Read the receive data. Dummy read to start receiving if the first frame is the last receive data. [8] Wait for 1 byte to be received.
[9] Clear IRIC. [10] Read the receive data.
[11] Set stop condition issuance. Generate stop condition.
Figure 18.10 Sample Flowchart for Operations in Master Receive Mode (HNDS = 1)
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Section 18 I2C Bus Interface (IIC)
The reception procedure and operations by which the data reception process is provided in 1-byte units with SCL fixed low at each data reception are described below. 1. Clear the TRS bit in ICCR to 0 to switch from transmit mode to receive mode. Clear the ACKB bit in ICSR to 0 (acknowledge data setting). Set the HNDS bit in ICXR to 1. Clear the IRIC flag to 0 to determine the end of reception. Go to step [6] to halt reception operation if the first frame is the last receive data. 2. When ICDR is read (dummy data read), reception is started, and the receive clock is output, and data received, in synchronization with the internal clock. (Data from the SDA pin is sequentially transferred to ICDRS in synchronization with the rise of the receive clock pulses.) 3. The master device drives SDA low to return the acknowledge data at the 9th receive clock pulse. The receive data is transferred to ICDRR from ICDRS at the rise of the 9th clock pulse, setting the ICDRF, IRIC, and IRTR flags to 1. If the IEIC bit has been set to 1, an interrupt request is sent to the CPU. The master device drives SCL low from the fall of the 9th receive clock pulse to the ICDR data reading. 4. Clear the IRIC flag to determine the next interrupt. Go to step [6] to halt reception operation if the next frame is the last receive data. 5. Read ICDR receive data. This clears the ICDRF flag to 0. The master device outputs the receive clock continuously to receive the next data. Data can be received continuously by repeating steps [3] to [5]. 6. Set the ACKB bit to 1 so as to return the acknowledge data for the last reception. 7. Read ICDR receive data. This clears the ICDRF flag to 0. The master device outputs the receive clock to receive data. 8. When one frame of data has been received, the ICDRF, IRIC, and IRTR flags are set to 1 at the rise of the 9th receive clock pulse. 9. Clear the IRIC flag to 0. 10. Read ICDR receive data after setting the TRS bit. This clears the ICDRF flag to 0. 11. Clear the BBSY bit and SCP bit to 0 in ICCR. This changes SDA from low to high when SCL is high, and generates the stop condition.
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Section 18 I2C Bus Interface (IIC)
Master transmit mode
Master receive mode SCL is fixed low until ICDR is read SCL is fixed low until ICDR is read 5 Bit 3 6 Bit 2 7 Bit 1 8 Bit 0 [3] A 9 1 Bit 7 2 Bit 6
SCL (master output) SDA (slave output) SDA (master output) IRIC IRTR ICDRF ICDRR
9 A
1 Bit 7
2 Bit 6
3 Bit 5
4 Bit 4
Data 1
Data 2
Undefined value
Data 1
User processing
[1] TRS cleared to 0 [1] IRIC clear
[2] ICDR read (Dummy read)
[4] IRIC clear
[6] ICDR read (Data 1)
Figure 18.11 Master Receive Mode Operation Timing Example (MLS = WAIT = 0, HNDS = 1)
Stop condition generation
SCL is fixed low until ICDR is read SCL (master output) SDA (slave output) SDA (master output) IRIC IRTR ICDRF ICDRR Data 1 Data 2 7 Bit 1 8 Bit 0 [3] A 9 1 Bit 7 2 Bit 6 3 Bit 5 4 Bit 4 5 Bit 3
SCL is fixed low until ICDR is read 6 Bit 2 7 Bit 1 8 Bit 0 [8] A 9
Data 2
Data 3
Data 3 [10] ICDR read (Data 3) [11] BBSY cleared to 0 and SCP cleared to 0 (Stop condition instruction issuance)
User processing
[4] IRIC clear
[7] ICDR read (Data 2) [6] ACKB set to 1
[9] IRIC clear
Figure 18.12 Stop Condition Issuance Timing Example in Master Receive Mode (MLS = WAIT = 0, HNDS = 1)
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Section 18 I2C Bus Interface (IIC)
Receive Operation Using the Wait Function: Figures 18.13 and 18.14 show the sample flowcharts for the operations in master receive mode (WAIT = 1).
Master receive mode Set TRS = 0 in ICCR Set ACKB = 0 in ICSR Set HNDS = 0 in ICXR Clear IRIC in ICCR Set WAIT = 1 in ICMR Read ICDR [2] Start receiving. The first read is a dummy read. [3] Wait for a receive wait (Set IRIC at the fall of the 8th clock) or, Wait for 1 byte to be received (Set IRIC at the rise of the 9th clock) [4] Determine end of reception IRTR = 1? Yes Last receive? No Read ICDR Clear IRIC in ICCR [5] Read the receive data. [6] Clear IRIC. (to end the wait insertion) Yes [1] Select receive mode.
Read IRIC in ICCR No IRIC = 1? Yes No
Set ACKB = 1 in ICSR Wait for one clock pulse Set TRS = 1 in ICCR Read ICDR Clear IRIC in ICCR
[7] Set acknowledge data for the last reception. [8] Wait for TRS setting [9] Set TRS for stop condition issuance [10] Read the receive data. [11] Clear IRIC.
Read IRIC in ICCR No IRIC=1? Yes IRTR=1? No Clear IRIC in ICCR Yes
[12] Wait for a receive wait (Set IRIC at the fall of the 8th clock) or, Wait for 1 byte to be received (Set IRIC at the rise of the 9th clock) [13] Determine end of reception
[14] Clear IRIC. (to end the wait insertion)
Set WAIT = 0 in ICMR Clear IRIC in ICCR Read ICDR Set BBSY= 0 and SCP= 0 in ICCR End
[15] Clear wait mode. Clear IRIC. ( IRIC should be cleared to 0 after setting WAIT = 0.) [16] Read the last receive data. [17] Generate stop condition
Figure 18.13 Sample Flowchart for Operations in Master Receive Mode (receiving multiple bytes) (WAIT = 1)
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Section 18 I2C Bus Interface (IIC)
Master receive mode Set TRS = 0 in ICCR Set ACKB = 0 in ICSR Set HNDS = 0 in ICXR Clear IRIC in ICCR Set WAIT = 0 in ICMR [1] Select receive mode.
Read ICDR
[2] Start receiving. The first read is a dummy read.
Read IRIC in ICCR
No
IRIC = 1?
[3] Wait for a receive wait (Set IRIC at the fall of the 8 th clock)
Yes
Set ACKB = 1 in ICSR Set TRS = 1 in ICCR Clear IRIC in ICCR [7] Set acknowledge data for the last reception. [9] Set TRS for stop condition issuance [14] Clear IRIC. (to end the wait insertion) [12] Wait for 1 byte to be received. (Set IRIC at the rise of the 9th clock)
Read IRIC in ICCR
No
IRIC = 1?
Yes
Set WAIT = 0 in ICMR Clear IRIC in ICCR [15] Clear wait mode. Clear IRIC. ( IRIC should be cleared to 0 after setting WAIT = 0.) [16] Read the last receive data [17] Generate stop condition
Read ICDR
Set BBSY = 0 and SCP = 0 in ICCR
End
Figure 18.14 Sample Flowchart for Operations in Master Receive Mode (receiving a single byte) (WAIT = 1) The reception procedure and operations using the wait function (WAIT bit), by which data is sequentially received in synchronization with ICDR (ICDRR) read operations, are described below. The following describes the multiple-byte reception procedure. In single-byte reception, some steps of the following procedure are omitted. At this time, follow the procedure shown in figure 18.14.
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Section 18 I2C Bus Interface (IIC)
1. Clear the TRS bit in ICCR to 0 to switch from transmit mode to receive mode. Clear the ACKB bit in ICSR to 0 to set the acknowledge data. Clear the HNDS bit in ICXR to 0 to cancel the handshake function. Clear the IRIC flag to 0, and then set the WAIT bit in ICMR to 1. 2. When ICDR is read (dummy data is read), reception is started, and the receive clock is output, and data received, in synchronization with the internal clock. 3. The IRIC flag is set to 1 in either of the following cases. If the IEIC bit in ICCR has been set to 1, an interrupt request is sent to the CPU. (1) At the fall of the 8th receive clock pulse for one frame SCL is automatically fixed low in synchronization with the internal clock until the IRIC flag clearing. (2) At the rise of the 9th receive clock pulse for one frame The IRTR and ICDRF flags are set to 1, indicating that one frame of data has been received. The master device outputs the receive clock continuously to receive the next data. 4. Read the IRTR flag in ICSR. If the IRTR flag is 0, execute step [6] to clear the IRIC flag to 0 to release the wait state. If the IRTR flag is 1 and the next data is the last receive data, execute step [7] to halt reception. 5. If IRTR flag is 1, read ICDR receive data. 6. Clear the IRIC flag. When the flag is set as (1) in step [3], the master device outputs the 9th clock and drives SDA low at the 9th receive clock pulse to return an acknowledge signal. Data can be received continuously by repeating steps [3] to [6]. 7. Set the ACKB bit in ICSR to 1 so as to return the acknowledge data for the last reception. 8. After the IRIC flag is set to 1, wait for at least one clock pulse until the rise of the first clock pulse for the next receive data. 9. Set the TRS bit in ICCR to 1 to switch from receive mode to transmit mode. The TRS bit value becomes valid when the rising edge of the next 9th clock pulse is input. 10. Read the ICDR receive data. 11. Clear the IRIC flag to 0.
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Section 18 I2C Bus Interface (IIC)
12. The IRIC flag is set to 1 in either of the following cases. (1) At the fall of the 8th receive clock pulse for one frame SCL is automatically fixed low in synchronization with the internal clock until the IRIC flag is cleared. (2) At the rise of the 9th receive clock pulse for one frame The IRTR and ICDRF flags are set to 1, indicating that one frame of data has been received. 13. Read the IRTR flag in ICSR. If the IRTR flag is 0, execute step [14] to clear the IRIC flag to 0 to release the wait state. If the IRTR flag is 1 and data reception is complete, execute step [15] to issue the stop condition. 14. If IRTR flag is 0, clear the IRIC flag to 0 to release the wait state. Execute step [12] to read the IRIC flag to detect the end of reception. 15. Clear the WAIT bit in ICMR to cancel the wait mode. Clearing of the IRIC flag should be done while WAIT = 0. (If the WAIT bit is cleared to 0 after clearing the IRIC flag and then an instruction to issue a stop condition is executed, the stop condition may not be issued correctly.) 16. Read the last ICDR receive data. 17. Clear the BBSY bit and SCP bit to 0 in ICCR. This changes SDA from low to high when SCL is high, and generates the stop condition.
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Section 18 I2C Bus Interface (IIC)
Master transmit mode
Master receive mode
SCL (master output)
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
SDA (slave output) SDA (master output)
A
Bit 7
Bit 6
Bit 5
Bit 4 Data 1
Bit 3
Bit 2
Bit 1
Bit 0 [3] A [3]
Bit 7
Bit 6
Bit 5 Data 2
Bit 4
Bit 3
IRIC
IRTR
[4]IRTR=0
[4] IRTR=1
ICDR
Data 1
User processing [1] TRS cleared to 0 IRIC clear to 0
[2] ICDR read (dummy read)
[6] IRIC clear [5] ICDR read [6] IRIC clear (to end wait insertion) (Data 1)
Figure 18.15 Master Receive Mode Operation Timing Example (MLS = ACKB = 0, WAIT = 1)
[8] Wait for one clock pulse
Stop condition generation SCL (master output) 8 9 1 Bit 7 [3] A 2 Bit 6 3 Bit 5 4 Bit 4 5 Bit 3 6 Bit 2 7 Bit 1 8 Bit 0 [12] A [12] 9
SDA Bit 0 (slave output) Data 2 [3] SDA (master output) IRIC IRTR ICDR
[4] IRTR=0
Data 3
[4] IRTR=1
[13] IRTR=0
[13] IRTR=1
Data 1
Data 2
Data 3 [15] WAIT cleared to 0, IRIC clear [14] IRIC clear (to end wait insertion) [17] Stop condition issuance [16] ICDR read (Data 3)
User processing
[6] IRIC clear (to end wait insertion)
[11] IRIC clear [10] ICDR read (Data 2) [9] Set TRS=1
[7] Set ACKB=1
Figure 18.16 Stop Condition Issuance Timing Example in Master Receive Mode (MLS = ACKB = 0, WAIT = 1)
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Section 18 I2C Bus Interface (IIC)
18.4.5
2
Slave Receive Operation
In I C bus format slave receive mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. The slave device operates as the device specified by the master device when the slave address in the first frame following the start condition that is issued by the master device matches its own address.
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Section 18 I2C Bus Interface (IIC)
Receive Operation Using the HNDS Function (HNDS = 1): Figure 18.17 shows the sample flowchart for the operations in slave receive mode (HNDS = 1).
Slave receive mode Initialize IIC Set MST = 0 and TRS = 0 in ICCR Set ACKB = 0 in ICSR and HNDS = 1 in ICXR Clear IRIC in ICCR
ICDRF = 1? Yes No
[1] Initialization. Select slave receive mode.
[2] Read the receive data remaining unread.
ReadICDR, clear IRIC Read IRIC in ICCR
No IRIC = 1? Yes
[3] to [7] Wait for one byte to be received (slave address + R/W)
Clear IRIC in ICCR Read AASX, AAS and ADZ in ICSR AAS = 1 and ADZ = 1?
No Yes
[8] Clear IRIC
General call address processing * Description omitted
Yes
Read TRS in ICCR TRS = 1?
No No
Slave transmit mode
Last reception?
Yes
Read ICDR
[10] Read the receive data. The first read is a dummy read.
Read IRIC in ICCR
No IRIC = 1? Yes
[5] to [7] Wait for the reception to end.
Clear IRIC in ICCR Set ACKB = 1 in ICSR Read ICDR Read IRIC in ICCR
No IRIC = 1? Yes ESTP = 1 or STOP = 1? No
[8] Clear IRIC
[9] Set acknowledge data for the last reception. [10] Read the receive data. [5] to [7] Wait for the reception to end. or [11] Detect stop condition [12] Check STOP
Yes
Clear IRIC in ICCR
[8] Clear IRIC
Clear IRIC in ICCR End
[12] Clear IRIC
Figure 18.17 Sample Flowchart for Operations in Slave Receive Mode (HNDS = 1)
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Section 18 I2C Bus Interface (IIC)
The reception procedure and operations using the HNDS bit function by which data reception process is provided in 1-byte unit with SCL being fixed low at every data reception, are described below. 1. Initialize the IIC as described in section 18.4.2, Initialization. Clear the MST and TRS bits to 0 to set slave receive mode, and set the HNDS bit to 1 and the ACKB bit to 0. Clear the IRIC flag in ICCR to 0 to see the end of reception. 2. Confirm that the ICDRF flag is 0. If the ICDRF flag is set to 1, read the ICDR and then clear the IRIC flag to 0. 3. When the start condition output by the master device is detected, the BBSY flag in ICCR is set to 1. The master device then outputs the 7-bit slave address, and transmit/receive direction (R/W), in synchronization with the transmit clock pulses. 4. When the slave address matches in the first frame following the start condition, the device operates as the slave device specified by the master device. If the 8th data bit (R/W) is 0, the TRS bit remains cleared to 0, and slave receive operation is performed. If the 8th data bit (R/W) is 1, the TRS bit is set to 1, and slave transmit operation is performed. When the slave address does not match, receive operation is halted until the next start condition is detected. 5. At the 9th clock pulse of the receive frame, the slave device returns the data in the ACKB bit as the acknowledge data. 6. At the rise of the 9th clock pulse, the IRIC flag is set to 1. If the IEIC bit has been set to 1, an interrupt request is sent to the CPU. If the AASX bit has been set to 1, IRTR flag is also set to 1. 7. At the rise of the 9th clock pulse, the receive data is transferred from ICDRS to ICDRR, setting the ICDRF flag to 1. The slave device drives SCL low from the fall of the 9th receive clock pulse until data is read from ICDR. 8. Confirm that the STOP bit is cleared to 0, and clear the IRIC flag to 0. 9. If the next frame is the last receive frame, set the ACKB bit to 1. 10. If ICDR is read, the ICDRF flag is cleared to 0, releasing the SCL bus line. This enables the master device to transfer the next data. Receive operations can be performed continuously by repeating steps [5] to [10]. 11. When the stop condition is detected (SDA is changed from low to high when SCL is high), the BBSY flag is cleared to 0 and the STOP bit is set to 1. If the STOPIM bit has been cleared to 0, the IRIC flag is set to 1. 12. Confirm that the STOP bit is set to 1, and clear the IRIC flag to 0.
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Section 18 I2C Bus Interface (IIC)
Start condition generation SCL (Pin waveform) SCL (master output) SCL (slave output) SDA (master output) SDA (slave output)
IRIC 1 1 2 2 3 3 4 4 5 5 6 6 7 7
[7] SCL is fixed low until ICDR is read
8 8 9 9 1 1 2 2
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
Bit 7
Bit 6 Data 1
Slave address
[6]
A
Interrupt request occurrence
ICDRF
ICDRS
Address+R/W
ICDRR
Undefined value
Address+R/W
User processing
[2] ICDR read
[8] IRIC clear
[10] ICDR read (dummy read)
Figure 18.18 Slave Receive Mode Operation Timing Example (1) (MLS = 0, HNDS= 1)
Stop condition generation
[7] SCL is fixed low until ICDR is read SCL (master output) SCL (slave output) SDA (master output) Data (n-1) SDA (slave output) IRIC
Bit 0 Bit 7 Bit 6 Bit 5 Bit 4
8 9 1 2 3 4 5
[7] SCL is fixed low until ICDR is read
6 7 8 9
Bit 3
Bit 2
Bit 1
Bit 0
[6]
Data (n)
[6]
[11]
A
A
ICDRF
ICDRS ICDRR
Data (n-1)
Data (n) Data (n-1) Data (n)
Data (n-2)
User processing
[8] IRIC clear [10] ICDR read (Data (n-1)) [9] Set ACKB=1
[8] IRIC clear
[10] ICDR read (Data (n))
[12] IRIC clear
Figure 18.19 Slave Receive Mode Operation Timing Example (2) (MLS = 0, HNDS= 1)
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Section 18 I2C Bus Interface (IIC)
Continuous Receive Operation: Figure 18.20 shows the sample flowchart for the operations in slave receive mode (HNDS = 0).
Slave receive mode Set MST = 0 and TRS = 0 in ICCR Set ACKB = 0 in ICSR Set HNDS = 0 in ICXR Clear IRIC in ICCR ICDRF = 1? Yes Read ICDR Clear IRIC in ICCR Read IRIC in ICCR No IRIC = 1? Yes Clear IRIC in ICCR Read AASX, AAS and ADZ in ICSR AAS = 1 and ADZ = 1? No Read TRS in ICCR TRS = 1? No No Yes Yes No
[1] Select slave receive mode.
[2] Read the receive data remaining unread.
[3] to [7] Wait for one byte to be received (slave address + R/W) (Set IRIC at the rise of the 9th clock)
[8] Clear IRIC
General call address processing * Description omitted
Slave transmit mode
* n: Address + total number of bytes received
(n-2)th-byte reception? Wait for one frame Set ACKB = 1 in ICSR ICDRF = 1? Yes Read ICDR Read IRIC in ICCR No IRIC = 1?
[9] Wait for ACKB setting and set acknowledge data for the last reception (after the rise of the 9th clock of (n-1)th byte data)
No
[10] Read the receive data. The first read is a dummy read.
[11] Wait for one byte to be received (Set IRIC at the rise of the 9th clock)
ESTP = 1 or STOP = 1? No Clear IRIC in ICCR
Yes
[12] Detect stop condition
[13] Clear IRIC
ICDRF = 1? Yes Read ICDR Clear IRIC in ICCR End
No
[14] Read the last receive data
[15] Clear IRIC
Figure 18.20 Sample Flowchart for Operations in Slave Receive Mode (HNDS = 0)
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Section 18 I2C Bus Interface (IIC)
The reception procedure and operations in slave receive are described below. 1. Initialize the IIC as described in section 18.4.2, Initialization. Clear the MST and TRS bits to 0 to set slave receive mode, and set the HNDS and ACKB bits to 0. Clear the IRIC flag in ICCR to 0 to see the end of reception. 2. Confirm that the ICDRF flag is 0. If the ICDRF flag is set to 1, read the ICDR and then clear the IRIC flag to 0. 3. When the start condition output by the master device is detected, the BBSY flag in ICCR is set to 1. The master device then outputs the 7-bit slave address, and transmit/receive direction (R/W) in synchronization with the transmit clock pulses. 4. When the slave address matches in the first frame following the start condition, the device operates as the slave device specified by the master device. If the 8th data bit (R/W) is 0, the TRS bit remains cleared to 0, and slave receive operation is performed. If the 8th data bit (R/W) is 1, the TRS bit is set to 1, and slave transmit operation is performed. When the slave address does not match, receive operation is halted until the next start condition is detected. 5. At the 9th clock pulse of the receive frame, the slave device returns the data in the ACKB bit as the acknowledge data. 6. At the rise of the 9th clock pulse, the IRIC flag is set to 1. If the IEIC bit has been set to 1, an interrupt request is sent to the CPU. If the AASX bit has been set to 1, the IRTR flag is also set to 1. 7. At the rise of the 9th clock pulse, the receive data is transferred from ICDRS to ICDRR, setting the ICDRF flag to 1. 8. Confirm that the STOP bit is cleared to 0 and clear the IRIC flag to 0. 9. If the next read data is the third last receive frame, wait for at least one frame time to set the ACKB bit. Set the ACKB bit after the rise of the 9th clock pulse of the second last receive frame. 10. Confirm that the ICDRF flag is set to 1 and read ICDR. This clears the ICDRF flag to 0. 11. At the rise of the 9th clock pulse or when the receive data is transferred from IRDRS to ICDRR due to ICDR read operation, The IRIC and ICDRF flags are set to 1. 12. When the stop condition is detected (SDA is changed from low to high when SCL is high), the BBSY flag is cleared to 0 and the STOP or ESTP flag is set to 1. If the STOPIM bit has been cleared to 0, the IRIC flag is set to 1. In this case, execute step 14 to read the last receive data. 13. Clear the IRIC flag to 0.
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Section 18 I2C Bus Interface (IIC)
Receive operations can be performed continuously by repeating steps 9 to 13. 14. Confirm that the ICDRF flag is set to 1, and read ICDR. 15. Clear the IRIC flag.
Start condition issuance SCL (master output) SDA (master output) SDA (slave output) IRIC 1 Bit 7 2 Bit 6 3 Bit 5 4 Bit 4 5 Bit 3 6 Bit 2 7 Bit 1 8 Bit 0 R/W [6] A 9 1 Bit 7 2 Bit 6 Data 1 3 Bit 5 4 Bit 4
Slave address
ICDRF
ICDRS
Address+R/W [7]
Data 1
ICDRR
Address+R/W
User processing
[8] IRIC clear [10] ICDR read
Figure 18.21 Slave Receive Mode Operation Timing Example (1) (MLS = ACKB = 0, HNDS = 0)
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Section 18 I2C Bus Interface (IIC)
Stop condition detection SCL (master output) 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
SDA (master output) Bit 0 Data (n-2) SDA (slave output) IRIC ICDRF ICDRS ICDRR User processing Data (n-2)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 [11] A Data (n-1) [11] A
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Data (n) [11] A [12]
Data (n-1) Data (n-2) [9] Wait for one frame [13] IRIC clear Data (n-1)
Data (n) Data (n)
[13] IRIC clear [10] ICDR read [10] ICDR read (Data (n-1)) (Data (n-2)) [9] Set ACKB = 1
[13] IRIC clear [14] ICDR read (Data (n)) [15] IRIC clear
Figure 18.22 Slave Receive Mode Operation Timing Example (2) (MLS = ACKB = 0, HNDS = 0)
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Section 18 I2C Bus Interface (IIC)
18.4.6
Slave Transmit Operation
If the slave address matches to the address in the first frame (address reception frame) following the start condition detection when the 8th bit data (R/W) is 1 (read), the TRS bit in ICCR is automatically set to 1 and the mode changes to slave transmit mode. Figure 18.23 shows the sample flowchart for the operations in slave transmit mode.
Slave transmit mode Clear IRIC in ICCR Write transmit data in ICDR Clear IRIC in ICCR Read IRIC in ICCR [1], [2] If the slave address matches to the address in the first frame following the start condition detection and the R/W bit is 1 in slave receive mode, the mode changes to slave transmit mode. [3], [5] Set transmit data for the second and subsequent bytes.
[3], [4] Wait for 1 byte to be transmitted.
No
IRIC = 1?
Yes
Read ACKB in ICSR [4] Determine end of transfer.
No
End of transmission (ACKB = 1)?
Yes
Clear IRIC in ICCR [6] Clear IRIC in ICCR [7] Clear acknowledge bit data [8] Set slave receive mode. [9] Dummy read (to release the SCL line). [10] Wait for stop condition
Clear ACKE to 0 in ICCR (ACKB=0 clear)
Set TRS = 0 in ICCR Read ICDR Read IRIC in ICCR
No
IRIC = 1?
Yes
Clear IRIC in ICCR End
Figure 18.23 Sample Flowchart for Slave Transmit Mode
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Section 18 I2C Bus Interface (IIC)
In slave transmit mode, the slave device outputs the transmit data, while the master device outputs the receive clock and returns an acknowledge signal. The transmission procedure and operations in slave transmit mode are described below. 1. Initialize slave receive mode and wait for slave address reception. 2. When the slave address matches in the first frame following detection of the start condition, the slave device drives SDA low at the 9th clock pulse and returns an acknowledge signal. If the 8th data bit (R/W) is 1, the TRS bit in ICCR is set to 1, and the mode changes to slave transmit mode automatically. The IRIC flag is set to 1 at the rise of the 9th clock. If the IEIC bit in ICCR has been set to 1, an interrupt request is sent to the CPU. At the same time, the ICDRE flag is set to 1. The slave device drives SCL low from the fall of the 9th transmit clock until ICDR data is written, to disable the master device to output the next transfer clock. 3. After clearing the IRIC flag to 0, write data to ICDR. At this time, the ICDRE flag is cleared to 0. The written data is transferred to ICDRS, and the ICDRE and IRIC flags are set to 1 again. The slave device sequentially sends the data written into ICDRS in accordance with the clock output by the master device. The IRIC flag is cleared to 0 to detect the end of transmission. Processing from the ICDR register writing to the IRIC flag clearing should be performed continuously. Prevent any other interrupt processing from being inserted. 4. The master device drives SDA low at the 9th clock pulse, and returns an acknowledge signal. As this acknowledge signal is stored in the ACKB bit in ICSR, this bit can be used to determine whether the transfer operation was performed successfully. When one frame of data has been transmitted, the IRIC flag in ICCR is set to 1 at the rise of the 9th transmit clock pulse. When the ICDRE flag is 0, the data written into ICDR is transferred to ICDRS and the ICDRE and IRIC flags are set to 1 again. If the ICDRE flag has been set to 1, this slave device drives SCL low from the fall of the 9th transmit clock until data is written to ICDR. 5. To continue transmission, write the next data to be transmitted into ICDR. The ICDRE flag is cleared to 0. The IRIC flag is cleared to 0 to detect the end of transmission. Processing from the ICDR register writing to the IRIC flag clearing should be performed continuously. Prevent any other interrupt processing from being inserted. Transmit operations can be performed continuously by repeating steps 4 and 5. 6. Clear the IRIC flag to 0. 7. To end transmission, clear the ACKE bit in the ICCR register to 0, to clear the acknowledge bit stored in the ACKB bit to 0. 8. Clear the TRS bit to 0 for the next address reception, to set slave receive mode. 9. Dummy-read ICDR to release SCL on the slave side.
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Section 18 I2C Bus Interface (IIC)
10. When the stop condition is detected, that is, when SDA is changed from low to high when SCL is high, the BBSY flag in ICCR is cleared to 0 and the STOP flag in ICSR is set to 1. When the STOPIM bit in ICXR is 0, the IRIC flag is set to 1. If the IRIC flag has been set, it is cleared to 0.
Slave receive mode SCL (master output) SDA (slave output) Slave transmit mode
8
9
1
2
3
4
5
6
7
8
9
1
2
A
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
[2]
Data 1
[4]
Data 2
SDA (master output) R/W
A
IRIC
ICDRE
ICDR User processing
[3] IRIC clear [3] ICDR write [3] IRIC clear
Data 1
Data 2
[5] IRIC clear [5] ICDR write
Figure 18.24 Slave Transmit Mode Operation Timing Example (MLS = 0)
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Section 18 I2C Bus Interface (IIC)
18.4.7
IRIC Setting Timing and SCL Control
The interrupt request flag (IRIC) is set at different times depending on the WAIT bit in ICMR, the FS bit in SAR, and the FSX bit in SARX. If the ICDRE or ICDRF flag is set to 1, SCL is automatically held low after one frame has been transferred; this timing is synchronized with the internal clock. Figures 18.25 to 18.27 show the IRIC set timing and SCL control.
When WAIT = 0, and FS = 0 or FSX = 0 (I2C bus format, no wait)
SCL 7 8 9 1 2 3
SDA
7
8
A
1
2
3
IRIC User processing Clear IRIC
(a) Data transfer ends with ICDRE=0 at transmission, or ICDRF=0 at reception.
SCL 7 8 9 1
SDA
7
8
A
1
IRIC User processing Clear IRIC Write to ICDR (transmit) or read from ICDR (receive) Clear IRIC
(b) Data transfer ends with ICDRE=1 at transmission, or ICDRF=1 at reception.
Figure 18.25 IRIC Setting Timing and SCL Control (1)
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Section 18 I2C Bus Interface (IIC)
When WAIT = 1, and FS = 0 or FSX = 0 (I2C bus format, wait inserted)
SCL 8 9 1 2 3
SDA
8
A
1
2
3
IRIC User processing Clear IRIC Clear IRIC
(a) Data transfer ends with ICDRE=0 at transmission, or ICDRF=0 at reception.
SCL 8 9 1
SDA
8
A
1
IRIC User processing Clear IRIC Write to ICDR (transmit) or read from ICDR (receive) Clear IRIC
(b) Data transfer ends with ICDRE=1 at transmission, or ICDRF=1 at reception.
Figure 18.26 IRIC Setting Timing and SCL Control (2)
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Section 18 I2C Bus Interface (IIC)
When FS = 1 and FSX = 1 (clocked synchronous serial format)
SCL 7 8 1 2 3 4
SDA
7
8
1
2
3
4
IRIC User processing Clear IRIC
(a) Data transfer ends with ICDRE=0 at transmission, or ICDRF=0 at reception.
SCL 7 8 1
SDA
7
8
1
IRIC User processing Clear IRIC Write to ICDR (transmit) or read from ICDR (receive) Clear IRIC
(b) Data transfer ends with ICDRE=1 at transmission, or ICDRF=1 at reception.
Figure 18.27 IRIC Setting Timing and SCL Control (3)
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Section 18 I2C Bus Interface (IIC)
18.4.8
Operation Using the DTC
This LSI provides the DTC to allow continuous data transfer. The DTC is initiated when the IRTR flag is set to 1, which is one of the two interrupt flags (IRTR and IRIC). When the ACKE bit is 0, the ICDRE, IRIC, and IRTR flags are set at the end of data transmission regardless of the acknowledge bit value. When the ACKE bit is 1, the ICDRE, IRIC, and IRTR flags are set if data transmission is completed with the acknowledge bit value of 0, and when the ACKE bit is 1, only the IRIC flag is set if data transmission is completed with the acknowledge bit value of 1. When initiated, DTC transfers specified number of bytes, clears the ICDRE, IRIC, and IRTR flags to 0. Therefore, no interrupt is generated during continuous data transfer; however, if data transmission is completed with the acknowledge bit value of 1 when the ACKE bit is 1, DTC is not initiated, thus allowing an interrupt to be generated if enabled. The acknowledge bit may indicate specific events such as completion of receive data processing for some receiving devices, and for other receiving devices, the acknowledge bit may be held to 1, indicating no specific events. The I C bus format provides for selection of the slave device and transfer direction by means of the slave address and the R/W bit, confirmation of reception with the acknowledge bit, indication of the last frame, and so on. Therefore, continuous data transfer using the DTC must be carried out in conjunction with CPU processing by means of interrupts. Table 18.9 shows some examples of processing using the DTC. These examples assume that the number of transfer data bytes is known in slave mode.
2
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Section 18 I2C Bus Interface (IIC)
Table 18.9 Examples of Operation Using the DTC
Item Master Transmit Mode Master Receive Mode Transmission by CPU (ICDR write) Slave Transmit Mode Reception by CPU (ICDR read) Slave Receive Mode Reception by CPU (ICDR read)
Slave address + Transmission by R/W bit DTC (ICDR write) transmission/ reception Dummy data read Actual data transmission/ reception Dummy data (H'FF) write Last frame processing Transfer request processing after last frame processing Transmission by DTC (ICDR write) Not necessary 1st time: Clearing by CPU 2nd time: Stop condition issuance by CPU
Processing by CPU (ICDR read) Reception by DTC (ICDR read) Reception by CPU (ICDR read) Not necessary
Transmission by DTC (ICDR write) Processing by DTC (ICDR write) Not necessary
Reception by DTC (ICDR read) Reception by CPU (ICDR read)
Automatic clearing Not necessary on detection of stop condition during transmission of dummy data (H'FF) Transmission: Reception: Actual Actual data count data count + 1 (+1 equivalent to dummy data (H'FF))
Setting of number of DTC transfer data frames
Transmission: Reception: Actual Actual data count data count + 1 (+1 equivalent to slave address + R/W bits)
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Section 18 I2C Bus Interface (IIC)
18.4.9
Noise Canceler
The logic levels at the SCL and SDA pins are routed through noise cancelers before being latched internally. Figure 18.28 shows a block diagram of the noise canceler. The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA) pin input signal is sampled on the system clock, but is not passed forward to the next circuit unless the outputs of both latches agree. If they do not agree, the previous value is held.
Sampling clock
C SCL or SDA input signal D Latch Q D
C Q Latch Match detector Internal SCL or SDA signal
System clock cycle Sampling clock
Figure 18.28 Block Diagram of Noise Canceler 18.4.10 Initialization of Internal State The IIC has a function for forcible initialization of its internal state if a deadlock occurs during communication. Initialization is executed in accordance with clearing ICE bit. Scope of Initialization: The initialization executed by this function covers the following items: * ICDRE and ICDRF internal flags * Transmit/receive sequencer and internal operating clock counter * Internal latches for retaining the output state of the SCL and SDA pins (wait, clock, data output, etc.)
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Section 18 I2C Bus Interface (IIC)
The following items are not initialized: * Actual register values (ICDR, SAR, SARX, ICMR, ICCR, ICSR, ICXR (other than ICDRE and ICDRF)) * Internal latches used to retain register read information for setting/clearing flags in the ICMR, ICCR, and ICSR registers * The value of the ICMR register bit counter (BC2 to BC0) * Generated interrupt sources (interrupt sources transferred to the interrupt controller) Notes on Initialization: * Interrupt flags and interrupt sources are not cleared, and so flag clearing measures must be taken as necessary. * Basically, other register flags are not cleared either, and so flag clearing measures must be taken as necessary. * If a flag clearing setting is made during transmission/reception, the IIC module will stop transmitting/receiving at that point and the SCL and SDA pins will be released. When transmission/reception is started again, register initialization, etc., must be carried out as necessary to enable correct communication as a system. The value of the BBSY bit cannot be modified directly by this module clear function, but since the stop condition pin waveform is generated according to the state and release timing of the SCL and SDA pins, the BBSY bit may be cleared as a result. Similarly, state switching of other bits and flags may also have an effect. To prevent problems caused by these factors, the following procedure should be used when initializing the IIC state. 1. Execute initialization of the internal state according to the ICE bit clearing. 2. Execute a stop condition issuance instruction (write 0 to BBSY and SCP) to clear the BBSY bit to 0, and wait for two transfer rate clock cycles. 3. Re-execute initialization of the internal state according to the ICE bit clearing. 4. Initialize (re-set) the IIC registers.
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Section 18 I2C Bus Interface (IIC)
18.5
Interrupt Source
The IIC interrupt source is IICI. The IIC interrupt sources and their priority order are shown in table 18.10. Each interrupt source is enabled or disabled by the ICCR interrupt enable bit and transferred to the interrupt controller independently. Table 18.10 IIC Interrupt Source
Channel Bit Name Enable Bit Interrupt Source Interrupt Flag DTC Activation Priority
2 3 0 1 4 5
IICI2 IICI3 IICI0 IICI1 IICI4 IICI5
IEIC IEIC IEIC IEIC IEIC IEIC
I C bus interface interrupt request I C bus interface interrupt request I C bus interface interrupt request I C bus interface interrupt request I C bus interface interrupt request I C bus interface interrupt request
2 2 2 2 2
2
IRIC IRIC IRIC IRIC IRIC IRIC
Possible Possible Possible Possible Not possible Not possible
High
Low
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Section 18 I2C Bus Interface (IIC)
18.6
Usage Notes
1. In master mode, if an instruction to generate a start condition is immediately followed by an instruction to generate a stop condition, neither condition will be output correctly. To output consecutive start and stop conditions*, after issuing the instruction that generates the start 2 condition, read the relevant DR registers of I C bus output pins, check that SCL and SDA are both low. If the ICE bit is set to 1, pin state can be monitored by reading DR register. Then issue the instruction that generates the stop condition. Note that SCL may not yet have gone low when BBSY is cleared to 0. Note: * An illegal procedure in the I C bus specification. 2. Either of the following two conditions will start the next transfer. Pay attention to these conditions when accessing to ICDR. Write to ICDR when ICE = 1 and TRS = 1 (including automatic transfer from ICDRT to ICDRS) Read from ICDR when ICE = 1 and TRS = 0 (including automatic transfer from ICDRS to ICDRR) 3. Table 18.11 shows the timing of SCL and SDA outputs in synchronization with the internal clock. Timings on the bus are determined by the rise and fall times of signals affected by the bus load capacitance, series resistance, and parallel resistance. Table 18.11 I C Bus Timing (SCL and SDA Outputs)
Item SCL output cycle time SCL output high pulse width SCL output low pulse width SDA output bus free time Start condition output hold time Retransmission start condition output setup time Stop condition output setup time Data output setup time (master) Data output setup time (slave) Data output hold time Note: * tSDAHO Symbol Output Timing tSCLO tSCLHO tSCLLO tBUFO tSTAHO tSTASO tSTOSO tSDASO 28 tcyc to 512 tcyc 0.5 tSCLO 0.5 tSCLO 0.5 tSCLO - 1 tcyc 0.5 tSCLO - 1 tcyc 1 tSCLO 0.5 tSCLO + 2 tcyc 1 tSCLLO - 3 tcyc 1 tSCLLO - (6 tcyc or 12 tcyc*) 3 tcyc ns Unit ns ns ns ns ns ns ns ns Notes See figure 31.32 (reference)
2 2
6 tcyc when IICXn is 0, 12 tcyc when IICXn is 1 (n = 0 to 5).
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Section 18 I2C Bus Interface (IIC)
4. SCL and SDA input are sampled in synchronization with the internal clock. The AC timing therefore depends on the system clock cycle tcyc, as shown in section 31, Electrical 2 Characteristics. Note that the I C bus interface AC timing specification will not be met with a system clock frequency of less than 5 MHz. 5. The I C bus interface specification for the SCL rise time tsr is 1000 ns or less (300 ns for high2 speed mode). In master mode, the I C bus interface monitors the SCL line and synchronizes one bit at a time during communication. If tsr (the time for SCL to go from low to VIH) exceeds 2 the time determined by the input clock of the I C bus interface, the high period of SCL is extended. The SCL rise time is determined by the pull-up resistance and load capacitance of the SCL line. To insure proper operation at the set transfer rate, adjust the pull-up resistance and load capacitance so that the SCL rise time does not exceed the values given in table 18.12. Table 18.12 Permissible SCL Rise Time (tsr) Values
Time Indication [ns] TCSS IICXn 0 0 tcyc Indication 7.5 tcyc Standard mode High-speed mode 1 1 1 0 1 37.5 tcyc 17.5 tcyc Standard mode High-speed mode Standard mode High-speed mode I C Bus Specification (Max.) = 20 MHz 1000 300 375 300
2
2
= 25 MHz 300 300
= 34 MHz 221 221
1000 300 1000 300
875 300 1000 300
700 300 1000 300
515 300 1000 300
Note: n = 0 to 5
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Section 18 I2C Bus Interface (IIC)
6. The I C bus interface specifications for the SCL and SDA rise and fall times are under 1000 ns 2 and 300 ns. The I C bus interface SCL and SDA output timing is prescribed by tcyc, as shown in 2 table 18.11. However, because of the rise and fall times, the I C bus interface specifications may not be satisfied at the maximum transfer rate. Table 18.13 shows output timing calculations for different operating frequencies, including the worst-case influence of rise and fall times. tBUFO fails to meet the I C bus interface specifications at any frequency. The solution is either (a) to provide coding to secure the necessary interval (approximately 1 s) between issuance of a stop condition and issuance of a start condition, or (b) to select devices whose input timing 2 permits this output timing for use as slave devices connected to the I C bus. tSCLLO in high-speed mode and tSTASO in standard mode fail to satisfy the I C bus interface specifications for worst-case calculations of tSr/tSf. Possible solutions that should be investigated include (a) adjusting the rise and fall times by means of a pull-up resistor and capacitive load, (b) reducing the transfer rate to meet the specifications, or (c) selecting devices 2 whose input timing permits this output timing for use as slave devices connected to the I C bus.
2 2
2
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Section 18 I2C Bus Interface (IIC)
Table 18.13 I C Bus Timing (with Maximum Influence of tSr/tSf)
Time Indication (at Maximum Transfer Rate) [ns] tSr/tSf Influence (Max.) Standard mode High-speed mode Standard mode High-speed mode tSCLLO 0.5 tSCLO (-tSf) Standard mode High-speed mode tBUFO 0.5 tSCLO -1 tcyc ( -tSr) 0.5 tSCLO -1 tcyc (-tSf) 1 tSCLO (-tSr) Standard mode High-speed mode Standard mode High-speed mode Standard mode High-speed mode tSTOSO 0.5 tSCLO + 2 tcyc (-tSr) 1 tSCLLO*3 -3 tcyc (-tSr)
3 1 tSCLL* -12 2 tcyc* (-tSr) 2
2
Item tSCLHO
tcyc Indication 0.5 tSCLO (-tSr)
I C Bus Specification (Min.) 4000 600 4700 1300 4700 1300 4000 600 4700 600 4000 600 250 100 250 100
= 20 MHz /200 /48 4000 900 4750 950*
1
= 25 MHz /224 /56 3480 820 4230 870*
1
= 34 MHz /224 /80 3706 876 4456 926*
1
-1000 -300 -250 -250 -1000 -300 -250 -250 -1000 -300 -1000 -300 -1000 -300 -1000 -300
3950* 850*
1
1
3440* 780*
1
1
3676* 847*
1
1
tSTAHO
4700 900 9000 2100 4100 1000 3600 500 3100 400
4190 830 7960 1940 3560 900 3110 450 3220 520
4426 897 8412 2053 3765 935 3368 538 3347 64
tSTASO
Standard mode High-speed mode Standard mode High-speed mode Standard mode High-speed mode
tSDASO (master) tSDASO (slave)
tSDAHO
3 tcyc
Standard mode High-speed mode
2
0 0
0 0
150 150
120 120
88 88
Notes: 1. Does not meet the I C bus interface specification. Remedial action such as the following is necessary: (a) secure a start/stop condition issuance interval; (b) adjust the rise and fall times by means of a pull-up resistor and capacitive load; (c) reduce the transfer rate; (d) select slave devices whose input timing permits this output timing. The values in the above table will vary depending on the settings of the bits TCSS, IICX3 to IICX0 and CKS2 to CKS0. Depending on the frequency it may not be possible 2 to achieve the maximum transfer rate; therefore, whether or not the I C bus interface specifications are met must be determined in accordance with the actual setting conditions. 2. Value when the IICXn bit is set to 1. When the IICXn bit is cleared to 0, the value is (- 6tcyc) (n = 0 to 5). 2 3. Calculated using the I C bus specification values (standard mode: 4700 ns min.; highspeed mode: 1300 ns min.).
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Section 18 I2C Bus Interface (IIC)
7. Notes on ICDR register read at end of master reception To halt reception at the end of a receive operation in master receive mode, set the TRS bit to 1 and write 0 to BBSY and SCP in ICCR. This changes SDA from low to high when SCL is high, and generates the stop condition. After this, receive data can be read by means of an ICDR read, but if data remains in the buffer the ICDRS receive data will not be transferred to ICDR, and so it will not be possible to read the second byte of data. If it is necessary to read the second byte of data, issue the stop condition in master receive mode (i.e. with the TRS bit cleared to 0). When reading the receive data, first confirm that the BBSY bit in the ICCR register is cleared to 0, the stop condition has been generated, and the bus has been released, then read the ICDR register with TRS cleared to 0. Note that if the receive data (ICDR data) is read in the interval between execution of the instruction for issuance of the stop condition (writing of 0 to BBSY and SCP in ICCR) and the actual generation of the stop condition, the clock may not be output correctly in subsequent master transmission. Clearing of the MST bit after completion of master transmission/reception, or other modifications of IIC control bits to change the transmit/receive operating mode or settings, must be carried out during interval (a) in figure 18.29 (after confirming that the BBSY bit has been cleared to 0 in the ICCR register).
Stop condition (a) SDA SCL Internal clock BBSY bit Bit 0 8 A 9 Start condition
Master receive mode ICDR read disabled period
Execution of instruction for issuing stop condition (write 0 to BBSY and SCP)
Confirmation of stop condition issuance (read BBSY = 0)
Start condition issuance
Figure 18.29 Notes on Reading Master Receive Data Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to B'11 in ICXR.
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Section 18 I2C Bus Interface (IIC)
8. Notes on start condition issuance for retransmission Figure 18.30 shows the timing of start condition issuance for retransmission, and the timing for subsequently writing data to ICDR, together with the corresponding flowchart. Write the transmit data to ICDR after the start condition for retransmission is issued and then the start condition is actually generated.
IRIC = 1? Yes Clear IRIC in ICCR
No
[1]
[1] Wait for end of 1-byte transfer
[2] Determine whether SCL is low
[3] Issue start condition instruction for retransmission Read SCL pin SCL = Low? Yes Set BBSY = 1, SCP = 0 (ICCR) [3] No [2] [4] Determine whether start condition is generated or not
[5] Set transmit data (slave address + R/W)
IRIC = 1? Yes Write transmit data to ICDR
No
[4]
Note: Program so that processing from [3] to [5] is executed continuously.
[5]
Start condition generation (retransmission) SCL 9
SDA
ACK
Bit 7
IRIC
[5] ICDR write (transmit data) [4] IRIC determination [3] (Retransmission) Start condition instruction issuance [2] Determination of SCL = Low [1] IRIC determination
Figure 18.30 Flowchart for Start Condition Issuance Instruction for Retransmission and Timing Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to B'11 in ICXR.
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Section 18 I2C Bus Interface (IIC)
9. Note on when I C bus interface stop condition instruction is issued In a situation where the rise time of the 9th clock of SCL exceeds the stipulated value because of a large bus load capacity or where a slave device in which a wait can be inserted by driving the SCL pin low is used, the stop condition instruction should be issued after reading SCL after the rise of the 9th clock pulse and determining that it is low.
9th clock VIH Secures a high period
2
SCL
SCL is detected as low because the rise of the waveform is delayed SDA Stop condition generation IRIC [1] SCL = low determination [2] Stop condition instruction issuance
Figure 18.31 Stop Condition Issuance Timing Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to B'11 in ICXR. 10. Note on IRIC flag clear when the wait function is used When the wait function is used in I C bus interface master mode and in a situation where the rise time of SCL exceeds the stipulated value or where a slave device in which a wait can be inserted by driving the SCL pin low is used, the IRIC flag should be cleared after determining that the SCL is low. If the IRIC flag is cleared to 0 when WAIT = 1 while the SCL is extending the high level time, the SDA level may change before the SCL goes low, which may generate a start or stop condition erroneously.
2
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Section 18 I2C Bus Interface (IIC)
Secures a high period SCL VIH SCL = low detected
SDA
IRIC [1] SCL = low determination [2] IRIC clear
Figure 18.32 IRIC Flag Clearing Timing When WAIT = 1 Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to B'11 in ICXR. 11. Note on ICDR register read and ICCR register access in slave transmit mode In I C bus interface slave transmit mode, do not read ICDR or do not read/write from/to ICCR during the time shaded in figure 18.33. However, such read and write operations source no problem in interrupt handling processing that is generated in synchronization with the rising edge of the 9th clock pulse because the shaded time has passed before making the transition to interrupt handling. To handle interrupts securely, be sure to keep either of the following conditions. Read ICDR data that has been received so far or read/write from/to ICCR before starting the receive operation of the next slave address. Monitor the BC2 to BC0 counter in ICMR; when the count is B'000 (8th or 9th clock pulse), wait for at least two transfer clock times in order to read ICDR or read/write from/to ICCR during the time other than the shaded time.
2
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Section 18 I2C Bus Interface (IIC)
Waveform at problem occurrence
SDA
R/W
A
Bit 7
SCL
8
9
TRS bit
Address reception
Data transmission
ICDR read and ICCR read/write are disabled (6 system clock period)
ICDR write
The rise of the 9th clock is detected
Figure 18.33 ICDR Register Read and ICCR Register Access Timing in Slave Transmit Mode Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to B'11 in ICXR. 12. Note on TRS bit setting in slave mode In I C bus interface slave mode, if the TRS bit value in ICCR is set after detecting the rising edge of the 9th clock pulse or the stop condition before detecting the next rising edge on the SCL pin (the time indicated as (a) in figure 18.34), the bit value becomes valid immediately when it is set. However, if the TRS bit is set during the other time (the time indicated as (b) in figure 18.34), the bit value is suspended and remains invalid until the rising edge of the 9th clock pulse or the stop condition is detected. Therefore, when the address is received after the restart condition is input without the stop condition, the effective TRS bit value remains 1 (transmit mode) internally and thus the acknowledge bit is not transmitted after the address has been received at the 9th clock pulse. To receive the address in slave mode, clear the TRS bit to 0 during the time indicated as (a) in figure 18.34. To release the SCL low level that is held by means of the wait function in slave mode, clear the TRS bit to and then dummy-read ICDR.
2
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Section 18 I2C Bus Interface (IIC)
Restart condition (a) SDA (b) A
SCL
8
9
1
2
3
4
5
6
7
8
9
TRS
Data transmission
Address reception
TRS bit setting is suspended in this period ICDR dummy read TRS bit setting The rise of the 9th clock is detected
The rise of the 9th clock is detected
Figure 18.34 TRS Bit Set Timing in Slave Mode Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to B'11 in ICXR. 13. Note on ICDR read in transmit mode and ICDR write in receive mode When ICDR is read in transmit mode (TRS = 1) or ICDR is written to in receive mode (TRS = 0), the SCL pin may not be held low in some cases after transmit/receive operation has been completed, thus inconveniently allowing clock pulses to be output on the SCL bus line before ICDR is accessed correctly. To access ICDR correctly, read the ICDR after setting receive mode or write to the ICDR after setting transmit mode.
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Section 18 I2C Bus Interface (IIC)
14. Note on ACKE and TRS bits in slave mode In the I C bus interface, if 1 is received as the acknowledge bit value (ACKB = 1) in transmit mode (TRS = 1) and then the address is received in slave mode without performing appropriate processing, interrupt handling may start at the rising edge of the 9th clock pulse even when the address does not match. Similarly, if the start condition and address are transmitted from the master device in slave transmit mode (TRS = 1), the ICDRE flag is set, and 1 is received as the acknowledge bit value (ACKB = 1), the IRIC flag may be set thus causing an interrupt source even when the address does not match. To use the I C bus interface module in slave mode, be sure to follow the procedures below. When having received 1 as the acknowledge bit value for the last transmit data at the end of a series of transmit operation, clear the ACKE bit in ICCR once to initialize the ACKB bit to 0. Set receive mode (TRS = 0) before the next start condition is input in slave mode. Complete transmit operation by the procedure shown in figure 18.23, in order to switch from slave transmit mode to slave receive mode. 15. Notes on Arbitration Lost in Master Mode Operation The I C bus interface recognizes the data in transmit/receive frame as an address when arbitration is lost in master mode and a transition to slave receive mode is automatically carried out. When arbitration is lost not in the first frame but in the second frame or subsequent frame, transmit/receive data that is not an address is compared with the value set in the SAR or SARX register as an address. If the receive data matches with the address in the SAR or SARX 2 register, the I C bus interface erroneously recognizes that the address call has occurred. (See figure 18.35.) In multi-master mode, a bus conflict could happen. When the I C bus interface is operated in master mode, check the state of the AL bit in the ICSR register every time after one frame of data has been transmitted or received. When arbitration is lost during transmitting the second frame or subsequent frame, take avoidance measures.
2 2 2 2
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Section 18 I2C Bus Interface (IIC)
* Arbitration is lost * The AL flag in ICSR is set to 1
I2C bus interface (Master transmit mode)
S
SLA
R/W
A
DATA1
Transmit data does not match
Transmit data match Transmit timing match
Other device (Master transmit mode)
S
SLA
R/W
A
DATA2
A
DATA3
A
Data contention I2C bus interface (Slave receive mode) S SLA R/W A SLA R/W A DATA4 A
* Receive address is ignored
* Automatically transferred to slave receive mode * Receive data is recognized as an address * When the receive data matches to the address set in the SAR or SARX register, the I2C bus interface operates as a slave device.
Figure 18.35 Diagram of Erroneous Operation when Arbitration Lost Though it is prohibited in the normal I C protocol, the same problem may occur when the MST bit is erroneously set to 1 and a transition to master mode is occurred during data transmission or reception in slave mode. When the MST bit is set to 1 during data transmission or reception in slave mode, the arbitration decision circuit is enabled and arbitration is lost if conditions are satisfied. In this case, the transmit/receive data which is not an address may be erroneously recognized as an address. In multi-master mode, pay attention to the setting of the MST bit when a bus conflict may occur. In this case, the MST bit in the ICCR register should be set to 1 according to the order below. A. Make sure that the BBSY flag in the ICCR register is 0 and the bus is free before setting the MST bit. B. Set the MST bit to 1. C. To confirm that the bus was not entered to the busy state while the MST bit is being set, check that the BBSY flag in the ICCR register is 0 immediately after the MST bit has been set. Note: Above restrictions can be released by setting the bits FNC1 and FNC2 in ICXR to B'11.
2
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Section 19 LPC Interface (LPC)
Section 19 LPC Interface (LPC)
This LSI has an on-chip LPC interface. The LPC includes three register sets, each of which comprises data and status registers, control register, the fast Gate A20 logic circuit, and the host interrupt request circuit. The LPC performs serial transfer of cycle type, address, and data, synchronized with the 33 MHz PCI clock. It uses four signal lines for address/data and one for host interrupt requests. This LPC module supports I/O read and I/O write cycle transfers. It is also provided with power-down functions that can control the PCI clock and shut down the LPC interface.
19.1
Features
* Supports LPC interface I/O read and I/O write cycles Uses four signal lines (LAD3 to LAD0) to transfer the cycle type, address, and data. Uses three control signals: clock (LCLK), reset (LRESET), and frame (LFRAME). * Three register sets comprising data and status registers The basic register set comprises three bytes: an input register (IDR), output register (ODR), and status register (STR). I/O addresses from H'0000 to H'FFFF are selected for channels 1 to 3. A fast Gate A20 function is provided for channel 1. For channel 3, sixteen bidirectional data register bytes can be manipulated in addition to the basic register set. * Supports SCIF The LPC interface is connected to the SCIF, allowing direct control of the SCIF by the LPC host.
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Section 19 LPC Interface (LPC)
* Supports SERIRQ Host interrupt requests are transferred serially on a single signal line (SERIRQ). On channel 1, HIRQ1 and HIRQ12 can be generated. On channels 2 and 3, SMI, HIRQ6, and HIRQ9 to HIRQ11 can be generated. In the SCIF, SMI, and HIRQ1 to HIRQ15 can be generated. Operation can be switched between quiet mode and continuous mode. The CLKRUN signal can be manipulated to restart the PCI clock (LCLK). * Power-down modes and interrupts The LPC module can be shut down by inputting the LPCPD signal. Three pins, PME, LSMI, and LSCI, are provided for general input/output. * Supports version 1.5 of the Intelligent Platform Management Interface (IPMI) specifications Channel 3 supports the SMIC interface, KCS interface, and BT interface.
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Section 19 LPC Interface (LPC)
Figure 19.1 shows a block diagram of the LPC.
Module data bus BTDTR FIFO (IN)
TWR0MW IDR3 IDR2 IDR1
Parallel serial conversion
SERIRQ
TWR1 to TWR15
SIRQCR0 to 5 Cycle detection HISEL
CLKRUN
Serial parallel conversion
Control logic
LPCPD LFRAME
Address match
LRESET
LAD0 to LAD3
LADR12 LADR1 LADR2 LADR3
LSCIE LSCIB LSCI input LSMIE LSMIB LSMI input PMEE PMEB PME input
LCLK
LSCI
LSMI
Serial parallel conversion
PME
SYNC output
ODR3
BTDTR FIFO (OUT)
TWR0SW
ODR2 ODR1 STR3 STR2 STR1
HICR0 to HICR5 GA20
TWR1 to TWR15
Internal interrupt control [Legend] HICR0 to HICR5: LADR12H, LADR12L: LADR3H, LADR3L: IDR1 to IDR3: ODR1 to ODR3: STR1 to STR3:
OBEI IBFI1 IBFI2 IBFI3 ERRI
Host interface control registers 0 to 5 LPC channel 1, 2 address registers 12H and 12L LPC channel 3 address registers 3H and 3L Input data registers 1 to 3 Output data registers 1 to 3 Status registers 1 to 3
TWR0MW: TWR0SW: TWR1 to TWR15: SIRQCR0 to SIRQCR5: HISEL:
Bidirectional data register 0MW Bidirectional data register 0SW Bidirectional data registers 1 to 15 SERIRQ control registers 0 to 5 Host interface select register
Figure 19.1 Block Diagram of LPC
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Section 19 LPC Interface (LPC)
19.2
Input/Output Pins
Table 19.1 lists the LPC pin configuration. Table 19.1 Pin Configuration
Name LPC address/ data 3 to 0 LPC frame LPC reset LPC clock Serialized interrupt request LSCI general output LSMI general output PME general output GATE A20 LPC clock run LPC power-down Abbreviation Port I/O Function Cycle type/address/data signals serially (4-signal-line) transferred in synchronization with LCLK
1
LAD3 to LAD0 PE to PE0 I/O
LFRAME LRESET LCLK SERIRQ
PE4 PE5 PE6 PE7
Input* Input* Input I/O*
1
Transfer cycle start and forced termination signal LPC interface reset signal 33-MHz PCI clock signal Serialized host interrupt request signal (SMI, HIRQ1 to HIRQ15) in synchronization with LCLK
1, 2
1
LSCI LSMI PME GA20 CLKRUN LPCPD
PD0 PD1 PD2 PD3 PD4 PD5
Output* * Output* * Output* * Output* * I/O* * Input*
1, 2 1, 1, 1,
General output General output General output Gate A20 control signal output LCLK restart request signal when serial host interrupt is requested LPC module shutdown signal
2
2
2
1
Notes: 1. Pin state monitoring input is possible in addition to the LPC interface control input/output function. 2. Only 0 can be output. If 1 is output, the pin is in the high-impedance state, so an external resistor is necessary to pull the signal up to VCC.
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Section 19 LPC Interface (LPC)
19.3
Register Descriptions
The LPC has the following registers. * Host interface control register 0 (HICR0) * Host interface control register 1 (HICR1) * Host interface control register 2 (HICR2) * Host interface control register 3 (HICR3) * Host interface control register 4 (HICR4) * Host interface control register 5 (HICR5) * Pin function control register (PINFNCR) * LPC channel 1, 2 address register H, L (LADR12H, LADR12L) * LPC channel 3 address register H, L (LADR3H, LADR3L) * Input data register 1 (IDR1) * Input data register 2 (IDR2) * Input data register 3 (IDR3) * Output data register 1 (ODR1) * Output data register 2 (ODR2) * Output data register 3 (ODR3) * Status register 1 (STR1) * Status register 2 (STR2) * Status register 3 (STR3) * Bidirectional data registers 0 to 15 (TWR0 to TWR15) * SERIRQ control register 0 (SIRQCR0) * SERIRQ control register 1 (SIRQCR1) * SERIRQ control register 2 (SIRQCR2) * SERIRQ control register 3 (SIRQCR3) * SERIRQ control register 4 (SIRQCR4) * SERIRQ control register 5 (SIRQCR5) * Host interface select register (HISEL) * SCIF address register H, L (SCIFADRH, SCIFADRL)
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Section 19 LPC Interface (LPC)
The following registers are necessary for SMIC mode * SMIC flag register (SMICFLG) * SMIC control/status register (SMICCSR) * SMIC data register (SMICDTR) * SMIC interrupt register 0 (SMICIR0) * SMIC interrupt register 1 (SMICIR1) The following registers are necessary for BT mode * BT status register 0 (BTSR0) * BT status register 1 (BTSR1) * BT control/status register 0 (BTCSR0) * BT control/status register 1 (BTCSR1) * BT control register (BTCR) * BT data buffer (BTDTR) * BT interrupt mask register (BTIMSR) * FIFO valid size register 0 (BTFVSR0) * FIFO valid size register 1 (BTFVSR1)
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Section 19 LPC Interface (LPC)
19.3.1
Host Interface Control Registers 0 and 1 (HICR0 and HICR1)
HICR0 and HICR1 contain control bits that enable or disable LPC interface functions, control bits that determine pin output and the internal state of the LPC interface, and status flags that monitor the internal state of the LPC interface. * HICR0
Initial Value 0 0 0 R/W Slave Host Description R/W R/W R/W LPC Enable 3 to 1 Enable or disable the LPC interface function. When the LPC interface is enabled (one of the three bits is set to 1), processing for data transfer between the slave (this LSI) and the host is performed using pins LAD3 to LAD0, LFRAME, LRESET, LCLK, SERIRQ, CLKRUN, and LPCPD. * LPC3E 0: LPC channel 3 operation is disabled No address (LADR3) matches for IDR3, ODR3, STR3, TWR0 to TWR15, SMIC, KCS, or BT 1: LPC channel 3 operation is enabled * LPC2E 0: LPC channel 2 operation is disabled No address (LADR2) matches for IDR2, ODR2, or STR2 1: LPC channel 2 operation is enabled * LPC1E 0: LPC channel 1 operation is disabled No address (LADR1) matches for IDR1, ODR1, or STR1 1: LPC channel 1 operation is enabled
Bit 7 6 5
Bit Name LPC3E LPC2E LPC1E
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Section 19 LPC Interface (LPC)
Bit 4
Bit Name FGA20E
Initial Value 0
R/W Slave Host Description R/W Fast Gate A20 Function Enable Enables or disables the fast Gate A20 function. The PD3DDR bit should be cleared to 0 when the LPC is used. With the fast Gate A20 disabled, the normal Gate A20 can be implemented by firmware controlling PD3 output. 0: Fast Gate A20 function disabled General I/O function of pin PD3 is enabled The internal state of GA20 output is initialized to 1 1: Fast Gate A20 function enabled GA20 pin output is open-drain (external pull-up resistor (Vcc) required)
3
SDWNE
0
R/W
LPC Software Shutdown Enable Controls LPC interface shutdown. For details of the LPC shutdown function, and the scope of initialization by an LPC reset and an LPC shutdown, see section 19.4.6, LPC Interface Shutdown Function (LPCPD). 0: Normal state, LPC software shutdown setting enabled [Clearing conditions] * * * Writing 0 LPC hardware reset or LPC software reset LPC hardware shutdown release (rising edge of LPCPD signal)
1: LPC hardware shutdown state setting enabled Hardware shutdown state when LPCPD signal is low level [Setting condition] Writing 1 after reading SDWNE = 0
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Section 19 LPC Interface (LPC)
Bit 2
Bit Name PMEE
Initial Value 0
R/W Slave Host Description R/W PME Output Enable Controls PME output in combination with the PMEB bit in HICR1. PME pin output is open-drain, and an external pull-up resistor (Vcc) is needed. The PD2DDR bit should be cleared to 0 when the LPC is used. PMEE 0 1 1 PMEB X 0 1 : PME output disabled; general I/O function of pin PD2 is enabled : PME output enabled, PME pin output goes to 0 level : PME output enabled, PME pin output is high-impedance
1
LSMIE
0
R/W
LSMI output Enable Controls LSMI output in combination with the LSMIB bit in HICR1. LSMI pin output is open-drain, and an external pull-up resistor (Vcc) is needed. The PD1DDR bit should be cleared to 0 when the LPC is used. LSMIE 0 1 1 LSMIB X 0 1 : LSMI output disabled; general I/O function of pin PD1 is enabled : LSMI output enabled, LSMI pin output goes to 0 level : LSMI output enabled, LSMI pin output is Hi-Z
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Section 19 LPC Interface (LPC)
Bit 0
Bit Name LSCIE
Initial Value 0
R/W Slave Host Description R/W LSCI output Enable Controls LSCI output in combination with the LSCIB bit in HICR1. LSCI pin output is open-drain, and an external pull-up resistor (Vcc) is needed. The PD0DDR bit should be cleared to 0 when the LPC is used. LSCIE 0 1 1 LSCIB X 0 1 : LSCI output disabled; general I/O function of pin PD0 is enabled : LSCI output enabled, LSCI pin output goes to 0 level : LSCI output enabled, LSCI pin output is high-impedance
[Legend] X: Don't care
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Section 19 LPC Interface (LPC)
* HICR1
Initial Value 0 R/W Slave Host Description R LPC Busy Indicates that the LPC interface is processing a transfer cycle. 0: LPC interface is in transfer cycle wait state * * Bus idle, or transfer cycle not subject to processing is in progress Cycle type or address indeterminate during transfer cycle LPC hardware reset or LPC software reset LPC hardware shutdown or LPC software shutdown Forced termination (abort) of transfer cycle subject to processing Normal termination of transfer cycle subject to processing
Bit 7
Bit Name LPCBSY
[Clearing conditions] * * * *
1: LPC interface is performing transfer cycle processing [Setting condition] Match of cycle type and address
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Section 19 LPC Interface (LPC)
Bit 6
Bit Name CLKREQ
Initial Value 0
R/W Slave Host Description R LCLK Request Indicates that the LPC interface's SERIRQ output is requesting a restart of LCLK. 0: No LCLK restart request [Clearing conditions] * * * * LPC hardware reset or LPC software reset LPC hardware shutdown or LPC software shutdown SERIRQ is set to continuous mode There are no further interrupts for transfer to the host in quiet mode
1: LCLK restart request issued [Setting condition] In quiet mode, SERIRQ interrupt output becomes necessary while LCLK is stopped 5 IRQBSY 0 R SERIRQ Busy Indicates that the LPC interface's SERIRQ is engaged in transfer processing. 0: SERIRQ transfer frame wait state [Clearing conditions] * * * LPC hardware reset or LPC software reset LPC hardware shutdown or LPC software shutdown End of SERIRQ transfer frame
1: SERIRQ transfer processing in progress [Setting condition] Start of SERIRQ transfer frame
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Section 19 LPC Interface (LPC)
Bit 4
Bit Name LRSTB
Initial Value 0
R/W Slave Host Description R/W LPC Software Reset Bit Resets the LPC interface. For the scope of initialization by an LPC reset, see section 19.4.6, LPC Interface Shutdown Function (LPCPD). 0: Normal state [Clearing conditions] * * Writing 0 LPC hardware reset
1: LPC software reset state [Setting condition] Writing 1 after reading LRSTB = 0 3 SDWNB 0 R/W LPC Software Shutdown Bit Controls LPC interface shutdown. For details of the LPC shutdown function, and the scope of initialization by an LPC reset and an LPC shutdown, see section 19.4.6, LPC Interface Shutdown Function (LPCPD). 0: Normal state [Clearing conditions] * * * * Writing 0 LPC hardware reset or LPC software reset LPC hardware shutdown (falling edge of LPCPD signal when SDWNE = 1) LPC hardware shutdown release (rising edge of LPCPD signal when SDWNE = 0) 1: LPC software shutdown state [Setting condition] Writing 1 after reading SDWNB = 0 2 PMEB 0 R/W PME Output Bit Controls PME output in combination with the PMEE bit. For details, refer to description on the PMEE bit in HICR0.
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Section 19 LPC Interface (LPC)
Bit 1
Bit Name LSMIB
Initial Value 0
R/W Slave Host Description R/W LSMI Output Bit Controls LSMI output in combination with the LSMIE bit. For details, refer to description on the LSMIE bit in HICR0.
0
LSCIB
0
R/W
LSCI output Bit Controls LSCI output in combination with the LSCIE bit. For details, refer to description on the LSCIE bit in HICR0.
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Section 19 LPC Interface (LPC)
19.3.2
Host Interface Control Registers 2 and 3 (HICR2 and HICR3)
HICR2 controls interrupts to an LPC interface slave (this LSI). HICR3 monitors the states of the LPC interface pins. Bits 6 to 0 in HICR2 are initialized to H'00 by a reset. The states of other bits are decided by the pin states. The pin states can be monitored by the pin monitoring bits regardless of the LPC interface operating state or the operating state of the functions that use pin multiplexing. * HICR2
Initial Value 0 R/W Slave Host Description GA20 Pin Monitor LPC Reset Interrupt Flag This bit is a flag that generates an ERRI interrupt when an LPC hardware reset occurs. 0: [Clearing condition] Writing 0 after reading LRST = 1 1: [Setting condition] LRESET pin falling edge detection 5 SDWN 0 R/(W)* LPC Shutdown Interrupt Flag This bit is a flag that generates an ERRI interrupt when an LPC hardware shutdown request is generated. 0: [Clearing conditions] * * * Writing 0 after reading SDWN = 1 LPC hardware reset (LRESET pin falling edge detection) LPC software reset (LRSTB = 1) 1: [Setting condition] LPCPD pin falling edge detection R/(W)*
Bit 7 6
Bit Name GA20 LRST
Undefined R
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Section 19 LPC Interface (LPC)
Bit 4
Bit Name ABRT
Initial Value 0
R/W Slave Host Description LPC Abort Interrupt Flag This bit is a flag that generates an ERRI interrupt when a forced termination (abort) of an LPC transfer cycle occurs. 0: [Clearing conditions] * * * * Writing 0 after reading ABRT = 1 LPC hardware reset (LRESET pin falling edge detection) LPC software reset (LRSTB = 1) LPC hardware shutdown (SDWNE = 1 and LPCPD pin falling edge detection) * LPC software shutdown (SDWNB = 1) 1: [Setting condition] LFRAME pin falling edge detection during LPC transfer cycle R/(W)*
3
IBFIE3
0
R/W
IDR3 and TWR Receive Complete interrupt Enable Enables or disables IBFI3 interrupt to the slave (this LSI). 0: Input data register (IDR3) and TWR receive complete interrupt requests and SMIC/BT mode interrupt requests disabled 1: [When TWRIE = 0 in LADR3] Input data register (IDR3) receive complete interrupt requests and SMIC/BT mode interrupt requests enabled [When TWRIE = 1 in LADR3] Input data register (IDR3) and TWR receive complete interrupt requests and SMIC/BT mode interrupt requests enabled
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Section 19 LPC Interface (LPC)
Bit 2
Bit Name IBFIE2
Initial Value 0
R/W Slave Host Description R/W IDR2 Receive Complete interrupt Enable Enables or disables IBFI2 interrupt to the slave (this LSI). 0: Input data register (IDR2) receive complete interrupt requests disabled 1: Input data register (IDR2) receive complete interrupt requests enabled
1
IBFIE1
0
R/W
IDR1 Receive Complete interrupt Enable Enables or disables IBFI1 interrupt to the slave (this LSI). 0: Input data register (IDR1) receive complete interrupt requests disabled 1: Input data register (IDR1) receive complete interrupt requests enabled
0
ERRIE
0
R/W
Error Interrupt Enable Enables or disables ERRI interrupt to the slave (this LSI). 0: Error interrupt requests disabled 1: Error interrupt requests enabled
Note:
*
Only 0 can be written to bits 6 to 4, to clear the flag.
* HICR3
R/W Bit 7 6 5 4 3 2 1 0 Bit Name Initial Value Slave Host Description LFRAME Undefined CLKRUN Undefined SERIRQ LRESET LPCPD PME LSMI LSCI Undefined Undefined Undefined Undefined Undefined Undefined R R R R R R R R LFRAME Pin Monitor CLKRUN Pin Monitor SERIRQ Pin Monitor LRESET Pin Monitor LPCPD Pin Monitor PME Pin Monitor LSMI Pin Monitor LSCI Pin Monitor
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Section 19 LPC Interface (LPC)
19.3.3
Host Interface Control Register 4 (HICR4)
HICR4 controls the operation of the KCS, SMIC, and BT interface functions on channel 3.
Initial Value R/W Slave Host Description R/W Switches the channel accessed via LADR12H and LADR12L. 0: LADR1 is selected 1: LADR2 is selected 6 to 4 3 SWENBL All 0 0 R/W R/W Reserved The initial value should not be changed. In BT mode, H'5 (short wait) or H'6 (long wait) is returned to the host in the synchronized return cycle from slave, thus can make the host wait. 0: Short wait is issued 1: Long wait is issued 2 KCSENBL 0 R/W Enables or disables the use of the KCS interface included in channel 3. When the LPC3E bit in HICR0 is 0, this bit is valid. 0: KCS interface operation is disabled No address (LADR3) matches for IDR3, ODR3, or STR3 in KCS mode 1: KCS interface operation is enabled
Bit 7
Bit Name
LADR12SEL 0
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Section 19 LPC Interface (LPC)
R/W Bit 1 Bit Name SMICENBL Initial Value Slave Host Description 0 R/W Enables or disables the use of the SMIC interface included in channel 3. When the LPC3E bit in HICR0 is 0, this bit is valid. 0: SMIC interface operation is disabled No address (LADR3) matches for SMICFLG, SSMICCSR, or SMICDTR 1: SMIC interface operation is enabled 0 BTENBL 0 R/W Enables or disables the use of the BT interface included in channel 3. When the LPC3E bit in HICR0 is 0, this bit is valid. 0: BT interface operation is disabled No address (LADR3) matches for BTIMSR, BTCR, or BTDTR 1: BT interface operation is enabled
19.3.4
Host Interface Control Register 5 (HICR5)
HICR5 enables or disables the operation of the SCIF interface, and controls OBEI interrupts.
Initial Value All 0 0 R/W Slave Host Description R/W R/W Reserved The initial value bit should not be changed. SCIF Enable Enables or disables access from the LPC host of the SCIF. 0: Disables access to the SCIF from the LPC host 1: Enables access to the SCIF from the LPC host Reserved The initial value should not be changed.
Bit
Bit Name
7 to 2 1 SCIFE
0
0
R/W
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Section 19 LPC Interface (LPC)
19.3.5
Pin Function Control Register (PINFNCR)
PINFNCR selects whether the pins of the associated port are used for the LPC function or general I/O.
Initial Value All 0 0 0 R/W Slave Host Description R/W R/W R/W R/W Reserved The initial value bit should not be changed. 0: SERIRQ pin 1: General I/O port 0: LPCPD pin 1: General I/O port 0: CLKRUN pin 1: General I/O port
Bit
Bit Name
7 to 3 2 1 0
SERIRQOFF LPCPDOFF
CLKRUNOFF 0
19.3.6
LPC Channel 1, 2 Address Register H, L (LADR12H, LADR12L)
LADR12H and LADR12L are temporary registers for accessing internal registers LADR1H, LADR1L, LADR2H, and LADR2L. When the LADR12SEL bit in HICR4 is 0, LPC channel 1 host addresses (LADR1H, LADR1L) are set through LADR12. The contents of the address field in LADR1 must not be changed while channel 1 is operating (while LPC1E is set to 1). When the LADR12SEL bit is 1, LPC channel 2 host addresses (LADR2H, LADR2L) are set through LADR12. The contents of the address field in LADR2 must not be changed while channel 2 is operating (while LPC2E is set to 1). Table 19.2 shows the initial value of each register. Table 19.3 shows the host register selection in address match determination. Table 19.4 shows the slave selection internal registers in slave (this LSI) access. Table 19.2 LADR1, LADR2 Initial Values
Register Name LADR1 LADR2 Initial Value H'0060 H'0062 Description I/O address of channel 1 I/O address of channel 2
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Section 19 LPC Interface (LPC)
Table 19.3 Host Register Selection
I/O Address Bits 15 to 3 Bit 2 Bit 1 LADR1 (bit 1) LADR1 (bit 1) LADR1 (bit 1) LADR1 (bit 1) LADR2 (bit 1) LADR2 (bit 1) LADR2 (bit 1) LADR2 (bit 1) Bit 0 Transfer Cycle
Host Register Selection IDR1 write (data), C/D1 0 IDR1 write (command), C/D1 1 ORD1 read STR1 read IDR2 write (data), C/D2 0 IDR2 write (command), C/D2 1 ODR2 read STR2 read
LADR1 (bits 15 to 3) 0 LADR1 (bits 15 to 3) 1 LADR1 (bits 15 to 3) 0 LADR1 (bits 15 to 3) 1 LADR2 (bits 15 to 3) 0 LADR2 (bits 15 to 3) 1 LADR2 (bits 15 to 3) 0 LADR2 (bits 15 to 3) 1
LADR1 (bit 0) I/O write LADR1 (bit 0) I/O write LADR1 (bit 0) I/O read LADR1 (bit 0) I/O read LADR2 (bit 0) I/O write LADR2 (bit 0) I/O write LADR2 (bit 0) I/O read LADR2 (bit 0) I/O read
Table 19.4 Slave Selection Internal Registers
Slave (R/W) Bus Width (B/W) LADR12SEL R/W R/W R/W R/W R/W R/W B B B B W W 0 1 0 1 0 1 LADR12H LADR12H LADR12 LADR12H LADR12H LADR12L LADR12L LADR12L LADR12L LADR1H LADR2H Internal Register LADR1H LADR2H LADR1L LADR2L LADR1L LADR2L
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Section 19 LPC Interface (LPC)
19.3.7
LPC Channel 3 Address Register H, L (LADR3H, LADR3L)
LADR3 comprises two 8-bit readable/writable registers that perform LPC channel 3 host address setting and control the operation of the bidirectional data registers. The contents of the address field in LADR3 must not be changed while channel 3 is operating (while LPC3E is set to 1). * LADR3H
R/W Bit 7 6 5 4 3 2 1 0 Bit Name Initial Value Slave Host Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 All 0 R/W Description Channel 3 Address Bits 15 to 8 The host address of LPC channel 3 is set.
* LADR3L
Bit 7 6 5 4 3 2 1 0 Bit Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 1 TWRE 0 0 0 R/W R/W R/W Reserved The initial value should not be changed. Channel 3 Address Bit 1 The host address of LPC channel 3 is set. Bidirectional data Register Enable Enables or disables bidirectional data register operation. Clear this bit to 0 in KCS mode. 0: TWR operation is disabled TWR-related address (LADR3) match does not occur. 1: TWR operation is enabled Initial Value All 0 R/W Slave Host R/W Description Channel 3 Address Bits 7 to 3 The host address of LPC channel 3 is set.
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Section 19 LPC Interface (LPC)
When LPC3E = 1, an I/O address received in an LPC I/O cycle is compared with the contents of LADR3. When determining an IDR3, ODR3, or STR3 address match, bit 0 in LADR3 is regarded as 0, and the value of bit 2 is ignored. When determining a TWR0 to TWR15 address match, bit 4 of LADR3 is inverted, and the values of bits 3 to 0 are ignored. When determining an IDR3, ODR3, or STR3 address match in KCS mode, an SMICFLG, SMICCSR, SMICDTR address match in SMIC mode, and a BTDTR, BTCR, BTIMSR address match in BT mode, the values of bits 3 to 0 are ignored. Register selection according to the bits ignored in address match determination is as shown in the following table.
I/O Address Bits 15 to5 Bits 15 to5 Bits 15 to5 Bits 15 to5 Bits 15 to5 Bits 15 to5 Bits 15 to5 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 0 0 * * * 1 Bits 15 to5 Bits 15 to5 Bit 4 Bit 4 0 0 * * * 1 Bit 2 0 1 0 1 0 0 * * * 1 0 0 * * * 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 0 0 * * * 1 0 0 * * * 1 Bit 0 0 0 0 0 0 1 * * * 1 0 1 * * * 1 I/O read I/O read TWR0SW read TWR1 to TWR15 read Transfer Cycle I/O write I/O write I/O read I/O read I/O write I/O write Host Register Selection IDR3 write, C/D3 0 IDR3 write, C/D3 1 ODR3 read STR3 read TWR0MW write TWR1 to TWR15 write
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Section 19 LPC Interface (LPC)
* KCS mode
I/O Address Bits 15 to5 Bits 15 to5 Bits 15 to5 Bits 15 to5 Bits 15 to5 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 3 0 0 0 0 Bit 2 0 0 0 0 Bit 1 1 1 1 1 Bit 0 0 1 0 1 Transfer Cycle I/O write I/O write I/O read I/O read Host Register Selection IDR3 write, C/D3 0 IDR3 write, C/D3 1 ODR3 read STR3 read
* BT mode
I/O Address Bits 15 to5 Bits 15 to5 Bits 15 to5 Bits 15 to5 Bits 15 to5 Bits 15 to5 Bits 15 to5 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 3 0 0 0 0 0 0 Bit 2 1 1 1 1 1 1 Bit 1 0 0 1 0 0 1 Bit 0 0 1 0 0 1 0 Transfer Cycle I/O write I/O write I/O write I/O read I/O read I/O read Host Register Selection BTCR write BTDTR write BTIMSR write BTCR read BTDTR read BTIMSR read
* SMIC mode
I/O Address Bits 15 to5 Bits 15 to5 Bits 15 to5 Bits 15 to5 Bits 15 to5 Bits 15 to5 Bits 15 to5 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 3 1 1 1 1 1 1 Bit 2 0 0 0 0 0 0 Bit 1 0 1 1 0 1 1 Bit 0 1 0 1 1 0 1 Transfer Cycle I/O write I/O write I/O write I/O read I/O read I/O read Host Register Selection SMICDTR write SMICCSR write SMICFLG write SMICDTR read SMICCSR read SMICFLG read
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Section 19 LPC Interface (LPC)
19.3.8
Input Data Registers 1 to 3 (IDR1 to IDR3)
The IDR registers are 8-bit read-only registers to the slave processor (this LSI), and 8-bit writeonly registers to the host processor. The registers selected from the host according to the I/O address are described in the following sections: for information on IDR1 and IDR2 selection, see section 19.3.6, LPC Channel 1, 2 Address Register H, L (LADR12H, LADR12L), and for information on IDR3 selection, see section 19.3.7, LPC Channel 3 Address Register H, L (LADR3H, LADR3L). Data transferred in an LPC I/O write cycle is written to the selected register. The state of bit 2 of the I/O address is latched into the C/D bit in STR, to indicate whether the written information is a command or data. The initial values of the IDR registers are undefined. 19.3.9 Output Data Registers 0 to 3 (ODR1 to ODR3)
The ODR registers are 8-bit readable/writable registers to the slave processor (this LSI), and 8-bit read-only registers to the host processor. The registers selected from the host according to the I/O address are described in the following sections: for information on ODR1 and ODR2 selection, see section 19.3.6, LPC Channel 1, 2 Address Register H, L (LADR12H, LADR12L), and for information on ODR3 selection, see section 19.3.7, LPC Channel 3 Address Register H, L (LADR3H, LADR3L). In an LPC I/O read cycle, the data in the selected register is transferred to the host. The initial values of the ODR registers are undefined.
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Section 19 LPC Interface (LPC)
19.3.10 Bidirectional Data Registers 0 to 15 (TWR0 to TWR15) TWR0 to TWR15 are sixteen 8-bit readable/writable registers to both the slave processor (this LSI) and the host processor. In TWR0, however, two registers (TWR0MW and TWR0SW) are allocated to the same address for both the host address and the slave address. TWR0MW is a write-only register to the host processor, and a read-only register to the slave processor, while TWR0SW is a write-only register to the slave processor and a read-only register to the host processor. When the host and slave processors begin a write, after the respective TWR0 registers have been written to, access right arbitration for simultaneous access is performed by checking the status flags to see if those writes were valid. For the registers selected from the host according to the I/O address, see section 19.3.7, LPC Channel 3 Address Register H, L (LADR3H, LADR3L). Data transferred in an LPC I/O write cycle is written to the selected register; in an LPC I/O read cycle, the data in the selected register is transferred to the host. The initial values of TWR0 to TWR15 are undefined.
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Section 19 LPC Interface (LPC)
19.3.11 Status Registers 1 to 3 (STR1 to STR3) The STR registers are 8-bit registers that indicate status information during LPC interface processing. Bits 3, 1, and 0 in STR1 to STR3 are read-only bits to both the host processor and the slave processor (this LSI). However, 0 only can be written from the slave processor (this LSI) to bit 0 in STR1 to STR3, and bits 6 and 4 in STR3, in order to clear the flags to 0. The functions for bits 7 to 4 in STR3 differ according to the settings of bit SELSTR3 in HISEL and the TWRE bit in LADR3L. For details, see section 19.3.18, Host Interface Select Register (HISEL). The registers selected from the host processor according to the I/O address are described in the following sections. For information on STR1 and STR2 selection, see section 19.3.6, LPC Channel 1, 2 Address Register H, L (LADR12H, LADR12L), and information on STR3 selection, see section 19.3.7, LPC Channel 3 Address Register H, L (LADR3H, LADR3L). In an LPC I/O read cycle, the data in the selected register is transferred to the host processor. The STR registers are initialized to H'00 by a reset or in hardware standby mode. * STR1
R/W Bit 7 6 5 4 3 Bit Name Initial Value Slave Host Description DBU17 DBU16 DBU15 DBU14 C/D1 0 R R Command/Data When the host processor writes to an IDR1 register, bit 2 of the I/O address (when CH1OFFSEL1 = 0) or bit 0 of the I/O address (when CH1OFFSEL1 = 1) is written to this bit to indicate whether IDR1 contains data or a command. 0: Content of input data register (IDR1) is data 1: Content of input data register (IDR1) is a command 2 DBU12 0 R/W R Defined by User The user can use this bit as necessary. All 0 R/W R Defined by User The user can use these bits as necessary.
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Section 19 LPC Interface (LPC)
R/W Bit 1 Bit Name Initial Value Slave Host Description IBF1 0 R R Input Data Register Full Indicates whether or not there is receive data in IDR1. This bit is an internal interrupt source to the slave processor (this LSI). The IBF1 flag setting and clearing conditions are different when the fast A20 gate is used. For details see table 19.7. 0: There is not receive data in IDR1 [Clearing condition] When the slave processor reads IDR 1: There is receive data in IDR1 [Setting condition] When the host processor writes to IDR using I/O write cycle 0 OBF1 0 R/(W)* R Output Data Register Full Indicates whether or not there is transmit data in ODR1. 0: There is not transmit data in ODR1 [Clearing condition] When the host processor reads ODR1 using I/O read cycle, or the slave processor writes 0 to the OBF1 bit 1: There is transmit data in ODR1 [Setting condition] When the slave processor writes to ODR1 Note: * Only 0 can be written to clear the flag.
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Section 19 LPC Interface (LPC)
*
STR2
R/W
Bit 7 6 5 4 3
Bit Name Initial Value Slave Host Description DBU27 DBU26 DBU25 DBU24 C/D2 0 0 0 0 0 R/W R/W R/W R/W R R R R R R Command/Data When the host writes to IDR2, bit 2 of the I/O address (when CH2OFFSEL1 = 0) or bit 0 of the I/O address (when CH2OFFSEL1 = 1) is written to this bit to indicate whether IDR2 contains data or a command. 0: Content of input data register (IDR2) is a data 1: Content of input data register (IDR2) is a command Defined by User The user can use these bits as necessary.
2 1
DBU22 IBF2
0 0
R/W R
R R
Defined by User The user can use this bit as necessary. Input Data Register Full Indicates whether or not there is receive data in IDR2. This bit is an internal interrupt source to the slave (this LSI). 0: There is not receive data in IDR2 [Clearing condition] When the slave reads IDR2 1: There is receive data in IDR2 [Setting condition] When the host writes to IDR2 in an I/O write cycle
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Section 19 LPC Interface (LPC)
R/W Bit 0 Bit Name Initial Value Slave Host Description OBF2 0 R/(W)* R Output Data Register Full Indicates whether or not there is transmit data in ODR2. 0: There is not transmit data in ODR2 [Clearing conditions] * * When the host reads ODR2 in an I/O read cycle When the slave writes 0 to bit OBF2
1: There is transmit data in ODR2 [Setting condition] * Note: * Only 0 can be written to clear the flag. When the slave writes to ODR2
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Section 19 LPC Interface (LPC)
* STR3 (TWRE = 1 or SELSTR3 = 0)
R/W Bit 7 Bit Name Initial Value Slave Host Description IBF3B 0 R R Bidirectional Data Register Input Buffer Full Flag This is an internal interrupt source to the slave (this LSI). 0: [Clearing condition] When the slave reads TWR15 1: [Setting condition] When the host writes to TWR15 in I/O write cycle 6 OBF3B 0 R/(W)* R Bidirectional Data Register Output Buffer Full Flag 0: [Clearing conditions] * * When the host reads TWR15 in I/O read cycle When the slave writes 0 to the OBF3B bit
1: [Setting condition] When the slave writes to TWR15 5 MWMF 0 R R Master Write Mode Flag 0: [Clearing condition] When the slave reads TWR15 1: [Setting condition] When the host writes to TWR0 in I/O write cycle while SWMF = 0 4 SWMF 0 R/(W)* R Slave Write Mode Flag In the event of simultaneous writes by the master and the slave, the master write has priority. 0: [Clearing conditions] * * When the host reads TWR15 in I/O read cycle When the slave writes 0 to the SWMF bit
1: [Setting condition] When the slave writes to TWR0 while MWMF = 0
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Section 19 LPC Interface (LPC)
R/W Bit 3 Bit Name Initial Value Slave C/D3 0 R Host Description R Command/Data Flag When the host writes to IDR3, bit 2 of the I/O address is written into this bit to indicate whether IDR3 contains data or a command. 0: Content of input data register (IDR3) is a data 1: Content of input data register (IDR3) is a command 2 1 DBU32 IBF3A 0 0 R/W R R R Defined by User The user can use this bit as necessary. Input Data Register Full Indicates whether or not there is receive data in IDR3. This is an internal interrupt source to the slave (this LSI). 0: There is not receive data in IDR3 [Clearing condition] When the slave reads IDR3 1: There is receive data in IDR3 [Setting condition] When the host writes to IDR3 in an I/O write cycle 0 OBF3A 0 R/(W)* R Output Data Register Full Indicates whether or not there is transmit data in ODR3. 0: There is not transmit data in ODR3 [Clearing conditions] * * When the host reads ODR3 in an I/O read cycle When the slave writes 0 to bit OBF3A
1: There is transmit data in ODR3 [Setting condition] * Note: * Only 0 can be written to clear the flag. When the slave writes to ODR3
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Section 19 LPC Interface (LPC)
* STR3 (TWRE = 0 and SELSTR3 = 1)
R/W Bit 7 6 5 4 3 Bit Name Initial Value Slave Host Description DBU37 DBU36 DBU35 DBU34 C/D3 0 0 0 0 0 R/W R/W R/W R/W R R R R R R Command/Data Flag When the host writes to IDR3, bit 2 of the I/O address is written into this bit to indicate whether IDR3 contains data or a command. 0: Content of input data register (IDR3) is a data 1: Content of input data register (IDR3) is a command 2 1 DBU32 IBF3A 0 0 R/W R R R Defined by User The user can use this bit as necessary. Input Data Register Full Indicates whether or not there is receive data in IDR3. This bit is an internal interrupt source to the slave (this LSI). 0: There is not receive data in IDR3 [Clearing condition] When the slave reads IDR3 1: There is receive data in IDR3 [Setting condition] When the host writes to IDR3 in an I/O write cycle Defined by User The user can use these bits as necessary.
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Section 19 LPC Interface (LPC)
R/W Bit 0 Bit Name Initial Value Slave Host Description OBF3A 0 R/(W)* R Output Data Register Full Indicates whether or not there is transmit data in ODR3. 0: There is not receive data in ODR3 [Clearing conditions] * When the host reads ODR3 in an I/O read cycle * When the slave writes 0 to bit OBF3A 1: There is receive data in ODR3 [Setting condition] * When the slave writes to ODR3 Note: * Only 0 can be written to clear the flag.
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Section 19 LPC Interface (LPC)
19.3.12
SERIRQ Control Register 0 (SIRQCR0)
SIRQCR0 contains status bits that indicate the SERIRQ operating mode and bits that specify SERIRQ interrupt sources.
R/W Bit 7 Bit Name Initial Value Slave Host Description Q/C 0 R Quiet/Continuous Mode Flag Indicates the mode specified by the host at the end of an SERIRQ transfer cycle (stop frame). 0: Continuous mode [Clearing conditions] * * LPC hardware reset, LPC software reset Specification by SERIRQ transfer cycle stop frame
1: Quiet mode [Setting condition] Specification by SERIRQ transfer cycle stop frame. 6 SELREQ 0 R/W Start Frame Initiation Request Select Selects the condition of a start frame initiation request when a host interrupt request is cleared in quiet mode. 0: Start frame initiation is requested when all interrupt requests are cleared 1: Start frame initiation is requested when one or more interrupt requests are cleared 5 IEDIR2 0 R/W Interrupt Enable Direct Mode Specifies whether LPC channel 2 and channel 3 SERIRQ interrupt source (SMI, IRQ6, IRQ9 to IRQ11) generation is conditional upon OBF, or is controlled only by the host interrupt enable bit. 0: Host interrupt is requested when host interrupt enable and corresponding OBF bits are both set to 1 1: Host interrupt is requested when host interrupt enable bit is set to 1
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Section 19 LPC Interface (LPC)
R/W Bit 4 Bit Name Initial Value Slave Host Description SMIE3B 0 R/W Host SMI Interrupt Enable 3B Enables or disables an SMI interrupt request when OBF3B is set by a TWR15 write. 0: Host SMI interrupt request by OBF3B and SMIE3B is disabled [Clearing conditions] * * * Writing 0 to SMIE3B LPC hardware reset, LPC software reset Clearing OBF3B to 0 (when IEDIR3 = 0) Host SMI interrupt request by setting OBF3B to 1 is enabled [When IEDIR3 = 1] Host SMI interrupt is requested [Setting condition] Writing 1 after reading SMIE3B = 0 3 SMIE3A 0 R/W Host SMI Interrupt Enable 3A Enables or disables an SMI interrupt request when OBF3A is set by an ODR3 write. 0: Host SMI interrupt request by OBF3A and SMIE3A is disabled [Clearing conditions] * * * Writing 0 to SMIE3A LPC hardware reset, LPC software reset Clearing OBF3A to 0 (when IEDIR3 = 0) Host SMI interrupt request by setting is enabled [When IEDIR3 = 1] Host SMI interrupt is requested [Setting condition] Writing 1 after reading SMIE3A = 0
1: [When IEDIR3 = 0]
1: [When IEDIR3 = 0]
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Section 19 LPC Interface (LPC)
R/W Bit 2 Bit Name Initial Value Slave Host Description SMIE2 0 R/W Host SMI Interrupt Enable 2 Enables or disables an SMI interrupt request when OBF2 is set by an ODR2 write. 0: Host SMI interrupt request by OBF2 and SMIE2 is disabled [Clearing conditions] * * * Writing 0 to SMIE2 LPC hardware reset, LPC software reset Clearing OBF2 to 0 (when IEDIR2 = 0) Host SMI interrupt request by setting OBF2 to 1 is enabled [When IEDIR2 = 1] Host SMI interrupt is requested [Setting condition] Writing 1 after reading SMIE2 = 0 1 IRQ12E1 0 R/W Host IRQ12 Interrupt Enable 1 Enables or disables an HIRQ12 interrupt request when OBF1 is set by an ODR1 write. 0: HIRQ12 interrupt request by OBF1 and IRQ12E1 is disabled [Clearing conditions] * * * Writing 0 to IRQ12E1 LPC hardware reset, LPC software reset Clearing OBF1 to 0
1: [When IEDIR2 = 0]
1: HIRQ12 interrupt request by setting OBF1 to 1 is enabled [Setting condition] Writing 1 after reading IRQ12E1 = 0
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Section 19 LPC Interface (LPC)
R/W Bit 0 Bit Name Initial Value Slave Host Description IRQ1E1 0 R/W Host IRQ1 Interrupt Enable 1 Enables or disables a host HIRQ1 interrupt request when OBF1 is set by an ODR1 write. 0: HIRQ1 interrupt request by OBF1 and IRQ1E1 is disabled [Clearing conditions] * * * Writing 0 to IRQ1E1 LPC hardware reset, LPC software reset Clearing OBF1 to 0
1: HIRQ1 interrupt request by setting OBF1 to 1 is enabled [Setting condition] Writing 1 after reading IRQ1E1 = 0
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Section 19 LPC Interface (LPC)
19.3.13 SERIRQ Control Register 1 (SIRQCR1) SIRQCR1 contains status bits that indicate the SERIRQ operating mode and bits that specify SERIRQ interrupt sources.
R/W Bit 7 Bit Name Initial Value Slave Host Description IRQ11E3 0 R/W Host IRQ11 Interrupt Enable 3 Enables or disables an HIRQ11 interrupt request when OBF3A is set by an ODR3 write. 0: HIRQ11 interrupt request by OBF3A and IRQE11E3 is disabled [Clearing conditions] * * * Writing 0 to IRQ11E3 LPC hardware reset, LPC software reset Clearing OBF3A to 0 (when IEDIR3 = 0) HIRQ11 interrupt request by setting OBF3A to 1 is enabled [When IEDIR3 = 1] HIRQ11 interrupt is requested [Setting condition] Writing 1 after reading IRQ11E3 = 0 6 IRQ10E3 0 R/W Host IRQ10 Interrupt Enable 3 Enables or disables an HIRQ10 interrupt request when OBF3A is set by an ODR3 write. 0: HIRQ10 interrupt request by OBF3A and IRQE10E3 is disabled [Clearing conditions] * * * Writing 0 to IRQ10E3 LPC hardware reset, LPC software reset Clearing OBF3A to 0 (when IEDIR3 = 0) HIRQ10 interrupt request by setting OBF3A to 1 is enabled [When IEDIR3 = 1] HIRQ10 interrupt is requested [Setting condition] Writing 1 after reading IRQ10E3 = 0
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1: [When IEDIR3 = 0]
1: [When IEDIR3 = 0]
Section 19 LPC Interface (LPC)
R/W Bit 5 Bit Name Initial Value Slave Host Description IRQ9E3 0 R/W Host IRQ9 Interrupt Enable 3 Enables or disables an HIRQ9 interrupt request when OBF3A is set by an ODR3 write. 0: HIRQ9 interrupt request by OBF3A and IRQE9E3 is disabled [Clearing conditions] * * * Writing 0 to IRQ9E3 LPC hardware reset, LPC software reset Clearing OBF3A to 0 (when IEDIR3 = 0) HIRQ9 interrupt request by setting OBF3A to 1 is enabled [When IEDIR3 = 1] HIRQ9 interrupt is requested [Setting condition] Writing 1 after reading IRQ9E3 = 0 4 IRQ6E3 0 R/W Host IRQ6 Interrupt Enable 3 Enables or disables an HIRQ6 interrupt request when OBF3A is set by an ODR3 write. 0: HIRQ6 interrupt request by OBF3A and IRQE6E3 is disabled [Clearing conditions] * * * Writing 0 to IRQ6E3 LPC hardware reset, LPC software reset Clearing OBF3A to 0 (when IEDIR3 = 0) HIRQ6 interrupt request by setting OBF3A to 1 is enabled [When IEDIR3 = 1] HIRQ6 interrupt is requested [Setting condition] Writing 1 after reading IRQ6E3 = 0
1: [When IEDIR3 = 0]
1: [When IEDIR3 = 0]
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Section 19 LPC Interface (LPC)
R/W Bit 3 Bit Name Initial Value Slave Host Description IRQ11E2 0 R/W Host IRQ11 Interrupt Enable 2 Enables or disables an HIRQ11 interrupt request when OBF2 is set by an oDR2 write. 0: HIRQ11 interrupt request by OBF2 and IRQE11E2 is disabled [Clearing conditions] * * * Writing 0 to IRQ11E2 LPC hardware reset, LPC software reset Clearing OBF2 to 0 (when IEDIR2 = 0) HIRQ11 interrupt request by setting OBF2 to 1 is enabled [When IEDIR2 = 1] HIRQ11 interrupt is requested [Setting condition] Writing 1 after reading IRQ11E2 = 0 2 IRQ10E2 0 R/W Host IRQ10 Interrupt Enable 2 Enables or disables an HIRQ10 interrupt request when OBF2 is set by an ODR2 write. 0: HIRQ10 interrupt request by OBF2 and IRQE10E2 is disabled [Clearing conditions] * * * Writing 0 to IRQ10E2 LPC hardware reset, LPC software reset Clearing OBF2 to 0 (when IEDIR2 = 0) HIRQ10 interrupt request by setting OBF2 to 1 is enabled [When IEDIR2 = 1] HIRQ10 interrupt is requested [Setting condition] Writing 1 after reading IRQ10E2 = 0
1: [When IEDIR2 = 0]
1: [When IEDIR2 = 0]
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Section 19 LPC Interface (LPC)
R/W Bit 1 Bit Name Initial Value Slave Host Description IRQ9E2 0 R/W Host IRQ9 Interrupt Enable 2 Enables or disables an HIRQ9 interrupt request when OBF2 is set by an oDR2 write. 0: HIRQ9 interrupt request by OBF2 and IRQE9E2 is disabled [Clearing conditions] * * * Writing 0 to IRQ9E2 LPC hardware reset, LPC software reset Clearing OBF2 to 0 (when IEDIR2 = 0) HIRQ9 interrupt request by setting OBF2 to 1 is enabled [When IEDIR2 = 1] HIRQ9 interrupt is requested [Setting condition] Writing 1 after reading IRQ9E2 = 0 0 IRQ6E2 0 R/W Host IRQ6 Interrupt Enable 2 Enables or disables an HIRQ6 interrupt request when OBF2 is set by an oDR2 write. 0: HIRQ6 interrupt request by OBF2 and IRQE6E2 is disabled [Clearing conditions] * * * Writing 0 to IRQ6E2 LPC hardware reset, LPC software reset Clearing OBF2 to 0 (when IEDIR2 = 0) HIRQ6 interrupt request by setting OBF2 to 1 is enabled [When IEDIR2 = 1] HIRQ6 interrupt is requested [Setting condition] Writing 1 after reading IRQ6E2 = 0
1: [When IEDIR2 = 0]
1: [When IEDIR2 = 0]
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Section 19 LPC Interface (LPC)
19.3.14 SERIRQ Control Register 2 (SIRQCR2) SIRQCR2 contains bits that enable or disable SERIRQ interrupt requests and select the host interrupt request outputs.
R/W Bit 7 Bit Name Initial Value Slave Host Description IEDIR3 0 R/W Interrupt Enable Direct Mode 3 Selects whether an SERIRQ interrupt generation of LPC channel 3 is affected only by a host interrupt enable bit or by an OBF flag in addition to the enable bit. 0: A host interrupt is generated when both the enable bit and the corresponding OBF flag are set 1: A host interrupt is generated when the enable bit is set 6 to 0 All 0 R/W Reserved The initial value should not be changed.
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Section 19 LPC Interface (LPC)
19.3.15 SERIRQ Control Register 3 (SIRQCR3) SIRQCR3 selects the SERIRQ interrupt requests of the SCIF.
Initial Value All 0 0 0 0 0 R/W Slave Host Description R/W R/W R/W R/W R/W Reserved The initial value should not be changed. 3 2 1 0 SCSIRQ3 SCSIRQ2 SCSIRQ1 SCSIRQ0 SCIF SERIRQ Interrupt Select These bits select the SCIF interrupt request to the host. 0000: No interrupt request to the host 0001: HIRQ1 0010: SMI 0011: HIRQ3 0100: HIRQ4 0101: HIRQ5 0110: HIRQ6 0111: HIRQ7 1000: HIRQ8 1001: HIRQ9 1010: HIRQ10 1011: HIRQ11 1100: HIRQ12 1101: HIRQ13 1110: HIRQ14 1111: HIRQ15
Bit
Bit Name
7 to 4
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Section 19 LPC Interface (LPC)
19.3.16 SERIRQ Control Register 4 (SIRQCR4) SIRQCR4 controls LPC interrupt requests to the host.
Initial Value 0 R/W Slave Host Description R/W Host IRQ15 Interrupt Enable 0: Disables HIRQ15 interrupt request by IRQ15E 1: Enables HIRQ15 interrupt request 6 IRQ14E 0 R/W Host IRQ14 Interrupt Enable 0: Disables HIRQ14 interrupt request by IRQ14E 1: Enables HIRQ14 interrupt request 5 IRQ13E 0 R/W Host IRQ13 Interrupt Enable 0: Disables HIRQ13 interrupt request by IRQ13E 1: Enables HIRQ13 interrupt request 4 IRQ8E 0 R/W Host IRQ8 Interrupt Enable 0: Disables HIRQ8 interrupt request by IRQ8E 1: Enables HIRQ8 interrupt request 3 IRQ7E 0 R/W Host IRQ7 Interrupt Enable 0: Disables HIRQ7 interrupt request by IRQ7E 1: Enables HIRQ7 interrupt request 2 IRQ5E 0 R/W Host IRQ5 Interrupt Enable 0: Disables HIRQ5 interrupt request by IRQ5E 1: Enables HIRQ5 interrupt request 1 IRQ4E 1 R/W Host IRQ4 Interrupt Enable 0: Disables HIRQ4 interrupt request by IRQ4E 1: Enables HIRQ4 interrupt request 0 IRQ3E 1 R/W Host IRQ3 Interrupt Enable 0: Disables HIRQ3 interrupt request by IRQ3E 1: Enables HIRQ3 interrupt request
Bit 7
Bit Name IRQ15E
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Section 19 LPC Interface (LPC)
19.3.17 SERIRQ Control Register 5 (SIRQCR5) SIRQCR5 selects the output of the host interrupt request signal of each frame.
Initial Value 0 0 0 0 0 0 0 0 R/W Slave Host Description R/W R/W R/W R/W R/W R/W R/W R/W SERIRQ Output Select These bits select the state of the output on the pin for LPC host interrupt requests (HIRQ15, HIRQ14, HIRQ13, HIRQ8, HIRQ7, HIRQ5, HIRQ4, and HIRQ3). 0: [When host interrupt request is cleared] SERIRQ pin output is in the Hi-Z state [When host interrupt request is set] SERIRQ pin output is low 1: [When host interrupt request is cleared] SERIRQ pin output is low [When host interrupt request is set] SERIRQ pin output is in the Hi-Z state.
Bit 7 6 5 4 3 2 1 0
Bit Name SELIRQ15 SELIRQ14 SELIRQ13 SELIRQ8 SELIRQ7 SELIRQ5 SELIRQ4 SELIRQ3
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Section 19 LPC Interface (LPC)
19.3.18 Host Interface Select Register (HISEL) HISEL selects the function of bits 7 to 4 in STR3 and selects the output of the host interrupt request signal of each frame.
Initial Value 0 R/W Slave Host Description R/W Status Register 3 Selection Selects the function of bits 7 to 4 in STR3 in combination with the TWRE bit in LADR3L. For details of STR3, see section 19.3.11, Status Registers 1 to 3 (STR1 to STR3). 0: Bits 7 to 4 in STR3 indicate processing status of the LPC interface. 1: [When TWRE = 1] Bits 7 to 4 in STR3 indicate processing status of the LPC interface. [When TWRE = 0] Bits 7 to 4 in STR3 are readable/writable bits which user can use as necessary 6 5 4 3 2 1 0 SELIRQ11 SELIRQ10 SELIRQ9 SELIRQ6 SELSMI SELIRQ12 SELIRQ1 0 0 0 0 0 1 1 R/W R/W R/W R/W R/W R/W R/W Host IRQ Interrupt Select These bits select the state of the output on the SERIRQ pin. 0: [When host interrupt request is cleared] SERIRQ pin output is in the Hi-Z state [When host interrupt request is set] SERIRQ pin output is low 1: [When host interrupt request is cleared] SERIRQ pin output is low [When host interrupt request is set] SERIRQ pin output is in the Hi-Z state.
Bit 7
Bit Name SELSTR3
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Section 19 LPC Interface (LPC)
19.3.19 SCIF Address Register (SCIFADRH, SCIFADRL) SCIFADR sets the host address for the SCIF. Do not change the contents of SCIFADR while the SCIF is operating (i.e. while SCIFE is set to 1). * SCIFADRH
Initial Value 0 0 0 0 0 0 1 1 R/W Slave Host Description R/W R/W R/W R/W R/W R/W R/W R/W SCIF Address 15 to 8 These bits set the host address for the SCIF.
Bit 7 6 5 4 3 2 1 0
Bit Name
* SCIFADRL
Initial Value 1 1 1 1 1 0 0 0 R/W Slave Host Description R/W R/W R/W R/W R/W R/W R/W R/W SCIF Address 7 to 0 These bits set the host address for the SCIF.
Bit 7 6 5 4 3 2 1 0
Bit Name
Note: When the SCIF is in use, SCIFADR must be set to an address that is different from those for LPC channels 1, 2, and 3.
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Section 19 LPC Interface (LPC)
19.3.20 SMIC Flag Register (SMICFLG) SMICFLG is one of the registers used to implement SMIC mode. This register includes bits that indicate whether or not the system is ready to data transfer and those that are used for handshake of the transfer cycles.
R/W Bit Bit Name 7 RX_DATA_RDY Initial Value Slave Host Description 0 R/W R Read Transfer Ready Indicates whether or not the slave is ready for the host read transfer. 0: Slave waits for ready status 1: Slave is ready for the host read transfer 6 TX_DATA_RDY 0 R/W R Write Transfer Ready Indicates whether or not the slave is ready for the host next write transfer. 0: The slave waits for ready status 1: The slave is ready for the host write transfer. 5 4 SMI 0 0 R/W R/W R R Reserved The initial value should not be changed. SMI Flag This bit indicates that the SMI is asserted. 0: Indicates waiting for SMI assertion 1: Indicates SMI assertion 3 SEVT_ATN 0 R/W R Event Flag When the slave detects an event for the host, this bit is set. 0: Indicates waiting for event detection 1: Indicates event detection 2 SMS_ATN 0 R/W R SMS Flag When there is a message to be transmitted from the slave to the host, this bit is set. 0: There is not a message 1: There is a message
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Section 19 LPC Interface (LPC)
R/W Bit 1 0 Bit Name Initial Value Slave Host Description BUSY 0 0 R/W R Reserved The initial value should not be changed. R/(W)* W SMIC Busy This bit indicates that the slave is now transferring data. This bit can be cleared only by the slave and set only by the host. The rising edge of this bit is a source of internal interrupt to the slave. 0: Transfer cycle wait state [Clearing conditions] After the slave reads BUSY = 1, writes 0 to this bit. 1: Transfer cycle in progress [Setting condition] When the host writes 1 to this bit. Note: Only 0 can be written to clear the flag.
19.3.21 SMIC Control Status Register (SMICCSR) SMICCSR is one of the registers used to implement SMIC mode. This is an 8-bit readable/writable register that stores a control code issued from the host and a status code that is returned from the slave. The control code is written to this register accompanied by the transfer between the host and slave. The status code is returned to this register to indicate that the slave has recognized the control code, and a specified transfer cycle has been completed. 19.3.22 SMIC Data Register (SMICDTR) SMICDTR is one of the registers used to implement SMIC mode. This is an 8-bit register that is accessible (readable/writable) from both the slave processor (this LSI) and host processor. This is used for data transfer between the host and slave.
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Section 19 LPC Interface (LPC)
19.3.23 SMIC Interrupt Register 0 (SMICIR0) SMICIR0 is one of the registers used to implement SMIC mode. This register includes the bits that indicate the source of interrupt to the slave.
R/W Bit Bit Name Initial Value Slave Host Description All 0 0 R/W Reserved The initial value should not be changed. 4 HDTWI R/(W)* Transfer Data Transmission End Interrupt This is a status flag that indicates that the host has finished transmitting the transfer data to SMICDTR. When the IBFIE3 bit and HDTWIE bit are set to 1, the IBFI3 interrupt is requested to the slave. 0: Transfer data transmission wait state [Clearing condition] After the slave reads HDTWI = 1, writes 0 to this bit. 1: Transfer data transmission end [Setting condition] The transfer cycle is write transfer and the host writes the transfer data to SMICDTR. 3 HDTRI 0 R/(W)* Transfer Data Receive End Interrupt This is a status flag that indicates that the host has finished receiving the transfer data from SMICDTR. When the IBFIE3 bit and HDTRIE bit are set to 1, the IBFI3 interrupt is requested to the slave. 0: Transfer data receive wait state [Clearing condition] After the slave reads HDTRI = 1, writes 0 to this bit. 1: Transfer data receive end [Setting condition] The transfer cycle is read transfer and the host reads the transfer data from SMICDTR. 7 to 5
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Section 19 LPC Interface (LPC)
R/W Bit 2 Bit Name Initial Value Slave Host Description STARI 0 R/(W)* Status Code Receive End Interrupt This is a status flag that indicates that the host has finished receiving the status code from SMICCSR. When the IBFIE3 bit and STARIE bit are set to 1, the IBFI3 interrupt is requested to the slave. 0: Status code receive wait state [Clearing condition] After the slave reads STARI = 1, writes 0 to this bit. 1: Status code receive end [Setting condition] When the host reads the status code of SMICCSR. 1 CTLWI 0 R/(W)* Control Code Transmission End Interrupt This is a status flag that indicates that the host has finished transmitting the control code to SMICCSR. When the IBFIE3 bit and CTLWIE bit are set to1, the IBFI3 interrupt is requested to the slave. 0: Control code transmission wait state [Clearing condition] After the slave reads CTLWI = 1, writes 0 to this bit. 1: Control code transmission end [Setting condition] When the host writes the status code to SMICCSR. 0 BUSYI 0 R/(W)* Transfer Start Interrupt This is a status flag that indicates that the host starts transferring. When the IBFIE3 bit and BUSYIE bit are set to 1, the IBFI3 interrupt is requested to the slave. 0: Transfer start wait state [Clearing condition] After the slave reads BUSYI = 1, writes 0 to this bit. 1: Transfer start [Setting condition] When the rising edge of the BUSY bit in SMICFLG is detected. Note: * Only 0 can be written to clear the flag.
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Section 19 LPC Interface (LPC)
19.3.24 SMIC Interrupt Register 1 (SMICIR1) SMICIR1 is one of the registers used to implement SMIC mode. This register includes the bits that enables/disables an interrupt to the slave. The IBFI3 interrupt is enabled by setting the IBFIE3 bit in HICR2 to 1.
R/W Bit Bit Name Initial Value Slave Host Description All 0 R/W R/W Reserved The initial value should not be changed. Transfer Data Transmission End Interrupt Enable Enables or disables HDTWI interrupt that is IBFI3 interrupt source to the slave. 0: Disables transfer data transmission end interrupt 1: Enables transfer data transmission end interrupt 3 HDTRIE 0 R/W Transfer Data Receive End Interrupt Enable Enables or disables HDTRI interrupt that is IBFI3 interrupt source to the slave. 0: Disables transfer data receive end interrupt 1: Enables transfer data receive end interrupt 2 STARIE 0 R/W Status Code Receive End Interrupt Enable Enables or disables STARI interrupt that is IBFI3 interrupt source to the slave. 0: Disables status code receive end interrupt 1: Enables status code receive end interrupt 1 CTLWIE 0 R/W Control Code Transmission End Interrupt Enable Enables or disables CTLWI interrupt that is IBFI3 interrupt source to the slave. 0: Disables control code transmission end interrupt 1: Enables control code transmission end interrupt 0 BUSYIE 0 R/W Transfer Start Interrupt Enable Enables or disables BUSYI interrupt that is IBFI3 interrupt source to the slave. 0: Disables transfer start interrupt 1: Enables transfer start interrupt 7 to 5 4
HDTWIE 0
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Section 19 LPC Interface (LPC)
19.3.25 BT Status Register 0 (BTSR0) BTSR0 is one of the registers used to implement BT mode. This register includes flags that control interrupts to the slave (this LSI).
R/W Bit Bit Name Initial Value Slave Host Description All 0 0 R/W Reserved The initial value should not be changed. 4 FRDI R/(W)* FIFO Read Request Interrupt This status flag indicates that host writes the data to BTDTR buffer with FIFO full state at the host write transfer. When the IBFIE3 bit and FRDIE bit are set to 1, IBFI3 interrupt is requested to the slave. The slave must clear the flag after creating an unused area by reading the data in FIFO. 0: FIFO read is not requested [Clearing condition] After the slave reads FRDI = 1, writes 0 to this bit. 1: FIFO read is requested [Setting condition] After the host processor transfers data, the host writes the data with FIFO Full state. 3 HRDI 0 R/(W)* BT Host Read Interrupt This status flag indicates that the host reads 1 byte from BTDTR buffer. When the IBFIE3 bit and HRDIE bit are set to 1, IBFI3 interrupt is requested to the slave. 0: Host BTDTR read wait state [Clearing condition] After the slave reads HRDI = 1, writes 0 to this bit. 1: The host reads from BTDTR [Setting condition] The host reads one byte from BTDTR. 7 to 5
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Section 19 LPC Interface (LPC)
R/W Bit 2 Bit Name Initial Value Slave Host Description HWRI 0 R/(W)* BT Host Write Interrupt This status flag indicates that the host writes 1byte to BTDTR buffer. When the IBFIE3 bit and HWRIE bit are set to 1, IBFI3 interrupt is requested to the slave. 0: Host BTDTR write wait state [Clearing condition] After the slave reads HWRI = 1, writes 0 to this bit. 1: The host writes to BTDTR [Setting condition] The host writes one byte to BTDTR. 1 HBTWI 0 R/(W)* BTDTR Host Write Start Interrupt This status flag indicates that the host writes the first byte of valid data to BTDTR buffer. When the IBFIE3 bit and HBTWIE bit are set to 1, IBFI3 interrupt is requested to the slave. 0: BTDTR host write start wait state [Clearing condition] After the slave reads HBTWI = 1 and writes 0 to this bit. 1: BTDTR host write start [Setting condition] The host starts writing valid data to BTDTR.
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Section 19 LPC Interface (LPC)
R/W Bit 0 Bit Name Initial Value Slave Host Description HBTRI 0 R/(W)* BTDTR Host Read End Interrupt This status flag indicates that the host reads all valid data from BTDTR buffer. When the BFIE3 bit and HBTRIE bit are set to 1, IBFI3 interrupt is requested to the slave. 0: BTDTR host read end wait state [Clearing condition] After the slave reads HBTRI = 1 and writes 0 to this bit. 1: BTDTR host read end [Setting condition] When the host finished reading the valid data from BTDTR. Note: * Only 0 can be written to clear the flag.
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Section 19 LPC Interface (LPC)
19.3.26 BT Status Register 1 (BTSR1) BTSR1 is one of the registers used to implement the BT mode. This register includes a flag that controls an interrupt to the slave (this LSI).
R/W Bit 7 6 Bit Name Initial Value Slave Host Description HRSTI 0 0 R/W Reserved The initial value should not be changed. R/(W)* BT Reset Interrupt This status flag indicates that the BMC_HWRST bit in BTIMSR is set to 1 by the host. When the IBFIE3 bit and HRSTIE bit are set to 1, IBFI3 interrupt is requested to the slave. 0: [Clearing condition] When the slave reads HRSTI = 1 and writes 0 to this bit. 1: [Setting condition] When the slave detects the rising edge of BMC_HWRST. 5 IRQCRI 0 R/(W)* B2H_IRQ Clear Interrupt This status flag indicates that the B2H_IRQ bit in BTIMSR is cleared by the host. When the IBFIE3 bit and IRQCRIE bit are set to 1, IBFI3 interrupt is requested to the slave. 0: [Clearing condition] When the slave reads IRQCRI = 1 and writes 0 to this bit. 1: [Setting condition] When the slave detects the falling edge of B2H_IRQ.
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Section 19 LPC Interface (LPC)
Bit 4
Bit Name BEVTI
Initial Value 0
R/W Slave R/(W)* Host Description BEVT_ATN Clear Interrupt This status flag indicates that the BEVT_ATN bit in BTCR is cleared by the host. When the IBFIE3 bit and BEVTIE bit are set to 1, IBFI3 interrupt is requested to the slave. 0: [Clearing condition] When the slave reads BEVTI = 1 and writes 0 to this bit. 1: [Setting condition] When the slave detects the falling edge of BEVT_ATN.
3
B2HI
0
R/(W)*
Read End Interrupt This status flag indicates that the host has finished reading all data from the BTDTR buffer. When the IBFIE3 bit and B2HIE bit are set to 1, the IBFI3 interrupt is requested to the slave. 0: [Clearing condition] When the slave reads B2HI = 1 and writes 0 to this bit. 1: [Setting conditions] When the slave detects the falling edge of B2H_ATN.
2
H2BI
0
R/(W)*
Write End Interrupt This status flag indicates that the host has finished writing all data to the BTDTR buffer. When the IBFIE3 bit and H2BIE bit are set to 1, the IBFI3 interrupt is requested to the slave. 0: [Clearing condition] After the slave reads H2BI = 1, writes 0 to this bit. 1: [Setting condition] When the slave detects the falling edge of H2B_ATN.
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Section 19 LPC Interface (LPC)
Bit 1
Bit Name CRRPI
Initial Value 0
R/W Slave Host Description Read Pointer Clear Interrupt This status flag indicates that the CLR_RD_PTR bit in BTCR is set to 1 by the host. When the IBFIE3 bit and CRRPIE bit are set to 1, the IBFI3 interrupt is requested to the slave. 0: [Clearing condition] After the slave reads CRRPI = 1, writes 0 to this bit. 1: [Setting condition] When the slave detects the rising edge of CLR_RD_PTR. R/(W)*
0
CRWPI
0
R/(W)*
Write Pointer Clear Interrupt This status flag indicates that the CLR_WR_PTR bit in BTCR is set to 1 by the host. When the IBFIE3 bit and CRWPIE bit are set to 1, the IBFI3 interrupt is requested to the slave. 0: [Clearing condition] After the slave reads CRWPI = 1, writes 0 to this bit. 1: [Setting condition] When the slave detects the rising edge of CLR_WR_PTR.
Note:
*
Only 0 can be written to clear the flag.
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Section 19 LPC Interface (LPC)
19.3.27 BT Control Status Register 0 (BTCSR0) BTCSR0 is one of the registers used to implement the BT mode. The BTCSR0 register contains the bits used to switch FIFOs in BT transfer, and enable or disable the interrupts to the slave (this LSI). The IBFI3 interrupt is enabled by setting the IBFIE3 bit in HICR2 to 1.
Initial Value 0 0 0 R/W Slave Host Description R/W R/W R/W Reserved The initial value should not be changed. 6 5 FSEL1 FSEL0 These bits select either FIFO during BT transfer FSEL1 FSEL0 0 1 X X :FIFO disabled :FIFO enabled
Bit 7
Bit Name
The FIFO size: 64 bytes (for host write transfer), additional 64 bytes (for host read transfer). 4 FRDIE 0 R/W FIFO Read Request Interrupt Enable Enables or disables the FRDI interrupt which is an IBFI3 interrupt source to the slave. 0: FIFO read request interrupt is disabled. 1: FIFO read request interrupt is enabled. 3 HRDIE 0 R/W BT Host Read Interrupt Enable Enables or disables the HRDI interrupt which is an IBFI3 interrupt source to the slave. When using FIFO, the HRDIE bit must not be set to 1. 0: BT host read interrupt is disabled. 1: BT host read interrupt is enabled. 2 HWRIE 0 R/W BT Host Write Interrupt Enable Enables or disables the HWRI interrupt which is an IBFI3 interrupt source to the slave. When using FIFO, the HWRIE bit must not be set to 1. 0: BT host write interrupt is disabled. 1: BT host write interrupt is enabled.
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Section 19 LPC Interface (LPC)
Bit 1
Bit Name HBTWIE
Initial Value 0
R/W Slave Host Description R/W BTDTR Host Write Start Interrupt Enable Enables or disables the HBTWI interrupt which is an IBFI3 interrupt source to the slave. 0: BTDTR host write start interrupt is disabled. 1: BTDTR host write start interrupt is enabled.
0
HBTRIE
0
R/W
BTDTR Host Read End Interrupt Enable Enables or disables the HBTRI interrupt which is an IBFI3 interrupt source to the slave. 0: BTDTR host read end interrupt is disabled. 1: BTDTR host read end interrupt is enabled.
Note:
X Don't care.
19.3.28 BT Control Status Register 1 (BTCSR1) BTCSR1 is one of the registers used to implement the BT mode. The BTCSR1 register contains the bits used to enable or disable interrupts to the slave (this LSI). The IBFI3 interrupt is enabled by setting the IBFIE3 bit in HICR2 to 1.
Initial Value R/W Slave Host R/W Description Slave Reset Read Enable The host reads 0 from the BMC_HWRST bit in BTIMSR. When this bit is set to 1, the host can read 1 from the BMC_HWRST bit. 0: Host always reads 0 from BMC_HWRST 1: Host can reads 0 from BMC_HWRST 6 HRSTIE 0 R/W BT Reset Interrupt Enable Enables or disables the HRSTI interrupt which is an IBFI3 interrupt source to the slave. 0: BT reset interrupt is disabled. 1: BT reset interrupt is enabled.
Bit 7
Bit Name
RSTRENBL 0
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Section 19 LPC Interface (LPC)
Bit 5
Bit Name IRQCRIE
Initial Value 0
R/W Slave Host R/W Description B2H_IRQ Clear Interrupt Enable Enables or disables the IRQCRI interrupt which is an IBFI3 interrupt source to the slave. 0: B2H_IRQ clear interrupt is disabled. 1: B2H_IRQ clear interrupt is enabled.
4
BEVTIE
0
R/W
BEVT_ATN Clear Interrupt Enable Enables or disables the BEVTI interrupt which is an IBFI3 interrupt source to the slave. 0: BEVT_ATN clear interrupt is disabled. 1: BEVT_ATN clear interrupt is enabled.
3
B2HIE
0
R/W
Read End Interrupt Enable Enables or disables the B2HI interrupt which is an IBFI3 interrupt source to the slave. 0: Read end interrupt is disabled. 1: Read end interrupt is enabled.
2
H2BIE
0
R/W
Write End Interrupt Enable Enables or disables the H2BI interrupt which is an IBFI3 interrupt source to the slave. 0: Write end interrupt is disabled. 1: Write end interrupt is enabled.
1
CRRPIE
0
R/W
Read Pointer Clear Interrupt Enable Enables or disables the CRRPI interrupt which is an IBFI3 interrupt source to the slave. 0: Read pointer clear interrupt is disabled. 1: Read pointer clear interrupt is enabled.
0
CRWPIE
0
R/W
Write Pointer Clear Interrupt Enable Enables or disables the CRWPI interrupt which is an IBFI3 interrupt source to the slave. 0: Write pointer clear interrupt is disabled. 1: Write pointer clear interrupt is enabled.
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Section 19 LPC Interface (LPC)
19.3.29 BT Control Register (BTCR) BTCR is one of the registers used to implement BT mode. The BTCR register contains bits used in transfer cycle handshaking, and those indicating the completion of data transfer to the buffer.
R/W Initial Value Slave Host 1 R/W R
Bit 7
Bit Name B_BUSY
Description BT Write Transfer Busy Flag Read-only bit from the host. Indicates that the BTDTR buffer is being used for BT write transfer (write transfer is in progress.) 0: Indicates waiting for BT write transfer 1: Indicates that the BTDTR buffer is being used
6
H_BUSY
0
R
(W)*
3
BT Read Transfer Busy Flag This is a set/clear bit from the host. Indicates that the BTDTR buffer is being used for BT read transfer (read transfer is in progress.) 0: Indicates waiting for BT read transfer [Clearing condition] When the host writes a 1 while H_BUSY is set to 1. 1: Indicates that the BTDTR buffer is being used [Setting condition] When the host writes a 1 while H_BUSY is set to 0.
5
OEM0
0
R/W
R/(W)*
4
User defined bit This bit is defined by the user, and validated only when set to 1 by a 0 written from the host. 0: [Clearing condition] When the slave writes a 0 after a 1 has been read from OEM0. 1: [Setting condition] When the slave writes a 1, after a 0 has been read from OEM0, or when the host writes a 0.
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Section 19 LPC Interface (LPC)
Bit 4
Bit Name
Initial Value
R/W Slave R/(W)*
1
Host R/(W)*
5
Description Event Interrupt Sets when the slave detects an event to the host. Setting the B2H_IRQ_EN bit in the BTIMSR register enables the BEVT_ATN bit to be used as an interrupt source to the host. 0: No event interrupt request is available [Clearing condition] When the host writes a 1 to the bit. 1: An event interrupt request is available [Setting condition] When the slave writes a 1 after a 0 has been read from BEVT_ATN.
BEVT_ATN 0
3
B2H_ATN
0
R/(W)*
1
R/(W)*
5
Slave Buffer Write End Indication Flag This status flag indicates that the slave has finished writing all data to the BTDTR buffer. Setting the B2H_IRQ_EN bit in the BTIMSR register enables the B2H_ATN bit to be used as an interrupt source to the host. 0: Host has completed reading the BTDTR buffer [Clearing condition] When the host writes a 1 1: Slave has completed writing to the BTDTR buffer [Setting condition] When the slave writes a 1 after a 0 has been read from B2N_ATN.
2
H2B_ATN
0
R/(W)*
2
R/(W)*
1
Host Buffer Write End Indication Flag This status flag indicates that the host has finished writing all data to the BTDTR buffer. 0: Slave has completed reading the BTDTR buffer [Clearing condition] When the slave writes a 0 after a 1 has been read from H2B_ATN. 1: Host has completed writing to the BTDTR buffer [Setting condition] When the host writes a 1
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Section 19 LPC Interface (LPC)
Bit 1
Bit Name CLR_RD_ PTR
Initial Value 0
R/W Slave
2
Host Description
1
R/(W)* (W)* Read Pointer Clear This bit is used by the host to clear the read pointer during read transfer. A host read operation always yields 0 on readout. 0: Read pointer clear wait [Clearing condition] When the slave writes a 0 after a 1 has been read from CLR_RD_PTR. 1: Read pointer clear [Setting condition] When the host writes a 1.
0
CLR_WR_ PTR
0
R/(W)* (W)* Write Pointer Clear This bit is used by the host to clear the write pointer during write transfer. A host read operation always yields 0 on readout. 0: Write pointer clear wait [Clearing condition] When the slave writes a 0 after a 1 has been read from CLR_WR_PTR. 1: Write pointer clear [Setting condition] When the host writes a 1.
2
1
Notes: 1. 2. 3. 4. 5.
Only 1 can be written to set this flag. Only 0 can be written to clear this flag. Only 1 can be written to toggle this flag. Only 0 can be written to set this flag. Only 1 can be written to clear this flag.
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Section 19 LPC Interface (LPC)
19.3.30 BT Data Buffer (BTDTR) BTDTR is used to implement the BT mode. BTDTR consists of two FIFOs: the host write transfer FIFO and the host read transfer FIFO. Their capacities are 64 bytes each. When using BTDTR, enable FIFO by means of the bits FSEL0 and FSEL1.
Initial Value R/W Slave Host Description R/W The data written by the host is stored in FIFO (64 bytes) for host write transfer and read out by the slave in order of host writing. The data written by the slave is stored in FIFO (64 bytes) for host read transfer and read out by the host in order of slave writing.
Bit
Bit Name
7 to 0 bit7 to bit0 Undefined R/W
19.3.31 BT Interrupt Mask Register (BTIMSR) BTIMSR is one of the registers used to implement BT mode. The BTIMSR register contains the bits used to control the interrupts to the host.
Initial Value 0 R/W Slave R/(W)*
2
Bit 7
Bit Name BMC_ HWRST
Host
1
Description
R/(W)* Slave Reset Performs a reset from the host to the slave. The host can only write a 1. Writing a 0 to this bit is invalid. The host will always return a 0 on read out. Setting the RSTRENBL bit enables a 1 to be read from the host. 0: The reset is cancelled [Clearing condition] When the slave writes a 0, after a 1 has been read from BMC_HWRST. 1: The reset is in progress. [Setting condition] When the host writes a 1.
6 5

0 0
R/W R/W
R/W R/W
Reserved
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Section 19 LPC Interface (LPC)
Bit 4 3 2
Bit Name OEM3 OEM2 OEM1
Initial Value Slave 0 0 0 R/W R/W R/W
R/W Host
4 4
Description
R/(W)* User defined bit R/(W)* These bits are defined by the user and are valid 4 R/(W)* only when set to 1 by a 0 written from the host. 0: [Clearing condition] When the slave writes a 0, after a 1 has been read from OEM. 1: [Setting condition] When the slave writes a 1, after a 0 has been read from OEM, or when the host writes a 0.
1
B2H_IRQ
0
R/(W)*
1
R/(W)* BMC to HOST interrupt Informs the host that an interrupt has been requested when the BEVT_ATN or B2H_ATN bit has been set. The SERIRQ is not issued. To generate the SERIRQ, it should be issued by the program. 0: B2H_IRQ interrupt is not requested [Clearing condition] When the host writes a 1. 1: B2H_IRQ interrupt is requested [Setting condition] When the slave writes a 1, after a 0 has been read from B2H_IRQ
3
0
B2H_IRQ_EN 0
R
R/W
BMC to HOST interrupt enable Enables or disables the B2H_IRQ interrupt which is an interrupt source from the slave to the host. 0: B2H_IRQ interrupt is disabled [Clearing condition] When a 0 is written by the host. 1: B2H_IRQ interrupt is enabled [Setting condition] When a 1 is written by the host.
Notes: 1. Only 1 can be written to set this flag. 2. Only 0 can be written to clear this flag. 3. Only 1 can be written to clear this flag. 4. Only 0 can be written to set this flag.
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Section 19 LPC Interface (LPC)
19.3.32 BT FIFO Valid Size Register 0 (BTFVSR0) BTFVSR0 is one of the registers used to implement BT mode. BTFVSR0 indicates a valid data size in the FIFO for host write transfer.
R/W Bit Bit Name Initial Value Slave Host Description R These bits indicate the number of valid bytes in the FIFO (the number of bytes which the slave can read) for host write transfer. When data is written from the host, the value in BTFVSR0 is incremented by the number of bytes that have been written to. Further, when data is read from the slave, the value is decremented by only the number of bytes that have been read.
7 to 0 N7 to N0 All 0
19.3.33 BT FIFO Valid Size Register 1 (BTFVSR1) BTFVSR1 is one of the registers used to implement BT mode. BTFVSR1 indicates a valid data size in the FIFO for host read transfer.
R/W Bit Bit Name Initial Value Slave Host Description R These bits indicate the number of valid bytes in the FIFO (the number of bytes which the host can read) for host read transfer. When data is written from the slave, the value in BTFVSR1 is incremented by the number of bytes that have been written to. Further, when data is read from the host, the value is decremented by only the number of bytes that have been read.
7 to 0 N7 to N0 All 0
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Section 19 LPC Interface (LPC)
19.4
19.4.1
Operation
LPC interface Activation
The LPC interface is activated by setting any one of bits LPC3E to LPC1E in HICR0 and bit SICIE bit in HICR5 to 1. When the LPC interface is activated, the related I/O port pins (PE7 to PE0, PD5 and PD4) function as dedicated LPC interface input/output pins. In addition, setting the FGA20E, PMEE, LSMIE, and LSCIE bits to 1 adds the related I/O port pins (PD3 to PD0) to the LPC interface's input/output pins. Use the following procedure to activate the LPC interface after a reset release. 1. Read the signal line status and confirm that the LPC module can be connected. Also check that the LPC module is initialized internally. 2. When using channels 1 and 2, set LADR1 and LADR2 to determine the I/O address. 3. When using channel 3, set LADR3 to determine the I/O address and whether bidirectional data registers are to be used. 4. When using the SCIF module, set SCIFAR to determine the I/O address. 5. Set the enable bit (LPC3E to LPC1E) for the channel to be used. Also set SCIFE if the SCIF is to be used. 6. Set the enable bits (FGA20E, PMEE, LSMIE, and LSCIE) for the additional functions to be used. 7. Set the selection bits for other functions (SDWNE, IEDIR). 8. As a precaution, clear the interrupt flags (LRST, SDWN, ABRT, OBF, and OBEI). Read IDR or TWR15 to clear IBF. 9. Set receive complete interrupt enable bits (IBFIE3 to IBFIE1, and ERRIE) as necessary. 19.4.2 LPC I/O Cycles
There are 12 types of LPC transfer cycle: LPC memory read, LPC memory write, I/O read, I/O write, DMA read, DMA write, bus master memory read, bus master memory write, bus master I/O read, bus master I/O write, FW memory read, and FW memory write. Of these, the LPC of this LSI supports I/O read and I/O write.
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Section 19 LPC Interface (LPC)
An LPC transfer cycle is started when the LFRAME signal goes low in the bus idle state. If the LFRAME signal goes low when the bus is not idle, this means that a forced termination (abort) of the LPC transfer cycle has been requested. In an I/O read cycle or I/O write cycle, transfer is carried out using LAD3 to LAD0 in the following order, in synchronization with LCLK. The host can be made to wait by sending back a value other than B'0000 in the slave's synchronization return cycle, but the LPC interface of this LSI always returns B'0000 (except for the BT interface). If the received address matches the host address for an LPC register, the LPC interface enters the busy state; it returns to the idle state by output of a state count 12 turnaround. Register and flag changes are made at this timing, so in the event of a transfer cycle forced termination (abort), registers and flags are not changed. The timing of the LFRAME, LCLK, and LAD signals is shown in figures 19.2 and 19.3. Table 19.5 LPC I/O Cycle
I/O Read Cycle State Count 1 2 3 4 5 6 7 8 9 10 11 12 13 Contents Start Cycle type/direction Address 1 Address 2 Address 3 Address 4 Drive Source Host Host Host Host Host Host Value (3 to 0) 0000 0000 Bits 15 to 12 Bits 11 to 8 Bits 7 to 4 Bits 3 to 0 1111 ZZZZ 0000 Bits 3 to 0 Bits 7 to 4 1111 ZZZZ Contents Start Cycle type/direction Address 1 Address 2 Address 3 Address 4 Data 1 Data 2 I/O Write Cycle Drive Source Host Host Host Host Host Host Host Host Value (3 to 0) 0000 0010 Bits 15 to 12 Bits 11 to 8 Bits 7 to 4 Bits 3 to 0 Bits 3 to 0 Bits 7 to 4 1111 ZZZZ 0000 1111 ZZZZ
Turnaround (recovery) Host Turnaround Synchronization Data 1 Data 2 None Slave Slave Slave
Turnaround (recovery) Host Turnaround Synchronization None Slave
Turnaround (recovery) Slave Turnaround None
Turnaround (recovery) Slave Turnaround None
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Section 19 LPC Interface (LPC)
LCLK
LFRAME
LAD3 to LAD0
Start Cycle type, direction, and size
ADDR
TAR
Sync
Data
TAR
Start
Number of clocks
1
1
4
2
1
2
2
1
Figure 19.2 Typical LFRAME Timing
LCLK LFRAME
LAD3 to LAD0
Start Cycle type, direction, and size
ADDR
TAR
Sync Slave must stop driving
Master will drive high
Too many Syncs cause timeout
Figure 19.3 Abort Mechanism 19.4.3 SMIC Mode Transfer Flow
Figure 19.4 shows the write transfer flow and figure 19.5 shows the read transfer flow in SMIC mode.
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Section 19 LPC Interface (LPC)
Slave
Host Host confirms the BUSY bit in SMICFLG. The bit indicates slave (this LSI) is ready for receiving a new control code. When BUSY = 1, access from host is disabled. Host confirms the TX_DATA_RDY bit in SMICFLG. The confirmation is unnecessary when Write Start control is issued.
Wait for BUSY = 0
Bit that indicates slave is ready for write transfer. Issues when slave is ready for the next write transfer.
Wait for TX_DATA_RDY = 1
A
Write control code
Host writes the Write control code in SMICCSR.
Slave confirms that control code is written to SMICCSR by host. The CTLWI bit in SMICIR0 is set. Slave waits for the BUSY bit in SMICFLG is set.
Generate slave interrupt
Write transfer data
Host writes transfer data in SMICDTR.
Slave confirms that valid data is written to SMICDTR by host. The HDTWI bit in SMICIR0 is set.
Generate slave interrupt
BUSY = 1
Host sets the BUSY bit in SMICFLG.
Slave confirms the rising edge of the BUSY bit in SMICFLG. The BUSYI bit in SMICIR0 is set.
Generate slave interrupt
Slave clears the TX_DATA_RDY bit in SMICFLG.
TX_DATA_RDY = 0
Slave reads the control code in SMICCSR.
Read control code
Slave reads transfer data in SMICDTR according to Write control code.
Read transfer data
Slave writes the status code to SMICCSR to notify the processing completion status.
Write status code
Slave clears the BUSY bit in SMICFLG to indicate transfer completion.
BUSY = 0 Host confirms the falling edge of the BUSY bit in SMICFLG. An interrupt is generated.
Generate host interrupt Abnormal A Read status code Normal Slave confirms that status code is read from SMICCSR by host. The STARI bit in SMICIR0 is set. Generate slave interrupt
Host confirms the status code in SMICCSR. In the case of normal completion, the status code is reflected to the next step. In the case of abnormal completion, the status code is READY and an error is kept.
Figure 19.4 SMIC Write Transfer Flow
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Section 19 LPC Interface (LPC)
Slave
Host
Wait for BUSY = 0
Host confirms the BUSY bit in SMICFLG. The bit indicates slave (this LSI) is ready for receiving a new control code. When BUSY = 1, access from host is disabled.
Bit that indicates slave is ready for read transfer. Issues when slave is ready for the next read transfer.
Waits for RX_DATA_RDY = 1
Host confirms the RX_DATA_RDY bit in SMICFLG.
Slave waits for the BUSY bit in SMICFLG is set.
A
Write control code
Host writes the Read control code to SMICCSR.
Slave confirms that control code is written to SMICCSR by host. The CTLWI bit in SMICIR0 is set.
Generate slave interrupt
BUSY = 1
Host sets the BUSY bit in SMICFLG.
Slave confirms the rising edge of the BUSY bit in SMICFLG. The BUSYI bit in SMICIR0 is set.
Generate slave interrupt
Slave clears the RX_DATA_RDY bit in SMICFLG.
RX_DATA_RDY = 0
Slave reads the control code in SMICCSR.
Read control code
Slave writes transfer data to SMICDTR according to Read control code.
Write transfer data
Slave writes the status code to SMICCSR to notify the processing completion status.
Write status code
Slave clears the BUSY bit in SMICFLG to indicate transfer completion.
BUSY = 0
Generate host interrupt
Host confirms the falling edge of the BUSY bit in SMICFLG. An interrupt is generated.
Read transfer data
Host reads transfer data in SMICDTR.
Slave confirms that valid data is read from SMICDTR by host. The HDTRI bit in SMICIR0 is set.
Abnormal A
Generate slave interrupt
Read status code Normal
Host confirms the status code in SMICCSR. In the case of normal completion, the status code is reflected to the next step. In the case of abnormal completion, the status code is READY and an error is kept.
Slave confirms that status code is read from SMICCSR by host. The STARI bit in SMICIR0 is set.
Generate slave interrupt
Figure 19.5 SMIC Read Transfer Flow
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Section 19 LPC Interface (LPC)
19.4.4
BT Mode Transfer Flow
Figure 19.6 shows the write transfer flow and figure 19.7 shows the read transfer flow in BT mode.
Slave
Host
Wait for B_BUSY = 0
Slave waits for the H2B_ATN bit (interrupt from host) is set.
Host confirms the B_BUSY bit in BTCR.
Wait for H2B_ATN = 0
Host confirms the H2B_ATN bit in BTCR.
Clear write pointer
Host clears write pointer by setting the CLR_WR_PTR bit in BTCR.
Confirms the CLR_WR_PTR bit. The CRWPI bit in BTSR1 is set to notify write pointer clearing as an interrupt to slave.
Generate slave interrupt
Write BTDTR buffer
Host writes data of 1 to n bytes to the BTDTR buffer.
Confirms host write is started. The HBTWI bit in BTSR0 is set.
Generate slave interrupt
H2B_ATN = 1
Host sets the H2B_ATN bit in BTCR to indicate data write completion to the buffer for the BT interface.
Confirms the H2B_ATN bit is set. The H2BI bit in BTSR1 is set.
Generate slave interrupt
Slave sets the B_BUSY bit in BTCR.
B_BUSY = 1
Slave reads data from the BTDTR buffer.
Read BTDTR buffer
Slave clears the H2B_ATN bit in BTCR.
H2B_ATN = 0
Slave clears the B_BUSY bit in BTCR to indicate transfer completion.
B_BUSY = 0
Figure 19.6 BT Write Transfer Flow
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Section 19 LPC Interface (LPC)
Slave
Host
Slave confirms the H_BUSY bit in BTCR.
Wait for H_BUSY = 0
Host waits for the B2H_ATN bit (interrupt from slave) is set by slave.
Slave writes data of 1 to n bytes to the BTDTR buffer. Slave sets the B2H_ATN bit in BTCR to indicate data write completion to the BTDTR buffer.
Write BTDTR buffer
B2H_ATN = 1
Generate host interrupt
Host confirms the B2H_ATN bit in BTCR. The slave data write completion interrupt is notified to host.
H_BUSY = 1
Host sets the H_BUSY bit in BTCR.
Clear read pointer
Host clears read pointer by setting the CLR_RD_PTR bit in BTCR.
Confirms the CLR_RD_PTR bit. The CRRPI bit in BTSR1 is set to notify read pointer clearing as an interrupt source to slave.
Generate slave interrupt
Read BTDTR buffer
Host reads data from the BTDTR buffer.
The HBTRI bit in BTSR0 is set to notify host reads all data through the BTDTR buffer.
Generate slave interrupt
B2H_ATN = 0
Host clears the B2H_ATN bit in BTCR.
Confirms the B2H_ATN bit. The B2HI bit in BTSR1 is set to notify host data read completion as an interrupt source to slave.
Generate slave interrupt
H_BUSY = 0
Host clears the H_BUSY bit in BTCR to indicate transfer completion.
Figure 19.7 BT Read Transfer Flow
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Section 19 LPC Interface (LPC)
19.4.5
Gate A20
The Gate A20 signal can mask address A20 to emulate the address mode of the 8086* architecture CPU used in personal computers. Normally, the Gate A20 signal can be controlled by a firmware. The fast Gate A20 function that realizes high-seed performance by hardware is enabled by setting the FGA20E bit to 1 in HICR0. Note: An Intel microprocessor (1) Regular Gate A20 Operation
Output of the Gate A20 signal can be controlled by an H'D1 command and data. When the slave (this LSI) receives data, it normally reads IDR1 in the interrupt handling routine activated by the IBFI1 interrupt. At this time, firmware copies bit 1 of data following an H'D1 command and outputs it on pin GA20. (2) Fast Gate A20 Operation
The internal state of pin GA20 is initialized to 1 since the initial value of the FGA20E bit is 0. When the FGA20E bit is set to 1, pin P81/GA20 functions as the output of the fast GA20 signal. The state of pin GA20 can be monitored by reading bit GA20 in HICR2. The initial output from this pin is 1, which is the initial value. Afterward, the host can manipulate the output from this pin by sending commands and data. This function is only available via the IDR1. The LPC decodes commands input from the host. When an H'D1 host command is detected, bit 1 of the data following the host command is output from pin GA20. This operation does not depend on firmware or interrupts, and is faster than the regular processing using interrupts. Table 19.6 shows the conditions that set and clear pin GA20. Figure 19.8 shows the GA20 output flow. Table 19.7 indicates the GA20 output signal values. Table 19.6 GA20 Setting/Clearing Timing
Pin Name GA20 Setting Condition When bit 1 of the data that follows an H'D1 host command is 1 Clearing Condition When bit 1 of the data that follows an H'D1 host command is 0
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Section 19 LPC Interface (LPC)
Start
Host write
No
H'D1 command received? Yes
Wait for next byte
Host write
No
Data byte?
Yes Write bit 1 of data byte to the bit of GA20 in DR
Figure 19.8 GA20 Output
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Section 19 LPC Interface (LPC)
Table 19.7 Fast Gate A20 Output Signals
Internal CPU Interrupt Flag (IBF) 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 0 0 GA20 (P81) Q 1 Q (1) Q 0 Q (0) Q 1 Q (1) Q 0 Q (0) Q Q Q Q Q 1/0 Q (1/0) Consecutively executed sequences Retriggered sequence Cancelled sequence Turn-off sequence (abbreviated form) Turn-on sequence (abbreviated form) Turn-off sequence
C/D1 Data/Command 1 0 1 1 0 1 1 0 1/0 1 0 1/0 1 1 1 1 1 0 1 H'D1 command 1 data*
1
Remarks Turn-on sequence
H'FF command H'D1 command 0 data*
2
H'FF command H'D1 command 1 data*
1
Command other than H'FF and H'D1 H'D1 command 0 data*
2
Command other than H'FF and H'D1 H'D1 command Command other than H'D1 H'D1 command H'D1 command H'D1 command Any data H'D1 command
Notes: 1. Any data with bit 1 set to 1. 2. Any data with bit 1 cleared to 0.
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Section 19 LPC Interface (LPC)
19.4.6
LPC Interface Shutdown Function (LPCPD)
The LPC interface can be placed in the shutdown state according to the state of the LPCPD pin. There are two kinds of LPC interface shutdown state: LPC hardware shutdown and LPC software shutdown. The LPC hardware shutdown state is controlled by the LPCPD pin, while the LPC software shutdown state is controlled by the SDWNB bit. In both states, the LPC interface enters the reset state by itself, and is no longer affected by external signals other than the LRESET and LPCPD signals. Placing the slave in sleep mode or software standby mode is effective in reducing current dissipation in the shutdown state. If software standby mode is set, some means must be provided for exiting software standby mode before clearing the shutdown state with the LPCPD signal. If the SDWNE bit has been set to 1 beforehand, the LPC hardware shutdown state is entered at the same time as the LPCPD signal falls, and prior preparation is not possible. If the LPC software shutdown state is set by means of the SDWNB bit, on the other hand, the LPC software shutdown state cannot be cleared at the same time as the rising edge of the LPCPD signal. Taking these points into consideration, the following operating procedure uses a combination of LPC software shutdown and LPC hardware shutdown. 1. Clear the SDWNE bit to 0. 2. Set the ERRIE bit to 1 and wait for an interrupt by the SDWN flag. 3. When an ERRI interrupt is generated by the SDWN flag, check the LPC interface internal status flags and perform any necessary processing. 4. Set the SDWNB bit to 1 to set LPC software standby mode. 5. Set the SDWNE bit to 1 and make a transition to LPC hardware standby mode. The SDWNB bit is cleared automatically. 6. Check the state of the LPCPD signal to make sure that the LPCPD signal has not risen during steps 3 to 5. If the signal has risen, clear SDWNE to 0 to return to the state in step 1. 7. If software standby mode has been set, exit software standby mode by some means independent of the LPC. 8. When a rising edge is detected in the LPCPD signal, the SDWNE bit is automatically cleared to 0. If the slave has been placed in sleep mode, the mode is exited by means of LRESET signal input, on completion of the LPC transfer cycle, or by some other means.
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Section 19 LPC Interface (LPC)
Table 19.8 shows the scope of the LPC interface pin shutdown. Table 19.8 Scope of LPC Interface Pin Shutdown
Abbreviation LAD3 to LAD0 LFRAME LRESET LCLK SERIRQ LSCI LSMI PME GA20 CLKRUN LPCPD Port PE3 to P30 PE4 PE5 PE6 PE7 PD0 PD1 PD2 PD3 PD4 PD5 Scope of Shutdown O O X O O O X I/O I/O Input Input Input I/O I/O I/O I/O I/O Input Input Notes Hi-Z Hi-Z LPC hardware reset function is active Hi-Z Hi-Z Hi-Z, only when LSCIE = 1 Hi-Z, only when LSMIE = 1 Hi-Z, only when PMEE = 1 Hi-Z, only when FGA20E = 1 Hi-Z Needed to clear shutdown state
[Legend] O: Pin that is shutdown by the shutdown function : Pin that is shutdown only when the LPC function is selected by register setting X: Pin that is not shutdown
In the LPC shutdown state, the LPC's internal state and some register bits are initialized. The order of priority of LPC shutdown and reset states is as follows. 1. System reset (reset by RES pin input, or WDT0 overflow) All register bits, including bits LPC4E to LPC1E, are initialized. 2. LPC hardware reset (reset by LRESET pin input) LRSTB, SDWNE, and SDWNB bits are cleared to 0. 3. LPC software reset (reset by LRSTB) SDWNE and SDWNB bits are cleared to 0. 4. LPC hardware shutdown SDWNB bit is cleared to 0. 5. LPC software shutdown The scope of the initialization in each mode is shown in table 19.9.
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Section 19 LPC Interface (LPC)
Table 19.9 Scope of Initialization in Each LPC interface Mode
Items Initialized LPC transfer cycle sequencer (internal state), LPCBSY and ABRT flags SERIRQ transfer cycle sequencer (internal state), CLKREQ and IRQBSY flags System Reset Initialized Initialized LPC Reset Initialized Initialized Initialized LPC Shutdown Initialized Initialized Retained
Initialized LPC interface flags (IBF1, IBF2, IBF3A, IBF3B, MWMF, C/D1, C/D2, C/D3, OBF1, OBF2, OBF3A, OBF3B, SWMF, DBU, SMICFLG, SMICIR0, BTSR0, BTSR1, BTIMSR, BTFVSR0, BTFVSR1), GA20 (internal state) Initialized Host interrupt enable bits (IRQ1E1, IRQ12E1, SMIE2, IRQ6E2, IRQ9E2 to IRQ11E2, SMIE3B, SMIE3A, IRQ6E3, IRQ9E3 to IRQ11E3, SELREQ, IEDIR2 to IEDIR3), Q/C flag LRST flag SDWN flag LRSTB bit SDWNB bit SDWNE bit LPC interface operation control bits (LPC3E to LPC1E, FGA20E, LADR1 to LADR3, IBFIE1 to IBFIE3, PMEE, PMEB, LSMIE, LSMIB, LSCIE, LSCIB, TWRE, SELSTR3, SELIRQ1, SELSMI, SELIRQ3 to SELIRQ15, HICR4, HICR5, SCIFAR, HISEL, BTCSR0, BTCSR1) LRESET signal LPCPD signal LAD3 to LAD0, LFRAME, LCLK, SERIRQ, CLKRUN signals PME, LSMI, LSCI, GA20 signals (when function is selected) PME, LSMI, LSCI, GA20 signals (when function is not selected)
Initialized
Retained
Initialized (0) Can be set/cleared
Can be set/cleared
Initialized (0) Initialized (0) Can be set/cleared Initialized (0) HR: 0 SR: 1 0 (can be set)
Initialized (0) Initialized (0) HS: 0 SS: 1 Initialized (0) Initialized (0) HS: 1 SS: 0 or 1 Initialized Retained Retained
Input (port function
Input Input Input Output
Input Input Hi-Z Hi-Z
Port function Port function
Note: System reset: Reset by STBY input, RES input, or WDT overflow LPC reset: Reset by LPC hardware reset (HR) or LPC software reset (SR) LPC shutdown: Reset by LPC hardware shutdown (HS) or LPC software shutdown (SS)
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Section 19 LPC Interface (LPC)
Figure 19.9 shows the timing of the LPCPD and LRESET signals.
LCLK LPCPD
LAD3 to LAD0 LFRAME
At least 30 s
At least 100 s
At least 60 s
LRESET
Figure 19.9 Power-Down State Termination Timing
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Section 19 LPC Interface (LPC)
19.4.7
LPC Interface Serialized Interrupt Operation (SERIRQ)
A host interrupt request can be issued from the LPC interface by means of the SERIRQ pin. In a host interrupt request via the SERIRQ pin, LCLK cycles are counted from the start frame of the serialized interrupt transfer cycle generated by the host or a peripheral function, and a request signal is generated by the frame corresponding to that interrupt. The timing is shown in figure 19.10.
SL or H
Start frame
H R T
IRQ0 frame
S R T
IRQ1 frame
S R T
IRQ2 frame S R T
LCLK SERIRQ Drive source IRQ1 START Host controller None IRQ1 None
H = Host control, SL = Slave control, R = Recovery, T = Turnaround, S = Sample
IRQ14 frame
S R T
IRQ15 frame S R T
IOCHCK frame
S R T I
Stop frame
H R T
Next cycle
LCLK SERIRQ Driver None IRQ15 None STOP Host controller START
H = Host control, R = Recovery, T = Turnaround, S = Sample, I = Idle
Figure 19.10 SERIRQ Timing
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Section 19 LPC Interface (LPC)
The serialized interrupt transfer cycle frame configuration is as follows. Two of the states comprising each frame are the recover state in which the SERIRQ signal is returned to the 1-level at the end of the frame, and the turnaround state in which the SERIRQ signal is not driven. The recover state must be driven by the host or slave that was driving the preceding state. Table 19.10 Serialized Interrupt Transfer Cycle Frame Configuration
Serial Interrupt Transfer Cycle Frame Count 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Contents Start IRQ0 IRQ1 SMI IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 IOCHCK Stop Drive Source Slave Host Slave Slave Slave Slave Slave Slave Slave Slave Slave Slave Slave Slave Slave Slave Slave Slave Slave Host Number of States 6 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 Undefined Notes In quiet mode only, slave drive possible in the first state, then next 3 states 0-driven by host Drive impossible Drive possible in LPC channel 1 and SCIF Drive possible in LPC channels 2, 3, and SCIF Drive possible in SCIF or by IRQ3E Drive possible in SCIF or by IRQ4E Drive possible in SCIF or by IRQ5E Drive possible in LPC channels 2, 3, and SCIF Drive possible in SCIF or by IRQ7E Drive possible in SCIF or by IRQ8E Drive possible in LPC channels 2, 3, and SCIF Drive possible in LPC channels 2, 3, and SCIF Drive possible in LPC channels 2, 3, and SCIF Drive possible in LPC channel 1 and SCIF Drive possible in SCIF or by IRQ13E Drive possible in SCIF or by IRQ14E Drive possible in SCIF or by IRQ15E Drive impossible First, 1 or more idle states, then 2 or 3 states 0-driven by host 2 states: Quiet mode next 3 states: Continuous mode next
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Section 19 LPC Interface (LPC)
There are two modescontinuous mode and quiet modefor serialized interrupts. The mode initiated in the next transfer cycle is selected by the stop frame of the serialized interrupt transfer cycle that ended before that cycle. In continuous mode, the host initiates host interrupt transfer cycles at regular intervals. In quiet mode, the slave with interrupt sources requiring a request can also initiate an interrupt transfer cycle, in addition to the host. In quiet mode, since the host does not necessarily initiate interrupt transfer cycles, it is possible to suspend the clock (LCLK) supply and enter the power-down state. In order for a slave to transfer an interrupt request in this case, a request to restart the clock must first be issued to the host. 19.4.8 LPC Interface Clock Start Request
A request to restart the clock (LCLK) can be sent to the host by means of the CLKRUN pin. With LPC data transfer and SERIRQ in continuous mode, a clock restart is never requested since the transfer cycles are initiated by the host. With SERIRQ in quiet mode, when a host interrupt request is generated the CLKRUN signal is driven and a clock (LCLK) restart request is sent to the host. The timing for this operation is shown in figure 19.11.
LCLK
1 2 3 4 5 6
CLKRUN
Pull-up enable
Driven by the slave processor
Driven by the host processor
Figure 19.11 Clock Start Request Timing Cases other than SERIRQ in quiet mode when clock restart is required must be handled with a different protocol, using the PME signal, etc. 19.4.9 SCIF Control from LPC Interface
Setting the SCIFE bit in HICR5 to 1 allows the LPC host to communicate with the SCIF. Then, the LPC interface can access the registers of the module SCIF other than SCIFCR. For details on transmission and reception, see section 15, Serial Communication Interface with FIFO (SCIF).
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Section 19 LPC Interface (LPC)
19.5
19.5.1
Interrupt Sources
IBFI1, IBFI2, IBFI3, and ERRI
The host has four interrupt requests for the slave (this LSI): IBF1, IBF2, IBF3, and ERRI. IBFI1, IBFI2, and IBFI3 are IDR receive complete interrupts for IDR1, IDR2, and IDR3 and TWR, respectively. IBFI3 is also used for SMIC mode and BT mode interrupt requests. The ERRI interrupt indicates the occurrence of a special state such as an LPC reset, LPC shutdown, or transfer cycle abort. The LMCI and LMCUI interrupts are command receive complete interrupts. Table 19.11 Receive Complete Interrupts and Error Interrupt
Interrupt IBFI1 IBFI2 IBFI3 ERRI Description When IBFIE1 is set to 1 and IDR1 reception is completed When IBFIE2 is set to 1 and IDR2 reception is completed When IBFIE3 is set to 1 and IDR3 reception is completed, or when TWRE and IBFIE3 are set to 1 and reception is completed up to TWR15 When ERRIE is set to 1 and one of LRST, SDWN and ABRT is set to 1
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Section 19 LPC Interface (LPC)
19.5.2
SMI, HIRQ1, HIRQ3, HIRQ4, HIRQ5, HIRQ6, HIRQ7, HIRQ8, HIRQ9, HIRQ10, HIRQ11, HIRQ12, HIRQ13, HIRQ14, and HIRQ15
The LPC interface can request 15 kinds of host interrupt by means of SERIRQ. HIRQ1 and HIRQ12 are used on LPC channel 1, while SMI, HIRQ6, HIRQ9, HIRQ10, and HIRQ11 can be requested from LPC channels 2 and 3. For the SCIF, any one of 15 types of interrupts can be selected. In addition, by the setting of SCIFCR4, the SCIF can request eight types of host interrupts: HIRQ3, HIRQ4, HIRQ5, HIRQ7, HIRQ8, HIRQ13, HIRQ14, and HIRQ15. There are two ways of clearing a host interrupt request when the LPC channels are used. When the IEDIR bit in SIRQCR0is cleared to 0, host interrupt sources and LPC channels are all linked to the host interrupt request enable bits. When the OBF flag is cleared to 0 by a read of ODR or TWR15 by the host in the corresponding LPC channel, the corresponding host interrupt enable bit is automatically cleared to 0, and the host interrupt request is cleared. When the IEDIR bit is set to 1 in SIRQCR, a host interrupt is only requested by the host interrupt enable bits. The host interrupt enable bit is not cleared when OBF is cleared. Therefore, SMIE2, SMIE3A, SMIE3B, SMIE4 and IRQ6En, IRQ9En, IRQ10En, IRQ11En lose their respective functional differences (n = 2, 3). In order to clear a host interrupt request, it is necessary to clear the host interrupt enable bit. As for HIRQ3 to HIRQ5, HIRQ7, HIRQ8, and HIRQ13 to HIRQ15, setting the enable bit in SIRQCR4 to 1 requests the corresponding host interrupt, and clearing the enable bit to 0 clears the corresponding host interrupt request. When the SCIF channels are used, a host interrupt request is cleared when the relevant SCIF interrupt is cleared. Table 19.12 summarizes the methods of setting and clearing these bits when the LPC channels are used, and table 19.13 summarizes the methods of setting and clearing these bits when the SCIF channels are used. Figure 19.12 shows the processing flowchart.
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Section 19 LPC Interface (LPC)
Table 19.12 HIRQ Setting and Clearing Conditions when LPC Channels are Used
Host Interrupt HIRQ1 HIRQ12 SMI (IEDIR2 = 0 or IEDIR3 = 0) Setting Condition Clearing Condition
Internal CPU writes to ODR1, then reads 0 Internal CPU writes 0 to bit IRQ1E1, from bit IRQ1E1 and writes 1 or host reads ODR1 Internal CPU writes to ODR1, then reads 0 Internal CPU writes 0 to bit from bit IRQ12E1 and writes 1 IRQ12E1, or host reads ODR1 Internal CPU * * * writes to ODR2, then reads 0 from bit SMIE2 and writes 1 writes to ODR3, then reads 0 from bit SMIE3A and writes 1 Internal CPU * * writes 0 to bit SMIE2, or host reads ODR2 writes 0 to bit SMIE3A, or host reads ODR3 writes 0 to bit SMIE3B, or host reads TWR15 writes 0 to bit SMIE2 writes 0 to bit SMIE3A writes 0 to bit SMIE3B writes 0 to bit IRQiE2, or host reads ODR2 writes 0 to bit IRQiE3, or host reads ODR3 writes 0 to bit IRQiE2 writes 0 to bit IRQiE3
writes to TWR15, then reads 0 from bit * SMIE3B and writes 1 reads 0 from bit SMIE2, then writes 1 *
SMI (IEDIR2 = 1 or IEDIR3 = 1)
Internal CPU * * *
Internal CPU
reads 0 from bit SMIE3A, then writes 1 * reads 0 from bit SMIE3B, then writes 1 * * *
HIRQi Internal CPU (i = 6, 9, 10, 11) * writes to ODR2, then reads 0 from bit (IEDIR2 = 0 or IRQiE2 and writes 1 IEDIR3 = 0) * writes to ODR3, then reads 0 from bit IRQiE3 and writes 1 HIRQi Internal CPU (i = 6, 9, 10, 11) * reads 0 from bit IRQiE2, then writes 1 (IEDIR2 = 1 or * reads 0 from bit IRQiE3, then writes 1 IEDIR3 = 1)
Internal CPU
Internal CPU * *
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Section 19 LPC Interface (LPC)
Table 19.13 HIRQ Setting and Clearing Conditions when SCIF Channels are Used
Host Interrupt SMI HIRQi (i = 1, 3 to 15) Setting Condition The SCIF interrupt corresponding to the host interrupt request selected by SIRQCR3 occurs. Clearing Condition Relevant SCIF interrupt is cleared
Slave CPU
Master CPU
ODR1 write
Write 1 to IRQ1E1
SERIRQ IRQ1 output SERIRQ IRQ1 source clear
Interrupt initiation ODR1 read
OBF1 = 0? No Yes All bytes transferred? Hardware operation Yes Software operation
No
Figure 19.12 HIRQ Flowchart (Example of Channel 1)
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Section 19 LPC Interface (LPC)
19.6
19.6.1
Usage Note
Data Conflict
The LPC interface provides buffering of asynchronous data from the host and slave (this LSI), but an interface protocol that uses the flags in STR must be followed to avoid data conflict. For example, if the host and slave both try to access IDR or ODR at the same time, the data will be corrupted. To prevent simultaneous accesses, IBF and OBF must be used to allow access only to data for which writing has finished. Unlike the IDR and ODR registers, the transfer direction is not fixed for the bidirectional data registers (TWR). MWMF and SWMF are provided in STR to handle this situation. After writing to TWR0, MWMF and SWMF must be used to confirm that the write authority for TWR1 to TWR15 has been obtained. Table 19.14 shows host address examples for LADR3 and registers, IDR3, ODR3, STR3, TWR0MW, TWR0SW, and TWR1 to TWR15.
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Section 19 LPC Interface (LPC)
Table 19.14 Host Address Example
Register IDR3 ODR3 STR3 TWR0MW TWR0SW TWR1 TWR2 TWR3 TWR4 TWR5 TWR6 TWR7 TWR8 TWR9 TWR10 TWR11 TWR12 TWR13 TWR14 TWR15 Host Address when LADR3 = H'A24F Host Address when LADR3 = H'3FD0 H'A24A and H'A24E H'A24A H'A24E H'A250 H'A250 H'A251 H'A252 H'A253 H'A254 H'A255 H'A256 H'A257 H'A258 H'A259 H'A25A H'A25B H'A25C H'A25D H'A25E H'A25F H'3FD0 and H'3FD4 H'3FD0 H'3FD4 H'3FC0 H'3FC0 H'3FC1 H'3FC2 H'3FC3 H'3FC4 H'3FC5 H'3FC6 H'3FC7 H'3FC8 H'3FC9 H'3FCA H'3FCB H'3FCC H'3FCD H'3FCE H'3FCF
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Section 19 LPC Interface (LPC)
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Section 20 Ethernet Controller (EtherC)
Section 20 Ethernet Controller (EtherC)
This LSI has an on-chip Ethernet controller (EtherC) conforming to the Ethernet or the IEEE802.3 MAC (Media Access Control) layer standard. Connecting a physical-layer LSI (PHY-LSI) complying with this standard enables the Ethernet controller (EtherC) to perform transmission and reception of Ethernet/IEEE802.3 frames. This LSI has one MAC layer interface. The Ethernet controller is connected to the direct memory access controller for Ethernet controller (E-DMAC) inside this LSI, and carries out high-speed data transfer to and from the memory.
20.1
Features
* Transmission and reception of Ethernet/IEEE802.3 frames * Supports 10/100 Mbps receive/transfer * Supports full-duplex and half-duplex modes * Conforms to IEEE802.3u standard RMII (Reduced Media Independent Interface) * Magic Packet detection and Wake-On-LAN (WOL) signal output * Conforms to IEEE802.3x flow control Note: The EtherC operates only in high-speed mode. Figure 20.1 shows the configuration of the EtherC.
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Section 20 Ethernet Controller (EtherC)
CPU EtherC
Bus interface
MAC
Receive controller Transmit controller
Command status interface
MII
Converter
MII/RMII conversion
PORT PHY
Figure 20.1 Configuration of EtherC
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Section 20 Ethernet Controller (EtherC)
20.2
Input/Output Pins
Table 20.1 lists the pin configuration of the EtherC. Table 20.1 Pin Configuration
Type RMII interface signals Abbreviation RM_REF-CLK I/O Input Function Transmit/Receive Clock Timing reference signal for the RM_TX-EN, RM_TXD1 to RM_TXD0, RM_CRS-DV, RM_RXD1 to RM_RXD0, and RM_RX-ER signals RM_TX-EN Output Transmit Enable Indicates that transmit data is ready on pins RM_TXD1 and RM_TXD0. RM_TXD1 RM_TXD0 RM_CRS-DV Output Input Transmit Data 2-bit transmit data Carrier Detection/Receive Data Valid Carrier detection signal/Signal that indicates that valid receive data is on pins RM_RXD1 and RM_RXD0. RM_RXD1 RM_RXD0 RM_RX-ER PHY register interface signals MDC MDIO Input Input Output Input/ Output Receive Data 2-bit receive data Receive Error Indicates the error state during data reception. Management Data Clock Reference clock signal for information transfer via MDIO Management Data I/O Bidirectional signal for exchange of management information between the station management entity (STA) and physical layer (PHY) Link Status Inputs link status from PHY-LSI WOL EXOUT Output Output Wake-On-LAN Signal indicating reception of Magic Packet External Output
Others
LNKSTA
Input
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Section 20 Ethernet Controller (EtherC)
20.3
Register Description
The EtherC has the following registers. For details on addresses and access sizes of registers, see section 29, List of Registers. MAC Layer Interface Control Register * EtherC mode register (ECMR) * EtherC status register (ECSR) * EtherC interrupt permission register (ECSIPR) * PHY interface register (PIR) * MAC address high register (MAHR) * MAC address low register (MALR) * Receive frame length register (RFLR) * PHY status register (PSR) * Transmit retry over counter register (TROCR) * Delayed collision detect counter register (CDCR) * Lost carrier counter register (LCCR) * Carrier not detect counter register (CNDCR) * CRC error frame counter register (CEFCR) * Frame receive error counter register (FRECR) * Too-short frame receive counter register (TSFRCR) * Too-long frame receive counter register (TLFRCR) * Residual-bit frame counter register (RFCR) * Multicast address frame counter register (MAFCR) * IPG register (IPGR) * Automatic PAUSE frame set register (APR) * Manual PAUSE frame set register (MPR) * Automatic PAUSE frame retransmission count set register (TPAUSER)
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Section 20 Ethernet Controller (EtherC)
20.3.1
EtherC Mode Register (ECMR)
ECMR is a 32-bit readable/writable register and specifies the operating mode of the Ethernet controller. The settings in this register are normally made in the initialization process following a reset. The operating mode setting must not be changed while the transmitting and receiving functions are enabled. To switch the operating mode, return the EtherC and E-DMAC to their initial states by means of the SWR bit in EDMR before making settings again.
Bit 31 to 20 Initial Bit Name Value All 0 R/W R Description Reserved These bits are always read as 0. The initial value should not be changed. 19 ZPF 0 R/W 0-Time PAUSE Frame Use Enable 0: Disables PAUSE frame control in which the TIME parameter is 0. The next frame is transmitted after the time indicated by the Timer value has elapsed. When the EtherC receives a PAUSE frame with the time indicated by the Timer value set to 0, the PAUSE frame is discarded. 1: Enables PAUSE frame control in which the TIME parameter is 0. A PAUSE frame with the Timer value set to 0 is transmitted when the number of data in the receive FIFO is less than the FCFTR value before the time indicated by the Timer value has not elapsed. When the EtherC receives a PAUSE frame with the time indicated by the Timer value set to 0, the transmit wait state is canceled. 18 PFR 0 R/W PAUSE Frame Receive Mode 0: PAUSE frame is not transferred to the E-DMAC 1: PAUSE frame is transferred to the E-DMAC 17 RXF 0 R/W Receive Flow Control Operating Mode 0: PAUSE frame detection function is disabled 1: Receive flow control function is enabled
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Section 20 Ethernet Controller (EtherC)
Bit 16
Initial Bit Name Value TXF 0
R/W R/W
Description Transmit Flow Control Operating mode 0: Transmit flow control function is disabled (automatic PAUSE frames are not transmitted) 1: Transmit flow control function is enabled (automatic PAUSE frame is transmitted as necessary)
15 to 13
All 0
R
Reserved These bits are always read as 0. The initial value should not be changed.
12
PRCEF
0
R/W
Permit Receive CRC Error Frame 0: A frame with a CRC error is received as a frame with an error. 1: A frame with a CRC error is received as a frame without an error. The CEFCR register is therefore not incremented. If this bit is clear and a frame with an error is received, a CRC error is reflected in ECSR of the E-DMAC and the status of the receive descriptor. If this bit is set to 1, a frame with an error is received as a normal frame.
11, 10
All 0
R
Reserved These bits are always read as 0. The initial value should not be changed.
9
MPDE
0
R/W
Magic Packet Detection Enable Enables or disables Magic Packet detection by hardware to allow activation from the Ethernet. 0: Magic Packet detection is not enabled 1: Magic Packet detection is enabled
8, 7
All 0
R
Reserved These bits are always read as 0. The initial value should not be changed.
6
RE
0
R/W
Reception Enable 0: Receive function is disabled 1: Receive function is enabled If this bit is changed from enabling to disabling while a frame is being received, the receive function remains enabled until reception of the frame is completed.
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Section 20 Ethernet Controller (EtherC)
Bit 5
Initial Bit Name Value TE 0
R/W R/W
Description Transmission Enable 0: Transmit function is disabled 1: Transmit function is enabled If this bit is changed from enabling to disabling while a frame is being transmitted, the transmit function remains enabled until transmission of the frame is completed.
4
0
R
Reserved This bit is always read as 0. The initial value should not be changed.
3
ILB
0
R/W
Internal Loop Back Mode Specifies loopback mode in the EtherC. 0: Normal data transmission/reception is performed. 1: When DM = 1, data loopback is performed inside the MAC in the EtherC.
2
0
R
Reserved This bit is always read as 0. The initial value should not be changed.
1
DM
0
R/W
Duplex Mode Specifies the EtherC transfer method. 0: Half-duplex transfer is specified 1: Full-duplex transfer is specified
0
PRM
0
R/W
Promiscuous Mode Setting this bit enables all Ethernet frames to be received. All Ethernet frames means all receivable frames, irrespective of differences in or presence/absence of the destination address, broadcast address, multicast bit, etc. 0: EtherC performs normal operation 1: EtherC performs promiscuous mode operation
Note: Bits other than TE and RE should be rewritten while both transmission and reception are disabled (TE = 0 and also RE =0).
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Section 20 Ethernet Controller (EtherC)
20.3.2
EtherC Status Register (ECSR)
ECSR is a 32-bit readable/writable register and indicates the status in the EtherC. This status can be notified to the CPU by interrupts. When 1 is written to the PSRTO, LCHNG, MPD, and ICD, the corresponding flags can be cleared. Writing 0 does not affect the flag. For bits that generate interrupt, the interrupt can be enabled or disabled according to the corresponding bit in ECSIPR. The interrupts generated due to this status register are indicated in the ECI bit in EESR.
Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The initial value should not be changed. 4 PSRTO 0 R/W PAUSE Frame Retransmission Retry Over Indicates that during the retransmission of PAUSE frames when the flow control is enabled, the number of retries has exceeded the upper limit set in the automatic PAUSE frame retransmission count set register (TPAUSER). 0: Number of PAUSE frame retransmissions has not exceeded the upper limit 1: Number of PAUSE frame retransmissions has exceeded the upper limit 3 0 R Reserved This bit is always read as 0. The initial value should not be changed. 2 LCHNG 0 R/W Link Signal Change Indicates that the LNKSTA signal input from the PHY has changed from high to low or low to high. To check the current Link state, refer to the LMON bit in the PHY status register (PSR). 0: Changes in the LNKSTA signal are not detected 1: Changes in the LNKSTA signal are detected (high to low or low to high)
31 to 5
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Section 20 Ethernet Controller (EtherC)
Bit 1
Bit Name MPD
Initial Value 0
R/W R/W
Description Magic Packet Detection Indicates that a Magic Packet has been detected on the line. 0: Magic Packet has not been detected 1: Magic Packet has been detected
0
ICD
0
R/W
Illegal Carrier Detection Indicates that the PHY has detected an illegal carrier on the line. If a change in the signal input from the PHY occurs before the software recognition period, the correct information may not be obtained. Refer to the timing specification for the PHY used. 0: LSI has not detected an illegal carrier on the line 1: LSI has detected an illegal carrier on the line
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Section 20 Ethernet Controller (EtherC)
20.3.3
EtherC Interrupt Permission Register (ECSIPR)
ECSIPR is a 32-bit readable/writable register that enables or disables the interrupt sources indicated by ECSR. Each bit can disable or enable interrupts corresponding to the bits in ECSR.
Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The initial value should not be changed. 4 PSRTOIP 0 R/W PAUSE Frame Retransmission Retry Over Interrupt Enable 0: Interrupt notification by the PSRTO bit is disabled 1: Interrupt notification by the PSRTO bit is enabled 3 0 R Reserved This bit is always read as 0. The initial value should not be changed. 2 LCHNGIP 0 R/W LINK Signal Changed Interrupt Enable 0: Interrupt notification by the LCHNG bit is disabled 1: Interrupt notification by the LCHNG bit is enabled 1 MPDIP 0 R/W Magic Packet Detection Interrupt Enable 0: Interrupt notification by the MPD bit is disabled 1: Interrupt notification by the MPD bit is enabled 0 ICDIP 0 R/W Illegal Carrier Detection Interrupt Enable 0: Interrupt notification by the ICD bit is disabled 1: Interrupt notification by the ICD bit is enabled
31 to 5
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Section 20 Ethernet Controller (EtherC)
20.3.4
PHY Interface Register (PIR)
PIR is a 32-bit readable/writable register that provides a means of accessing the PHY registers via the RMII.
Bit Bit Name Initial Value All 0 R/W Description R Reserved These bits are always read as 0. The initial value should not be changed. 3 2 MDI MDO Undefined R 0 MII Management Data-In Indicates the level of the MDIO pin. R/W MII Management Data-Out Outputs the value set to this bit from the MDIO pin, when the MMD bit is 1. 1 MMD 0 R/W MII Management Mode Specifies the data read/write direction with respect to the MII. 0: Read direction is indicated 1: Write direction is indicated 0 MDC 0 R/W MII Management Data Clock Outputs the value set to this bit from the MDC pin and supplies the MII with the management data clock. For the method of accessing the MII registers, see section 20.4.4, Accessing MII Registers.
31 to 4
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Section 20 Ethernet Controller (EtherC)
20.3.5
MAC Address High Register (MAHR)
MAHR is a 32 -bit readable/writable register that specifies the upper 32 bits of the 48-bit MAC address. The settings in this register are normally made in the initialization process after a reset. The MAC address setting must not be changed while the transmitting and receiving functions are enabled. To switch the MAC address setting, return the EtherC and E-DMAC to their initial states by means of the SWR bit in EDMR before making settings again.
Bit Bit Name Initial Value R/W R/W Description MAC Address Bits These bits are used to set the upper 32 bits of the MAC address. If the MAC address is 01-23-45-67-89-AB (hexadecimal), the value set in this register is H'01234567.
31 to 0 MA47 to MA16 All 0
20.3.6
MAC Address Low Register (MALR)
MALR is a 32-bit readable/writable register that specifies the lower 16 bits of the 48-bit MAC address. The settings in this register are normally made in the initialization process after a reset. The MAC address setting must not be changed while the transmitting and receiving functions are enabled. To switch the MAC address setting, return the EtherC and E-DMAC to their initial states by means of the SWR bit in EDMR before making settings again.
Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The initial value should not be changed. 15 to 0 MA15 to MA0 All 0 R/W MAC Address Bits 15 to 0 These bits are used to set the lower 16 bits of the MAC address. If the MAC address is 01-23-45-67-89-AB (hexadecimal), the value set in this register is H'000089AB.
31 to 16
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Section 20 Ethernet Controller (EtherC)
20.3.7
Receive Frame Length Register (RFLR)
RFLR is a 32-bit readable/writable register and it specifies the maximum frame length (in bytes) that can be received by this LSI. The settings in this register must not be changed while the receiving function is enabled.
Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The initial value should not be changed. 11 to 0 RFL11 to RFL0 All 0 R/W Receive Frame Length 11 to 0 The frame length described here refers to all fields from the destination address up to and including the CRC data. Frame contents from the destination address up to and including the data are actually transferred to memory. CRC data is not included in the transfer. When data that exceeds the specified value is received, the part of the data that exceeds the specified value is discarded. H'000 to H'5EE: 1,518 bytes H'5EF: 1,519 bytes H'5F0: 1,520 bytes : : H'7FF: 2,047 bytes H'800 to H'FFF: 2,048 bytes
31 to 12
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Section 20 Ethernet Controller (EtherC)
20.3.8
PHY Status Register (PSR)
PSR is a read-only register that can read interface signals from the PHY.
Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The initial value should not be changed. 0 LMON 0 R LNKSTA Pin Status The Link status can be read by connecting the Link signal output from the PHY to the LNKSTA pin. For the polarity, refer to the PHY specifications to be connected.
31 to 1
20.3.9
Transmit Retry Over Counter Register (TROCR)
TROCR is a 32-bit counter that indicates the number of frames that were unable to be transmitted in 16 transmission attempts including the retransmission. When 16 transmission attempts have failed, TROCR is incremented by 1. When the value in this register reaches H'FFFFFFFF, the count is halted. The counter value is cleared to 0 by a write to this register with any value.
Bit Bit Name Initial Value All 0 R/W R/W Description Transmit Retry Over Count These bits indicate the number of frames that were unable to be transmitted in 16 transmission attempts including retransmission.
31 to 0 TROC31 to TROC0
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Section 20 Ethernet Controller (EtherC)
20.3.10 Delayed Collision Detect Counter Register (CDCR) CDCR is a 32-bit counter that indicates the number of delayed collisions on all lines from a start of transmission. When the value in this register reaches H'FFFFFFFF, count-up is halted. The counter value is cleared to 0 by a write to this register with any value.
Bit Bit Name Initial Value All 0 R/W R/W Description Delayed Collision Detect Count These bits indicate the number of delayed collisions on all lines from a start of transmission.
31 to 0 COSDC31 to COSDC0
20.3.11 Lost Carrier Counter Register (LCCR) LCCR is a 32-bit counter that indicates the number of times the carrier was lost during data transmission. When the value in this register reaches H'FFFFFFFF, the count is halted. The counter value is cleared to 0 by writing to this register with any value.
Bit Bit Name Initial Value All 0 R/W R/W Description Lost Carrier Count These bits indicate the number of times the carrier was lost during data transmission.
31 to 0 LCC31 to LCC0
20.3.12 Carrier Not Detect Counter Register (CNDCR) CNDCR is a 32-bit counter that indicates the number of times the carrier could not be detected while the preamble was being sent. When the value in this register reaches H'FFFFFFFF, the count is halted. The counter value is cleared to 0 by a write to this register with any value.
Bit Bit Name Initial Value All 0 R/W R/W Description Carrier Not Detect Count These bits indicate the number of times the carrier was not detected.
31 to 0 CNDC31 to CNDC0
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Section 20 Ethernet Controller (EtherC)
20.3.13 CRC Error Frame Counter Register (CEFCR) CEFCR is a 32-bit counter that indicates the number of times a frame with a CRC error was received. When the value in this register reaches H'FFFFFFFF, the count is halted. The counter value is cleared to 0 by a write to this register with any value.
Bit Bit Name Initial Value All 0 R/W R/W Description CRC Error Frame Count These bits indicate the count of CRC error frames received.
31 to 0 CEFC31 to CEFC0
20.3.14 Frame Receive Error Counter Register (FRECR) FRECR is a 32-bit counter that indicates the number of frames input from the PHY-LSI for which a receive error was indicated by the RM_RX-ER pin. FRECR is incremented each time the RM_RX-ER pin becomes active. When the value in this register reaches H'FFFFFFFF, the count is halted. The counter value is cleared to 0 by a write to this register with any value.
Bit Bit Name Initial Value All 0 R/W R/W Description Frame Receive Error Count These bits indicate the count of errors during frame reception.
31 to 0 FREC31 to FREC0
20.3.15 Too-Short Frame Receive Counter Register (TSFRCR) TSFRCR is a 32-bit counter that indicates the number of frames of fewer than 64 bytes that have been received. When the value in this register reaches H'FFFFFFFF, the count is halted. The counter value is cleared to 0 by a write to this register with any value.
Bit Bit Name Initial Value All 0 R/W R/W Description Too-Short Frame Receive Count These bits indicate the count of frames received with a length of less than 64 bytes.
31 to 0 TSFC31 to TSFC0
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Section 20 Ethernet Controller (EtherC)
20.3.16 Too-Long Frame Receive Counter Register (TLFRCR) TLFRCR is a 32-bit counter that indicates the number of frames received with a length exceeding the value specified by the receive frame length register (RFLR). When the value in this register reaches H'FFFFFFFF, the count is halted. TLFRCR is not incremented when a frame containing residual bits is received. In this case, the reception of the frame is indicated in the residual-bit frame counter register (RFCR). The counter value is cleared to 0 by a write to this register with any value.
Bit Bit Name Initial Value All 0 R/W R/W Description Too-Long Frame Receive Count These bits indicate the count of frames received with a length exceeding the value in RFLR.
31 to 0 TLFC31 to TLFC0
20.3.17 Residual-Bit Frame Counter Register (RFCR) RFCR is a 32-bit counter that indicates the number of frames received containing residual bits (less than an 8-bit unit). When the value in this register reaches H'FFFFFFFF, the count is halted. The counter value is cleared to 0 by a write to this register with any value.
Bit Bit Name Initial Value All 0 R/W R/W Description Residual-Bit Frame Count These bits indicate the count of frames received containing residual bits.
31 to 0 RFC31 to RFC0
20.3.18 Multicast Address Frame Counter Register (MAFCR) MAFCR is a 32-bit counter that indicates the number of frames received with a specified multicast address. When the value in this register reaches H'FFFFFFFF, the count is halted. The counter value is cleared to 0 by a write to this register with any value.
Bit Bit Name Initial Value All 0 R/W R/W Description Multicast Address Frame Count These bits indicate the count of multicast frames received.
31 to 0 MAFC31 to MAFC0
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Section 20 Ethernet Controller (EtherC)
20.3.19 IPG Register (IPGR) IPGR sets the IPG (Inter Packet Gap). This register must not be changed while the transmitting and receiving functions of the EtherC mode register (ECMR) are enabled. (For details, refer to section 20.4.6, Operation by IPG Setting.)
Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 4 to 0 IPG4 to IPG0 H'13 R/W Inter Packet Gap Sets the IPG value every 4-bit time. H'00: 20-bit time H'01: 24-bit time : : : : H'13: 96-bit time (Initial value) H'1F: 144-bit time
31 to 5
20.3.20 Automatic PAUSE Frame Set Register (APR) APR sets the TIME parameter value of the automatic PAUSE frame. When transmitting the automatic PAUSE frame, the value set in this register is used as the TIME parameter of the PAUSE frame.
Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 15 to 0 AP15 to AP0 All 0 R/W Automatic PAUSE Sets the TIME parameter value of the automatic PAUSE frame. At this time, 1 bit means 512-bit time.
31 to 16
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Section 20 Ethernet Controller (EtherC)
20.3.21 Manual PAUSE Frame Set Register (MPR) MPR sets the TIME parameter value of the manual PAUSE frame. When transmitting the manual PAUSE frame, the value set to this register is used as the TIME parameter of the PAUSE frame.
Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 15 to 0 MP15 to MP0 All 0 R/W Manual PAUSE Sets the TIME parameter value of the manual PAUSE frame. At this time, 1 bit means 512-bit time. Read values are undefined.
31 to 16
20.3.22 Automatic PAUSE Frame Retransmission Count Set Register (TPAUSER) TPAUSER sets the upper limit of the number of times of the PAUSE frame retransmission. TPAUSER must not be changed while the transmitting function is enabled.
Bit 31 to 16 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 15 to 0 TPAUSE15 All 0 to TPAUSE0 R/W Upper Limit of the Number of Times of PAUSE Frame Retransmission H'0000: Unlimited number of times of retransmission H'0001: Retransmit once : : H'FFFF: Number of times of retransmission is 65535
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Section 20 Ethernet Controller (EtherC)
20.4
Operation
The overview of the Ethernet controller (EtherC) are shown below. The EtherC transmits and receives PAUSE frames conforming to the Ethernet/IEEE802.3 frames. 20.4.1 Transmission
In response to a transmit request from the E-DMAC, the EtherC transmitter arranges the transmit data into a frame and outputs to the RMII. The transmit data that has gone through the RMII is output onto the lines by the PHY-LSI. Figure 20.2 shows the state transition of the EtherC transmitter.
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Section 20 Ethernet Controller (EtherC)
TE set Idle
FDPX
Start of transmission (preamble transmission) Carrier not detected Initiate retransmission HDPX FDPX Collision Carrier detection
Transmission halted
HDPX TE reset
Carrier detected
Carrier detection Reset
Retransmission processing*1
Carrier not detected Collision
Failure of 15 retransfer attempts or collision after 512-bit time
SFD transmission Error Collision*2
Error detection Error notification Error
Error
Data transmission
[Legend] FDPX: Path for full-duplex mode HDPX: Path for half-duplex mode SFD: Start Frame Delimiter
Normal transmission
CRC transmission
Notes: 1. Retransmission processing includes both jam transmission that depends on collision detection and the adjustment of transmission intervals based on the back-off algorithm. 2. Retransmission processing is only performed when data of 512 bits or less (including the preamble and SFD) is transmitted. When a collision is detected during transmission of data greater than 512 bits, only jam is transmitted and retransmission based on the back-off algorithm is not performed.
Figure 20.2 EtherC Transmitter State Transitions
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Section 20 Ethernet Controller (EtherC)
1. When the transmit enable (TE) bit is set, the transmitter enters the transmit idle state. 2. When a transmit request is issued by the transmit E-DMAC, the EtherC sends the preamble to RMII after a transmission delay equivalent to the time required by carrier detection and a frame interval time. If full-duplex transfer is selected, which does not require carrier detection, the preamble is sent as soon as a transmit request is issued by the E-DMAC. 3. The transmitter sends the SFD, data, and CRC sequentially. At the end of transmission, the transmit E-DMAC generates a transmission complete interrupt (TC). If a collision or the carrier-not-detected state occurs during data transmission, these are reported as interrupt sources. 4. After waiting for the frame interval time, the transmitter enters the idle state, and if there is more transmit data, continues transmitting.
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Section 20 Ethernet Controller (EtherC)
20.4.2
Reception
The EtherC receiver separates the frame data that inputs from the RMII into preamble, SFD, data, and CRC data, and outputs from D/A (destination address) to CRC data to the E-DMAC. Figure 20.3 shows the state transitions of the EtherC receiver.
Illegal carrier detection RX-DV negation
Idle RE set Preamble detection
Start of frame reception
Wait for SFD reception SFD reception Destination address reception Own destination address or broadcast or multicast or promiscuous Data reception End of reception CRC reception
Reception halted
RE reset Promiscuous and other station destination address
Reset
Error notification*
Error detection
Receive error detection
Receive error detection
Normal reception [Legend] SFD: Start frame delimiter Note: * The error frame also transmits data to the buffer.
Figure 20.3 EtherC Receiver State Transmissions 1. When the receive enable (RE) bit is set, the receiver enters the receive idle state. 2. When an SFD (start frame delimiter) is detected after a receive packet preamble, the receiver starts receive processing. Discards a frame with an invalid pattern. 3. In normal mode, if the destination address matches the receiver's own address, or if broadcast or multicast transmission or promiscuous mode is specified, the receiver starts data reception.
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Section 20 Ethernet Controller (EtherC)
4. Following data reception from the RMII, the receiver carries out a CRC check. The result is indicated as a status bit in the descriptor after the frame data has been written to memory. The error status is reported in the case of an abnormality. 5. After one frame has been received, if the receive enable bit is set (RE = 1) in the EtherC mode register, the receiver prepares to receive the next frame. 20.4.3 (1) RMII Frame Timing
RMII Frame Transmission Timing
Timing of RMII frame transmission is shown in figure 20.4.
RM_REF-CLK
RM_TX-EN
RM_TXD1
0
0
0
0
0
0
0
0
0
0
0
1
A
B
C
D
E
F
G
H
I
J
0
RM_TXD0
1
1
1
1
1
1
1
1
1
1
1
1
A
B
C
D
E
F
G
H
I
J
0
Preamble
SFD
Data
Figure 20.4 RMII Frame Transmit Timing (Normal Transmission) (2) RMII Frame Reception Timing
Timing of RMII frame reception is shown in figures 20.5 and 20.6.
RM_REF-CLK nibble boundary RM_CRS-DV
RM_RXD1
0
0
0
0
0
0
0
0
0
0
0
1
A
B
C
D
E
F
G
H
I
J
0
RM_RXD0
0
0
0
0
0
1
1
1
1
1
1
1
A
B
C
D
E
F
G
H
I
J
0
J
K
Preamble
SFD
Data
Figure 20.5 RMII Frame Receive Timing (Normal Reception)
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Section 20 Ethernet Controller (EtherC)
RM_REF-CLK
RM_CRS-DV
RM_RXD1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
RM_RXD0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
False Carrier detected
Figure 20.6 RMII Frame Receive Timing (Reception with False Carrier)
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Section 20 Ethernet Controller (EtherC)
20.4.4
Accessing MII Registers
MII registers in the PHY are accessed via this LSI's PHY interface register (PIR). Connection is made as a serial interface in accordance with the MII frame format specified in IEEE802.3u. (1) MII Management Frame Format
The format of an MII management frame is shown in figure 20.7. To access an MII register, a management frame is implemented by the program in accordance with the procedures shown in (2) MII Register Access Procedure.
Access Type Item Number of bits Read Write [Legend] PRE: ST: OP: PHYAD: PRE 32 1..1 1..1 ST 2 01 01 OP 2 10 01
MII Management Frame PHYAD 5 00001 00001 REGAD 5 RRRRR RRRRR TA 2 Z0 10 DATA 16 D..D D..D IDLE X
32 consecutive 1s Write of 01 indicating start of frame Write of code indicating access type Write of 0001 if the PHY address is 1 (sequential write starting with the MSB). This bit changes depending on the PHY address. REGAD: Write of 0001 if the register address is 1 (sequential write starting with the MSB). This bit changes depending on the PHY register address. TA: Time for switching data transmission source on MII interface (a) Read: Bus is released (indicated as Z0). (b) Write: B'10 is written. DATA: 16-bit data. Sequential write or read from MSB (a) Read: 16-bit data read (b) Write: 16-bit data write IDLE: Wait time until next MII management format input (a) Read: Since the bus has been relased at TA already, control is not required. (b) Write: Independent bus release (indicated as X) is performed.
Figure 20.7 MII Management Frame Format
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Section 20 Ethernet Controller (EtherC)
(2)
MII Register Access Procedure
The program accesses MII registers via the PHY interface register (PIR). Access is implemented by a combination of 1-bit-unit data write, 1-bit-unit data read, bus release, and independent bus release. Figures 20.8 to 20.11 show examples of MII register access timing. The timing will differ depending on the type of PHY-LSI.
(1) Write to PHY interface register MMD = 1 MDO = write data MDC = 0 (2) Write to PHY interface register MMD = 1 MDO = write data MDC = 1 (3) Write to PHY interface register MMD = 1 MDO = write data MDC = 0
MDC
MDO
(1) (2)
(3)
Figure 20.8 1-Bit Data Write Flowchart
(1)
Write to PHY interface register MMD = 0 MDC = 0 Write to PHY interface register MMD = 0 MDC = 1 Write to PHY interface register MMD = 0 MDC = 0
MDC
(2)
MDO
(3)
(1)
(2)
(3)
Figure 20.9 Bus Release Flowchart (TA in Read in Figure 20.7)
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Section 20 Ethernet Controller (EtherC)
(1) Write to PHY interface register MMD = 0 MDC = 1 (2) Write to PHY interface register read MMD = 0 MMC = 1 MDI is read data (3) Write to PHY interface register MMD = 0 MDC = 0
MDC
MDI
(1) (2) (3)
Figure 20.10 1-Bit Data Read Flowchart
(1) Write to PHY interfaceregister MMD = 0 MDC = 0
MDC
MDO
(1)
Figure 20.11 Independent Bus Release Flowchart (IDLE in Write in Figure 20.7)
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Section 20 Ethernet Controller (EtherC)
20.4.5
Magic Packet Detection
The EtherC supports the Magic Packet detection function. This function provides a Wake-OnLAN (WOL) facility that activates various peripheral devices connected to a LAN from the host device or other source. This makes it possible to construct a system in which a peripheral device receives a Magic Packet sent from the host device or other source, and activates itself. When the Magic Packet is detected, data is stored in the FIFO of the E-DMAC by the broadcast packet that has received data previously and the EtherC is notified of the receiving status. To return to normal operation from the interrupt processing, initialize the EtherC and E-DMAC by using the SWR bit in the E-DMAC mode register (EDMR). With a Magic Packet, reception is performed regardless of the destination address. As a result, this function is valid, and the WOL pin enabled, only in the case of a match with the destination address specified by the format in the Magic Packet. Further information on Magic Packets can be found in the technical documentation published by AMD Corporation. The procedure for using the WOL function with this LSI is as follows. 1. Disable interrupt source output by means of the various interrupt enable/mask registers. 2. Set the Magic Packet detection enable bit (MPDE) in the EtherC mode register (ECMR). 3. Set the Magic Packet detection interrupt enable bit (MPDIP) in the EtherC interrupt enable register (ECSIPR) to the enable setting. 4. If necessary, set the CPU operating mode to sleep mode or set supporting functions to module standby mode. 5. When a Magic Packet is detected, an interrupt is sent to the CPU. The WOL pin notifies peripheral LSIs that the Magic Packet has been detected.
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Section 20 Ethernet Controller (EtherC)
20.4.6
Operation by IPG Setting
The EtherC supports the function to change the Inter Packet Gap (IPG ), the non-transmission period between transmit frames. By changing the set values of the IPG setting register (IPGR), the transmission efficiency can be raised and lowered from the standard value. IPG settings are prescribed in IEEE802.3 standards. When changing settings, adequately check that the respective devices can operate smoothly on the same network. Note: IPG may be longer than the set value, depending on the state of the circuit and the system bus.
Case A (short IPG)
[1]
[2]
[3]
[4]
[5]
......
Case B (long IPG)
[1]
[2]
[3]
[4]
......
Figure 20.12 Changing IPG and Transmission Efficiency 20.4.7 Flow Control
The EtherC supports flow control functions conforming to IEEE802.3x in full-duplex operations. Flow control can be applied to both receive and transmit operations. The methods for transmitting PAUSE frames when controlling flow are as follows: (1) Automatic PAUSE Frame Transmission
For receive frames, PAUSE frames are automatically transmitted when the number of data in the receive FIFO (included in E-DMAC) reaches the value set in the flow control FIFO threshold register (FCFTR) of the E-DMAC. The TIME parameter included in the PAUSE frame at this time is set by the automatic PAUSE frame setting register (APR). The automatic PAUSE frame transmission is repeated until the number of data in the receive FIFO becomes less than the FCFTR setting as the receive data is read from the FIFO. The upper limit of the number of retransmissions of the PAUSE frame can also be set by the automatic PAUSE frame retransmission count set register (TPAUSER). In this case, PAUSE frame transmission is repeated until the number of data becomes FCFTR value set or below, or the
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Section 20 Ethernet Controller (EtherC)
number of transmits reaches the value set by TPAUSER. The automatic PAUSE frame transmission is enabled when the TXF bit in the EtherC mode register (ECMR) is 1. (2) Manual PAUSE Frame Transmission
PAUSE frames are transmitted by directives from the software. When writing the Timer value to the manual PAUSE frame set register (MPR), manual PAUSE frame transmission is started. With this method, PAUSE frame transmission is carried out only once. (3) PAUSE Frame Reception
The next frame is not transmitted until the time indicated by the Timer value elapses after receiving a PAUSE frame. However, the transmission of the current frame is continued. A received PAUSE frame is valid only when the RXF bit in the EtherC mode register (ECMR) is set to 1.
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Section 20 Ethernet Controller (EtherC)
20.5
20.5.1
Usage Notes
Conditions for Setting LCHNG Bit
Even if the level of the signal input to the LNKSTA pin is not changed, the LCHNG bit in ECSR may be set. It may happen when the pin function is changed from port to LNKSTA by PCCRH2 of the PFC or when a software reset caused by the SWR bit in EDMR is cleared while the LNKSTA pin is being driven high. This is because the LNKSTA signal is internally fixed low when the pin functions as a port or during the software reset state regardless of the external pin level. Clear the LCHNG bit before setting the LCHNGIP bit in ECSIPR not to request a LINK signal changed interrupt accidentally. 20.5.2 Flow Control Defect 1
Once a PAUSE frame is received while the receiving flow control is enabled in full-duplex mode (the RXF bit in ECMR = 1), each time when the local station receives a normal unicast frame (non-PAUSE frame without a CRC error), the TIME parameter specified by the PAUSE frame that has been previously received is incorrectly applied. As a result, unnecessary waiting time is generated to slow down the transmission throughput. The TIME parameter value is maintained until another PAUSE frame is received. This defect can be prevented if the destination station supports the function to transmit the 0-time PAUSE frame as the same as this LSI does. Enable the use of 0-time PAUSE frame in this LSI (the ZPF bit in ECMR = 1) before the 0-time PAUSE frame is received from the destination station. This clears the TIME parameter incorrectly maintained in the EtherC and prevents the unnecessary waiting time for transmission to be generated. 20.5.3 Flow Control Defect 2
When a PAUSE period is generated while the transmitting/receiving flow control is enabled in full-duplex mode (the TXF/RXF bit in ECMR = 1), non-PAUSE frames are waited for transmission (this is a normal operation) whereas PAUSE frames are incorrectly waited for transmission. The transmission of non-PAUSE frames in a PAUSE period is prohibited, though the transmission of PAUSE frames is enabled in IEEE802.3. When a PAUSE period is generated by the request from the destination station (that is, a PAUSE frame is received from the destination station), the load of the destination station is high and that
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Section 20 Ethernet Controller (EtherC)
of the local station is not so high. Therefore, the transmission of PAUSE frames during this period is less likely to happen. The possibility that this defect actually affects the operation in this LSI is rather low. 20.5.4 Operation Seed
The EtherC operates only in high-speed mode and does not operate in medium-speed mode.
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Section 20 Ethernet Controller (EtherC)
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Section 21 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Section 21 Ethernet Controller Direct Memory Access Controller (E-DMAC)
This LSI includes a direct memory access controller (E-DMAC) directly connected to the Ethernet controller (EtherC). A large proportion of buffer management is controlled by the E-DMAC itself using descriptors. This lightens the load on the CPU and enables efficient data transfer control to be achieved.
21.1
Features
The E-DMAC has the following features: * The load on the CPU is reduced by means of a descriptor management system * Transmit/receive frame status information is indicated in descriptors * Achieves efficient system bus utilization through the use of block transfer (16-byte units) * Supports single-frame/multi-buffer operation Figure 21.1 shows the configuration of the E-DMAC, and the descriptors and transmit/receive buffers in memory.
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Section 21 Ethernet Controller Direct Memory Access Controller (E-DMAC)
E-DMAC Descriptor information Internal bus interface Transmit DMAC
Transmit FIFO
EtherC Receive FIFO
Descriptor information Receive DMAC
Internal bus
RAM Transmit descriptor
Transmit buffer
Receive descriptor
Receive buffer
Figure 21.1 Configuration of E-DMAC, and Descriptors and Buffers
21.2
Register Descriptions
The E-DMAC has the following registers. * E-DMAC mode register (EDMR) * E-DMAC transmit request register (EDTRR) * E-DMAC receive request register (EDRRR) * Transmit descriptor list address register (TDLAR) * Receive descriptor list address register (RDLAR) * EtherC/E-DMAC status register (EESR) * EtherC/E-DMAC status interrupt permission register (EESIPR) * Transmit/receive status copy enable register (TRSCER) * Receive missed-frame counter register (RMFCR) * Transmit FIFO threshold register (TFTR) * FIFO depth register (FDR) * Receiving method control register (RMCR)
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Section 21 Ethernet Controller Direct Memory Access Controller (E-DMAC)
* Receive buffer write address register (RBWAR) * Receive descriptor fetch address register (RDFAR) * Transmit buffer read address register (TBRAR) * Transmit descriptor fetch address register (TDFAR) * Flow control FIFO threshold register (FCFTR) * Bit rate setting register (ECBRR) * Transmit interrupt register (TRIMD)
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Section 21 Ethernet Controller Direct Memory Access Controller (E-DMAC)
21.2.1
E-DMAC Mode Register (EDMR)
EDMR is a 32-bit readable/writable register that specifies the operating mode of the E-DMAC. The settings in this register are normally made in the initialization process following a reset. If the EtherC and E-DMAC are initialized by means of this register during data transmission, abnormal data may be sent onto the line. Operating mode settings must not be changed while the transmit and receive functions are enabled. To change the operating mode, the EtherC and E-DMAC modules are got into at their initial state by means of the software reset bit (SWR) in this register, then make new settings. It takes 64 states to initialize the EtherC and E-DMAC. Therefore, registers of the EtherC and E-DMAC should be accessed after 64 states have elapsed.
Bit 31 to 7 Bit Name Initial value All 0 R/W R Description Reserved These bits are always read as 0. The initial value should not be changed. 6 DE 0 R/W E-DMAC Data Endian Convert Selects whether or not the endian format is converted on data transfer by the E-DMAC. However, the endian format of the descriptors and E-DMAC register values are not converted regardless of this bit setting. 0: Endian format not converted (big endian) 1: Endian format converted (little endian) 5 4 DL1 DL0 0 0 R/W R/W Transmit/Receive Descriptor Length These bits specify the transmit/receive descriptor length. 00: 16 bytes 01: 32 bytes 10: 64 bytes 11: Setting prohibited 3 to 1 All 0 R Reserved These bits are always read as 0. The initial value should not be changed.
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Section 21 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Bit 0
Bit Name SWR
Initial value 0
R/W R/W
Description Software Reset Writing 1 in this bit initializes registers of the E-DMAC other than TDLAR, RDLAR, RMFCR, and ECBRR, and registers of the EtherC. While a software reset is issued (for 64 states), accesses to the all Ethernet-related registers are prohibited. Software reset period (example): When = 34 MHz: 1.88 s This bit is always read as 0. 0: Writing 0 is ignored (E-DMAC operation is not affected) 1: Writing 1 resets the EtherC and E-DMAC and then automatically cleared
21.2.2
E-DMAC Transmit Request Register (EDTRR)
The EDTRR is a 32-bit readable/writable register that issues transmit directives to the E-DMAC. When transmission of one frame is completed, the next descriptor is read. If the transmit descriptor active bit in this descriptor has the "active" setting, transmission is continued. If the transmit descriptor active bit has the "inactive" setting, the TR bit is cleared and operation of the transmit DMAC is halted.
Bit 31 to 1 Bit Name Initial value All 0 R/W R Description Reserved These bits are always read as 0. The initial value should not be changed. 0 TR 0 R/W Transmit Request Check TR = 0 before transmission is started. 0: Transmission-halted state. Writing 0 does not stop transmission. Termination of transmission is controlled by the active bit in the transmit descriptor 1: Start of transmission. The relevant descriptor is read and a frame is sent with the transmit active bit set to 1
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Section 21 Ethernet Controller Direct Memory Access Controller (E-DMAC)
21.2.3
E-DMAC Receive Request Register (EDRRR)
EDRRR is a 32-bit readable/writable register that issues receive directives to the E-DMAC. When the receive request bit is set, the E-DMAC reads the relevant receive descriptor. If the receive descriptor active bit in the descriptor has the "active" setting, the E-DMAC prepares for a receive request from the EtherC. When one receive buffer of data has been received, the E-DMAC reads the next descriptor and prepares to receive the next frame. If the receive descriptor active bit in the descriptor has the "inactive" setting, the RR bit is cleared and operation of the receive DMAC is halted.
Bit 31 to 1 Bit Name Initial value All 0 R/W R Description Reserved These bits are always read as 0. The initial value should not be changed. 0 RR 0 R/W Receive Request Check RR = 0 before reception is started. 0: The receive function is disabled* 1: A receive descriptor is read and the E-DMAC is ready to receive Note: * If the receive function is disabled during frame reception, write-back is not performed successfully to the receive descriptor. Following pointers to read a receive descriptor become abnormal and the E-DMAC cannot operate successfully. In this case, to make the E-DMAC reception enabled again, execute a software reset by the SWR bit in EDMR. To make the E-DMAC reception disabled without executing a software reset, set the RE bit in ECMR. Next, after the E_DMAC has completed the reception and write-back to the receive descriptor has been confirmed, disable the receive function of this register.
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Section 21 Ethernet Controller Direct Memory Access Controller (E-DMAC)
21.2.4
Transmit Descriptor List Address Register (TDLAR)
TDLAR is a 32-bit readable/writable register that specifies the start address of the transmit descriptor list. Descriptors have a boundary configuration in accordance with the descriptor length indicated by the DL bit in EDMR. This register must not be written to during transmission. Modifications to this register should only be made while transmission is disabled by the TR bit (= 0) in the E-DMAC transmit request register (EDTRR).
Bit 31 to 0 Bit Name TDLA31 to TDLA0 Initial value All 0 R/W R/W Description Transmit Descriptor Start Address The lower bits are set as follows according to the specified descriptor length. 16-byte boundary: TDLA3 to TDLA0 = 0000 32-byte boundary: TDLA4 to TDLA0 = 00000 64-byte boundary: TDLA5 to TDLA0 = 000000
21.2.5
Receive Descriptor List Address Register (RDLAR)
RDLAR is a 32-bit readable/writable register that specifies the start address of the receive descriptor list. Descriptors have a boundary configuration in accordance with the descriptor length indicated by the DL bit in EDMR. This register must not be written to during reception. Modifications to this register should only be made while reception is disabled by the RR bit (=0) in the E-DMAC Receive Request Register (EDRRR).
Bit 31 to 0 Bit Name RDLA31 to RDLA0 Initial value All 0 R/W R/W Description Receive Descriptor Start Address The lower bits are set as follows according to the specified descriptor length. 16-byte boundary: RDLA3 to RDLA0 = 0000 32-byte boundary: RDLA4 to RDLA0 = 00000 64-byte boundary: RDLA5 to RDLA0 = 000000
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Section 21 Ethernet Controller Direct Memory Access Controller (E-DMAC)
21.2.6
EtherC/E-DMAC Status Register (EESR)
EESR is a 32-bit readable/writable register that shows communications status information on the E-DMAC in combination with the EtherC. The information in this register is reported in the form of interrupts. Individual bits are cleared by writing 1 (however, bit 22 (ECI) is a read-only bit and not to be cleared by writing 1) and are not affected by writing 0. Each interrupt source can also be masked by means of the corresponding bit in the EtherC/E-DMAC status interrupt permission register (EESIPR). The interrupts generated by this register are EINT0. For interrupt priority, see section 5.5, Interrupt Exception Handling Vector Table.
Bit 31 Bit Name Initial value 0 R/W R Description Reserved This bit is always read as 0. The initial value should not be changed. 30 TWB 0 R/W Write-Back Complete Indicates that write-back from the E-DMAC to the corresponding descriptor has completed. This operation is enabled when the TIS bit in TRIMD is set to 1. 0: Write-back has not completed, or no transmission directive 1: Write-back has completed 29 to 27 All 0 R Reserved These bits are always read as 0. The initial value should not be changed. 26 TABT 0 R/W Transmit Abort Detection Indicates that the EtherC aborts transmitting a frame because of failures during transmitting the frame. 0: Frame transmission has not been aborted or no transmit directive 1: Frame transmit has been aborted
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Section 21 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Bit 25
Bit Name RABT
Initial value 0
R/W R/W
Description Receive Abort Detection Indicates that the EtherC aborts receiving a frame because of failures during receiving the frame. 0: Frame reception has not been aborted or no receive directive 1: Frame receive has been aborted
24
RFCOF
0
R/W
Receive Frame Counter Overflow Indicates that the receive FIFO frame counter has overflowed. 0: Receive frame counter has not overflowed 1: Receive frame counter overflows
23
ADE
0
R/W
Address Error Indicates that the memory address that the E-DMAC tried to transfer is found illegal. 0: Illegal memory address not detected (normal operation) 1: Illegal memory address detected Note: When an address error is detected, the E-DMAC halts transmitting/receiving. To resume the operation, set the E-DMAC again after software reset by means of the SWR bit in EDMR.
22
ECI
0
R
EtherC Status Register Interrupt Source This bit is a read-only bit. When the source of an ECSR interrupt in the EtherC is cleared, this bit is also cleared. 0: EtherC status interrupt source has not been detected 1: EtherC status interrupt source has been detected
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Section 21 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Bit 21
Bit Name TC
Initial value 0
R/W R/W
Description Frame Transmit Complete Indicates that all the data specified by the transmit descriptor has been transmitted to the EtherC. The transfer status is written back to the relevant descriptor. When 1-frame transmission is completed for 1-frame/1-buffer processing, or when the last data in the frame is transmitted and the transmission descriptor valid bit (TACT) in the next descriptor is not set for multiple-frame buffer processing, transmission is completed and this bit is set to 1. After frame transmission, the E-DMAC writes the transmission status back to the descriptor. 0: Transfer not complete, or no transfer directive 1: Transfer complete
20
TDE
0
R/W
Transmit Descriptor Empty Indicates that the transmission descriptor valid bit (TACT) in the descriptor is not set when the E-DMAC reads the transmission descriptor when the previous descriptor is not the last one of the frame for multiplebuffer frame processing. As a result, an incomplete frame may be transmitted. 0: Transmit descriptor active bit TACT = 1 detected 1: Transmit descriptor active bit TACT = 0 detected When transmission descriptor empty (TDE = 1) occurs, execute a software reset and initiate transmission. In this case, the address that is stored in the transmit descriptor list address register (TDLAR) is transmitted first.
19
TFUF
0
R/W
Transmit FIFO Underflow Indicates that underflow has occurred in the transmit FIFO during frame transmission. Incomplete data is sent onto the line. 0: Underflow has not occurred 1: Underflow has occurred
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Section 21 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Bit 18
Bit Name FR
Initial value 0
R/W R/W
Description Frame Reception Indicates that a frame has been received and the receive descriptor has been updated. This bit is set to 1 each time a frame is received. 0: Frame not received 1: Frame received
17
RDE
0
R/W
Receive Descriptor Empty When receive descriptor empty (RDE = 1) occurs, receiving can be restarted by setting RACT = 1 in the receive descriptor and initiating receiving. 0: Receive descriptor active bit RACT = 1 not detected 1: Receive descriptor active bit RACT = 0 detected
16
RFOF
0
R/W
Receive FIFO Overflow Indicates that the receive FIFO has overflowed during frame reception. 0: Overflow has not occurred 1: Overflow has occurred
15 to 12
All 0
R
Reserved These bits are always read as 0. The initial value should not be changed.
11
CND
0
R/W
Carrier Not Detect Indicates the carrier detection status. 0: A carrier is detected when transmission starts 1: A carrier is not detected when transmission starts
10
DLC
0
R/W
Detect Loss of Carrier Indicates that loss of the carrier has been detected during frame transmission. 0: Loss of carrier not detected 1: Loss of carrier detected
9
CD
0
R/W
Delayed Collision Detect Indicates that a delayed collision has been detected during frame transmission. 0: Delayed collision not detected 1: Delayed collision detected
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Section 21 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Bit 8
Bit Name TRO
Initial value 0
R/W R/W
Description Transmit Retry Over Indicates that a retry-over condition has occurred during frame transmission. Total 16 transmission retries including 15 retries based on the back-off algorithm are failed after the EtherC transmission starts. 0: Transmit retry-over condition not detected 1: Transmit retry-over condition detected
7
RMAF
0
R/W
Receive Multicast Address Frame 0: Multicast address frame has not been received 1: Multicast address frame has been received
6, 5
All 0
R
Reserved These bits are always read as 0. The initial value should not be changed.
4
RRF
0
R/W
Receive Residual-Bit Frame 0: Residual-bit frame has not been received 1: Residual-bit frame has been received
3
RTLF
0
R/W
Receive Too-Long Frame Indicates that the frame more than the number of receive frame length upper limit set by RFLR of the EtherC has been received. 0: Too-long frame has not been received 1: Too-long frame has been received
2
RTSF
0
R/W
Receive Too-Short Frame Indicates that a frame of fewer than 64 bytes has been received. 0: Too-short frame has not been received 1: Too-short frame has been received
1
PRE
0
R/W
PHY Receive Error 0: PHY receive error not detected 1: PHY receive error detected
0
CERF
0
R/W
CRC Error on Received Frame 0: CRC error not detected 1: CRC error detected
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Section 21 Ethernet Controller Direct Memory Access Controller (E-DMAC)
21.2.7
EtherC/E-DMAC Status Interrupt Permission Register (EESIPR)
EESIPR is a 32-bit readable/writable register that enables interrupts corresponding to individual bits in the EtherC/E-DMAC status register (EESR). An interrupt is enabled by writing 1 to the corresponding bit. In the initial state, interrupts are not enabled.
Bit 31 Bit Name Initial value 0 R/W R Description Reserved This bit is always read as 0. The initial value should not be changed. 30 TWBIP 0 R/W Write-Back Complete Interrupt Permission 0: Write-back complete interrupt is disabled 1: Write-back complete interrupt is enabled 29 to 27 All 0 R Reserved These bits are always read as 0. The initial value should not be changed. 26 TABTIP 0 R/W Transmit Abort Detection Interrupt Permission 0: Transmit abort detection interrupt is disabled 1: Transmit abort detection interrupt is enabled 25 RABTIP 0 R/W Receive Abort Detection Interrupt Permission 0: Receive abort detection interrupt is disabled 1: Receive abort detection interrupt is enabled 24 RFCOFIP 0 R/W Receive Frame Counter Overflow Interrupt Permission 0: Receive frame counter overflow interrupt is disabled 1: Receive frame counter overflow interrupt is enabled 23 ADEIP 0 R/W Address Error Interrupt Permission 0: Address error interrupt is disabled 1: Address error interrupt is enabled 22 ECIIP 0 R/W EtherC Status Register Interrupt Permission 0: EtherC status interrupt is disabled 1: EtherC status interrupt is enabled 21 TCIP 0 R/W Frame Transmit Complete Interrupt Permission 0: Frame transmit complete interrupt is disabled 1: Frame transmit complete interrupt is enabled
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Section 21 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Bit 20
Bit Name TDEIP
Initial value 0
R/W R/W
Description Transmit Descriptor Empty Interrupt Permission 0: Transmit descriptor empty interrupt is disabled 1: Transmit descriptor empty interrupt is enabled
19
TFUFIP
0
R/W
Transmit FIFO Underflow Interrupt Permission 0: Underflow interrupt is disabled 1: Underflow interrupt is enabled
18
FRIP
0
R/W
Frame Received Interrupt Permission 0: Frame received interrupt is disabled 1: Frame received interrupt is enabled
17
RDEIP
0
R/W
Receive Descriptor Empty Interrupt Permission 0: Receive descriptor empty interrupt is disabled 1: Receive descriptor empty interrupt is enabled
16
RFOFIP
0
R/W
Receive FIFO Overflow Interrupt Permission 0: Receive FIFO overflow interrupt is disabled 1: Receive FIFO overflow interrupt is enabled
15 to 12
All 0
R
Reserved These bits are always read as 0. The initial value should not be changed.
11
CNDIP
0
R/W
Carrier Not Detect Interrupt Permission 0: Carrier not detect interrupt is disabled 1: Carrier not detect interrupt is enabled
10
DLCIP
0
R/W
Detect Loss of Carrier Interrupt Permission 0: Detect loss of carrier interrupt is disabled 1: Detect loss of carrier interrupt is enabled
9
CDIP
0
R/W
Delayed Collision Detect Interrupt Permission 0: Delayed collision detect interrupt is disabled 1: Delayed collision detect interrupt is enabled
8
TROIP
0
R/W
Transmit Retry Over Interrupt Permission 0: Transmit retry over interrupt is disabled 1: Transmit retry over interrupt is enabled
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Section 21 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Bit 7
Bit Name RMAFIP
Initial value 0
R/W R/W
Description Receive Multicast Address Frame Interrupt Permission 0: Receive multicast address frame interrupt is disabled 1: Receive multicast address frame interrupt is enabled
6, 5
All 0
R
Reserved This bit is always read as 0. The initial value should not be changed.
4
RRFIP
0
R/W
Receive Residual-Bit Frame Interrupt Permission 0: Receive residual-bit frame interrupt is disabled 1: Receive residual-bit frame interrupt is enabled
3
RTLFIP
0
R/W
Receive Too-Long Frame Interrupt Permission 0: Receive too-long frame interrupt is disabled 1: Receive too-long frame interrupt is enabled
2
RTSFIP
0
R/W
Receive Too-Short Frame Interrupt Permission 0: Receive too-short frame interrupt is disabled 1: Receive too-short frame interrupt is enabled
1
PREIP
0
R/W
PHY-LSI Receive Error Interrupt Permission 0: PHY-LSI receive error interrupt is disabled 1: PHY-LSI receive error interrupt is enabled
0
CERFIP
0
R/W
CRC Error on Received Frame 0: CRC error on received frame interrupt is disabled 1: CRC error on received frame interrupt is enabled
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Section 21 Ethernet Controller Direct Memory Access Controller (E-DMAC)
21.2.8
Transmit/Receive Status Copy Enable Register (TRSCER)
TRSCER specifies whether or not receive status information reported by bits 7 and 4 in the EtherC/E-DMAC status register is to be indicated in bit RFE in the corresponding descriptor. Bits in this register correspond to bits 7 and 4 in the EtherC/E-DMAC status register (EESR). When a bit is cleared to 0, the receive status (bits 7 and 4 in EESR) is indicated in bit RFE of the receive descriptor. When a bit is set to 1, the occurrence of the corresponding interrupt is not indicated in the descriptor. After this LSI is reset, all bits are cleared to 0.
Bit 31 to 8 Bit Name Initial value All 0 R/W R Description Reserved These bits are always read as 0. The initial value should not be changed. 7 RMAFCE 0 R/W RMAF Bit Copy Directive 0: Indicates the RMAF bit state in bit RFE of the receive descriptor 1: Occurrence of the corresponding interrupt is not indicated in bit RFE of the receive descriptor 6, 5 All 0 R Reserved These bits are always read as 0. The initial value should not be changed. 4 RRFCE 0 R/W RRF Bit Copy Directive 0: Indicates the RRF bit state in bit RFE of the receive descriptor 1: Occurrence of the corresponding interrupt is not indicated in bit RFE of the receive descriptor 3 to 0 All 0 R Reserved These bits are always read as 0. The initial value should not be changed.
21.2.9
Receive Missed-Frame Counter Register (RMFCR)
RMFCR is a 16-bit counter that indicates the number of frames missed (discarded, and not transferred to the receive buffer) during reception. When the receive FIFO overflows, the receive frames in the FIFO are discarded. The number of frames discarded at this time is counted. When the value in this register reaches H'FFFF, counting-up is halted. When this register is read, the counter value is cleared to 0. Write operations to this register have no effect.
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Section 21 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Bit 31 to 16
Bit Name
Initial value All 0
R/W R
Description Reserved These bits are always read as 0. The initial value should not be changed.
15 to 0
MFC15 to MFC0
All 0
R
Missed-Frame Counter Indicate the number of frames that are discarded and not transferred to the receive buffer during reception.
21.2.10 Transmit FIFO Threshold Register (TFTR) TFTR is a 32-bit readable/writable register that specifies the transmit FIFO threshold at which the first transmission is started. The actual threshold is 4 times the set value. The EtherC starts transmission when the amount of data in the transmit FIFO exceeds the number of bytes specified by this register, when the transmit FIFO is full, or when 1-frame write is executed. When setting this register, do so in the transmission-halt state.
Bit 31 to 11 Bit Name Initial value All 0 R/W R Description Reserved These bits are always read as 0. The initial value should not be changed.
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Section 21 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Bit 10 to 0
Bit Name TFT10 to TFT0
Initial value All 0
R/W R/W
Description Transmit FIFO Threshold When setting a transmit FIFO, the FIFO must be set to a smaller value than the specified value of the FIFO capacity by FDR. The values between H'201 to H'7FF should not be set. H'00: Store and forward modes H'01 to H'0C: Setting prohibited H'0D: 52 bytes H'0E: 56 bytes : : : : : : H'20: 128 bytes H'40: 256 bytes H'80: 512 bytes H'200: 2048 bytes
Note: When starting transmission before one frame of data write has completed, take care the generation of the underflow.
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Section 21 Ethernet Controller Direct Memory Access Controller (E-DMAC)
21.2.11 FIFO Depth Register (FDR) FDR is a 32-bit readable/writable register that specifies the capacity of the transmit and receive FIFOs.
Bit 31 to 11 Bit Name Initial value All 0 R/W R Description Reserved These bits are always read as 0. The initial value should not be changed. 10 to 8 TFD2 to TFD0 B'000 R Transmit FIFO Capacity Specify the capacity of transmit FIFO, from 256 bytes to 2048 bytes, in 256-byte units. The set value should not be changed after the transmit/receive operation is started. All 0 R Reserved These bits are always read as 0. The initial value should not be changed. 2 to 0 RFD2 to RFD0 B'000 R Receive FIFO Capacity Specify the capacity of receive FIFO, from 256 bytes to 2048 bytes, in 256-byte units. The set value should not be changed after the transmit/receive operation is started.
7 to 3
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Section 21 Ethernet Controller Direct Memory Access Controller (E-DMAC)
21.2.12 Receiving method Control Register (RMCR) RMCR is a 32-bit readable/writable register that specifies the control method for the RR bit in EDRRR when a frame is received. This register must be set during the receiving-halt state.
Bit 31 to 1 Bit Name Initial value All 0 R/W R Description Reserved These bits are always read as 0. The initial value should not be changed. 0 RNC 0 R/W Receive Enable Control 0: When reception of one frame is completed, the EDMAC writes the receive status into the descriptor and clears the RR bit in EDRRR 1: When reception of one frame is completed, the EDMAC writes the receive status into the descriptor, reads the next descriptor, and prepares to receive the next frame
21.2.13 Receiving-Buffer Write Address Register (RBWAR) RBWAR stores the address of data to be written in the receiving buffer when the E-DMAC writes data to the receiving buffer. Which addresses in the receiving buffer are processed by the EDMAC can be recognized by monitoring addresses displayed in this register. The address that the E-DMAC is actually processing may be different from the value read from this register.
Bit 31 to 0 Bit Name RBWA31 to RBWA0 Initial value All 0 R/W R Description Receiving-Buffer Write Address These bits can only be read. Writing is prohibited.
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Section 21 Ethernet Controller Direct Memory Access Controller (E-DMAC)
21.2.14 Receiving-Descriptor Fetch Address Register (RDFAR) RDFAR stores the descriptor start address that is required when the E-DMAC fetches descriptor information from the receiving descriptor. Which receiving descriptor information is used for processing by the E-DMAC can be recognized by monitoring addresses displayed in this register. The address from which the E-DMAC is actually fetching a descriptor may be different from the value read from this register.
Bit 31 to 0 Bit Name RDFA31 to RDFA0 Initial value All 0 R/W R Description Receiving-Descriptor Fetch Address These bits can only be read. Writing is prohibited.
21.2.15 Transmission-Buffer Read Address Register (TBRAR) TBRAR stores the address of the transmission buffer when the E-DMAC reads data from the transmission buffer. Which addresses in the transmission buffer are processed by the E-DMAC can be recognized by monitoring addresses displayed in this register. The address from which the E-DMAC is actually reading in the buffer may be different from the value read from this register.
Bit 31 to 0 Bit Name TBRA31 to TBRA0 Initial value All 0 R/W R Description Transmission-Buffer Read Address These bits can only be read. Writing is prohibited.
21.2.16 Transmission-Descriptor Fetch Address Register (TDFAR) TDFAR stores the descriptor start address that is required when the E-DMAC fetches descriptor information from the transmission descriptor. Which transmission descriptor information is used for processing by the E-DMAC can be recognized by monitoring addresses displayed in this register. The address from which the E-DMAC is actually fetching a descriptor may be different from the value read from this register.
Bit 31 to 0 Bit Name TDFA31 to TDFA0 Initial value All 0 R/W R Description Transmission-Descriptor Fetch Address These bits can only be read. Writing is prohibited.
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Section 21 Ethernet Controller Direct Memory Access Controller (E-DMAC)
21.2.17 Flow Control FIFO Threshold Register (FCFTR) FCFTR is a 32-bit readable/writable register that sets the flow control of the EtherC (setting the threshold on automatic PAUSE transmission). The threshold can be specified by the depth of the receive FIFO data (RFD2 to RFD0) and the number of receive frames (RFF2 to RFF0). The condition to start the flow control is decided by taking OR operation on the two thresholds. Therefore, the flow control by the two thresholds is independently started. When flow control is performed according to the RFD bits setting, if the setting is the same as the depth of the receive FIFO specified by the FIFO depth register (FDR), flow control is started when the remaining FIFO is (FIFO data depth - 64) bytes. For instance, when RFD in FDR = 0 and RFD in FCFTR = 0, flow control is started when (256 - 64) bytes of data is stored in the receive FIFO. The value set in the RFD bits in this register should be equal to or less than those in FDR.
Bit 31 to 19 Bit Name Initial value All 0 R/W R Description Reserved These bits are always read as 0. The initial value should not be changed. 18 17 16 RFF2 RFF1 RFF0 1 1 1 R/W R/W R/W Receive Frame Number Flow Control Threshold 000: When 2 receive frame has been stored in the receive FIFO 001: When 4 receive frames have been stored in the receive FIFO : : 110: When 14 receive frames have been stored in the receive FIFO 111: When 16 receive frames have been stored in the receive FIFO
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Section 21 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Bit 15 to 3
Bit Name
Initial value All 0
R/W
Description Reserved These bits are always read as 0. The initial value should not be changed.
2 1 0
RFD2 RFD1 RFD0
1 1 1
R R R
Receive Byte Flow Control Threshold 000: When (256 - 32) bytes of data is stored in the receive FIFO 001: When (512 - 32) bytes of data is stored in the receive FIFO : : 110: When (1792 - 32) bytes of data is stored in the receive FIFO 001: When (2048 - 64) bytes of data is stored in the receive FIFO
21.2.18 Bit Rate Setting Register (ECBRR) ECBRR sets the bit rate for retransmission and reception.
Bit 7 to 1 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 0 RTM 0 R/W Transmit/Receive Rate 0: 10 Mbps 1: 100 Mbps
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Section 21 Ethernet Controller Direct Memory Access Controller (E-DMAC)
21.2.19 Transmit Interrupt Register (TRIMD) TRIMD is a 32-bit readable/writable register that specifies whether or not to notify write-back completion for each frame using the TWB bit in EESR and an interrupt on transmit operations.
Bit 31 to 1 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 0 TIS 0 R/W Transmit Interrupt Setting 0: Write-back completion for each frame is not notified 1: Write-back completion for each frame using the TWB bit in EESR is notified
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Section 21 Ethernet Controller Direct Memory Access Controller (E-DMAC)
21.3
Operation
The E-DMAC is connected to the EtherC, and performs efficient transfer of transmit/receive data between the EtherC and memory (buffers) without the intervention of the CPU. The E-DMAC itself reads control information, including buffer pointers called descriptors, relating to the buffers. The E-DMAC reads transmit data from the transmit buffer and writes receive data to the receive buffer in accordance with this control information. By setting up a number of consecutive descriptors (a descriptor list), it is possible to execute transmission and reception continuously. 21.3.1 Descriptor List and Data Buffers
Before starting transmission/reception, the communication program creates transmit and receive descriptor lists in memory. The start addresses of these lists are then set in the transmit and receive descriptor list start address registers. The descriptor start address must be aligned so that it matches the address boundary according to the descriptor length set by the E-DMAC mode register (EDMR). The transmit buffer start address may be set on a byte, a word, and a longword boundary. (1) Transmit Descriptor
Figure 21.2 shows the relationship between a transmit descriptor and the transmit buffer. According to the specification in this descriptor, the relationship between the transmit frame and transmit buffer can be defined as one frame/one buffer or one frame/multi-buffer.
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Section 21 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Transmit descriptor 31 30 29 28 27 26 TTTTT ADFFF CLPPE TE10 31 TD1 31 TD2 TBA Padding (4 bytes) TDL 0 TFS26 to TFS0
Transmit buffer
TD0
16 15 Fixed at H'0000
0 0
Valid transmit data
Figure 21.2 Relationship between Transmit Descriptor and Transmit Buffer
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Section 21 Ethernet Controller Direct Memory Access Controller (E-DMAC)
(a)
Transmit Descriptor 0 (TD0)
TD0 indicates the transmit frame status. The CPU and E-DMAC use RD0 to report the frame transmission status.
Bit 31 Bit Name TACT Initial value 0 R/W R/W Description Transmit Descriptor Active Indicates that this descriptor is active. The CPU sets this bit after transmit data has been transferred to the transmit buffer. The E-DMAC resets this bit on completion of a frame transfer or when transmission is suspended. 0: The transmit descriptor is invalid. Indicates that valid data has not been written to this bit by the CPU, or this bit has been reset by a write-back operation on termination of E-DMAC frame transfer processing (completion or suspension of transmission) If this state is recognized in an E-DMAC descriptor read, the E-DMAC terminates transmit processing and transmit operations cannot be continued (a restart is necessary) 1: The transmit descriptor is valid. Indicates that valid data has been written to the transmit buffer by the CPU and frame transfer processing has not yet been executed, or that frame transfer is in progress When this state is recognized in an E-DMAC descriptor read, the E-DMAC continues with the transmit operation 30 TDLE 0 R/W Transmit Descriptor List End After completion of the corresponding buffer transfer, the E-DMAC references the first descriptor. This specification is used to set a ring configuration for the transmit descriptors. 0: This is not the last transmit descriptor list 1: This is the last transmit descriptor list
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Section 21 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Bit 29 28
Bit Name TFP1 TFP0
Initial value 0 0
R/W R/W R/W
Description Transmit Frame Position 1, 0 These two bits specify the relationship between the transmit buffer and transmit frame. In the preceding and following descriptors, a logically positive relationship must be maintained between the settings of this bit and the TDLE bit. 00: Frame transmission for transmit buffer indicated by this descriptor continues (frame is not concluded) 01: Transmit buffer indicated by this descriptor contains end of frame (frame is concluded) 10: Transmit buffer indicated by this descriptor is start of frame (frame is not concluded) 11: Contents of transmit buffer indicated by this descriptor are equivalent to one frame (one frame/one buffer)
27
TFE
0
R/W
Transmit Frame Error Indicates that one or other bit of the transmit frame status indicated by bits 26 to 0 is set. 0: No error during transmission 1: An error occurred during transmission
26 to 0
TFS26 to TFS0
All 0
R/W
Transmit Frame Status TFS26 to TFS9: Reserved (The write value should always be 0.) TFS8: Transmit Abort Detection (indicates any of bits TFS3 to TFS0 has been set.) TFS7 to TFS4: Reserved (The write value should always be 0.) TFS3: Carrier Not Detected (corresponds to CND bit in EESR) TFS2: Detect Loss of Carrier (corresponds to DLC bit in EESR) TFS1: Delayed Collision Detect (corresponds to CD bit in EESR) TFS0: Transmit Retry Over (corresponds to TRO bit in EESR)
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Section 21 Ethernet Controller Direct Memory Access Controller (E-DMAC)
(b)
Transmit Descriptor 1 (TD1)
TD1 specifies the transmit buffer length (maximum 64 kbytes).
Bit 31 to 16 Bit Name TDL Initial value All 0 R/W R/W Description Transmit Buffer Data Length These bits specify the valid transfer byte length in the corresponding transmit buffer. If set to 0, the operation is not guaranteed. When the one frame/multi-buffer system is specified (TFP1 and TF0 in TD0 = B'10 or B'00), the transfer byte length specified in the descriptors at the start and midway can be set in byte units. 15 to 0 All 0 R Reserved These bits are always read as 0. The initial value should not be changed.
(c)
Transmit Descriptor 2 (TD2)
TD2 specifies the 32-bit transmit buffer start address. The transmit buffer start address setting may be on a byte, a word, or a longword boundary.
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Section 21 Ethernet Controller Direct Memory Access Controller (E-DMAC)
(2)
Receive Descriptor
Figure 21.3 shows the relationship between a receive descriptor and the receive buffer. In frame reception, the E-DMAC performs data rewriting up to a receive buffer 16-byte boundary, regardless of the receive frame length. Finally, the actual receive frame length is reported in the lower 16 bits of RD1 in the descriptor. Data transfer to the receive buffer is performed automatically by the E-DMAC to give a one frame/one buffer or one frame/multi-buffer configuration according to the size of one received frame.
Receive descriptor 31 30 29 28 27 26 RRRRR ADF FF CLPPE TE1 0 31 RD1 31 RD2 RBA Padding (4 bytes) RBL 20 19 0 RFS26 to RFS0 Valid receive data Receive buffer
RD0
16 15 H'0
0 RDL 0
Figure 21.3 Relationship between Receive Descriptor and Receive Buffer
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Section 21 Ethernet Controller Direct Memory Access Controller (E-DMAC)
(a)
Receive Descriptor 0 (RD0)
RD0 indicates the receive frame status. The CPU and E-DMAC use RD0 to report the frame receive status.
Bit 31 Bit Name RACT Initial value 0 R/W R/W Description Receive Descriptor Active Indicates that this descriptor is active. The E-DMAC resets this bit after receive data has been transferred to the receive buffer. On completion of receive frame processing, the CPU sets this bit to prepare for reception. 0: The receive descriptor is invalid. Indicates that the receive buffer is not ready (access disabled by E-DMAC), or this bit has been reset by a write-back operation on termination of E-DMAC frame transfer processing (completion or suspension of reception). If this state is recognized in an E-DMAC descriptor read, the E-DMAC terminates receive processing and receive operations cannot be continued. Reception can be restarted by setting RACT to 1 and executing receive initiation. 1: The receive descriptor is valid Indicates that the receive buffer is ready (access enabled) and processing for frame transfer from the FIFO has not been executed, or that frame transfer is in progress. When this state is recognized in an E-DMAC descriptor read, the E-DMAC continues with the receive operation. 30 RDLE 0 R/W Receive Descriptor List Last After completion of the corresponding buffer transfer, the E-DMAC references the first receive descriptor. This specification is used to set a ring configuration for the receive descriptors. 0: This is not the last receive descriptor list 1: This is the last receive descriptor list
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Section 21 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Bit 29 28
Bit Name RFP1 RFP0
Initial value 0 0
R/W R/W R/W
Description Receive Frame Position These two bits specify the relationship between the receive buffer and receive frame. 00: Frame reception for receive buffer indicated by this descriptor continues (frame is not concluded) 01: Receive buffer indicated by this descriptor contains end of frame (frame is concluded) 10: Receive buffer indicated by this descriptor is start of frame (frame is not concluded) 11: Contents of receive buffer indicated by this descriptor are equivalent to one frame (one frame/one buffer)
27
RFE
0
R/W
Receive Frame Error Indicates that one or other bit of the receive frame status indicated by bits 26 to 0 is set. Whether or not the receive frame status information is copied into this bit is specified by the transmit/receive status copy enable register. 0: No error during reception 1: A certain kind of error occurred during reception
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Section 21 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Bit 26 to 0
Bit Name RFS26 to RFS0
Initial value All 0
R/W R/W
Description Receive Frame Status These bits indicate the error status during frame reception. RFS26 to RFS10: Reserved (The initial value should not be changed.) RFS9: Receive FIFO overflow (corresponds to RFOF bit in EESR) RFS8: Abort Detection (indicates any of bits RFS3 to RFS0 has been set.) RFS7: Multicast address frame received (corresponds to RMAF bit in EESR) RFS6: CAM entry unregistered frame received (corresponds to the RUAF bit in EESR) RSF5: Reserved (The write value should always be 0.) RFS4: Receive residual-bit frame error (corresponds to RRF bit in EESR) RFS3: Receive too-long frame error (corresponds to RTLF bit in EESR) RFS2: Receive too-short frame error (corresponds to RTSF bit in EESR) RFS1: PHY-LSI receive error (corresponds to PRE bit in EESR) RFS0: CRC error on received frame (corresponds to CERF bit in EESR)
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Section 21 Ethernet Controller Direct Memory Access Controller (E-DMAC)
(b)
Receive Descriptor 1 (RD1)
RD1 specifies the receive buffer length (maximum 64 kbytes).
Bit 31 to 16 Bit Name RBL Initial value All 0 R/W R/W Description Receive Buffer Length These bits specify the maximum reception byte length in the corresponding receive buffer. The transfer byte length must align with a 16-byte boundary (bits 19 to 16 cleared to 0). The maximum receive frame length with one frame per buffer is 1,514 bytes, excluding the CRC data. Therefore, for the receive buffer length specification, a value of 1,520 bytes (H'05F0) that takes account of a 16-byte boundary is set as the maximum receive frame length. 15 to 0 RDL All 0 R/W Receive Data Length These bits specify the data length of a receive frame stored in the receive buffer. The receive data transferred to the receive buffer does not include the 4-byte CRC data at the end of the frame. The receive frame length is reported as the number of words (valid data bytes) not including this CRC data.
(c)
Receive Descriptor 2 (RD2)
RD2 specifies the 32-bit receive buffer start address. The receive buffer start address must be on a longword boundary.
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Section 21 Ethernet Controller Direct Memory Access Controller (E-DMAC)
21.3.2
Transmission
When the transmit function is enabled and the transmit request bit (TR) is set in the E-DMAC transmit request register (EDTRR), the E-DMAC reads the descriptor used last time from the transmit descriptor list (in the initial state, the descriptor indicated by the transmission descriptor start address register (TDLAR)). If the setting of the TACT bit in the read descriptor is active, the E-DMAC reads transmit frame data sequentially from the transmit buffer start address specified by TD2, and transfers it to the EtherC. The EtherC creates a transmit frame and starts transmission to the MII. After DMA transfer of data equivalent to the buffer length specified in the descriptor, the following processing is carried out according to the TFP value. 1. TFP = 00 or 01 (frame continuation): Descriptor write-back is performed after DMA transfer. 2. TFP = 01 or 11 (frame end): Descriptor write-back is performed after completion of frame transmission. The E-DMAC continues reading descriptors and transmitting frames as long as the setting of the TACT bit in the read descriptors is "active." When a descriptor with an "inactive" TACT bit is read, the E-DMAC resets the transmit request bit (TR) in the transmit register and ends transmit processing (EDTRR).
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Section 21 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Transmission flowchart This LSI + memory E-DMAC Transmit FIFO EtherC Ethernet
EtherC/E-DMAC initialization
Descriptor and transmit buffer setting Transmit directive Descriptor read
Transmit data transfer Descriptor write-back Descriptor read
Transmit data transfer Frame transmission
Descriptor write-back Transmission completed
Figure 21.4 Sample Transmission Flowchart
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Section 21 Ethernet Controller Direct Memory Access Controller (E-DMAC)
21.3.3
Reception
When the receive function is enabled and the CPU sets the receive request bit (RR) in the EDMAC receive request register (EDRRR), the E-DMAC reads the descriptor following the previously used one from the receive descriptor list (in the initial state, the descriptor indicated by the transmission descriptor start address register (TDLAR)), and then enters the receive-standby state. If the setting of the RACT bit is "active" and an own-address frame is received, the EDMAC transfers the frame to the receive buffer specified by RD2. If the data length of the received frame is greater than the buffer length given by RD1, the E-DMAC performs write-back to the descriptor when the buffer is full (RFP = 10 or 00), then reads the next descriptor. The EDMAC then continues to transfer data to the receive buffer specified by the new RD2. When frame reception is completed, or if frame reception is suspended because of a certain kind of error, the E-DMAC performs write-back to the relevant descriptor (RFP = 11 or 01), and then ends the receive processing. The E-DMAC then reads the next descriptor and enters the receive-standby state again. To receive frames continuously, the receive enable control bit (RNC) must be set to 1 in the receive control register (RCR). After initialization, this bit is cleared to 0.
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Section 21 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Reception flowchart This LSI + memory E-DMAC Receive FIFO EtherC Ethernet
EtherC/E-DMAC initialization
Descriptor and receive buffer setting Start of reception Descriptor read
Frame reception
Receive data transfer Descriptor write-back Descriptor read
Receive data transfer Descriptor write-back Descriptor read (receive ready for the next frame)
Reception completed
Figure 21.5 Sample Reception Flowchart
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Section 21 Ethernet Controller Direct Memory Access Controller (E-DMAC)
21.3.4
Multi-Buffer Frame Transmit/Receive Processing
Multi-Buffer Frame Transmit Processing If an error occurs during multi-buffer frame transmission, the processing shown in figure 21.6 is carried out by the E-DMAC. Where the transmit descriptor is shown as inactive (TACT bit = 0) in the figure, buffer data has already been transmitted normally, and where the transmit descriptor is shown as active (TACT bit = 1), buffer data has not been transmitted. If a frame transmit error occurs in the first descriptor part where the transmit descriptor is active (TACT bit = 1), transmission is halted, and the TACT bit cleared to 0, immediately. The next descriptor is then read, and the position within the transmit frame is determined on the basis of bits TFP1 and TFP0 (continuing [B'00] or end [B'01]). In the case of a continuing descriptor, the TACT bit is cleared to 0, only, and the next descriptor is read immediately. If the descriptor is the final descriptor, not only is the TACT bit cleared to 0, but write-back is also performed to the TFE and TFS bits at the same time. Data in the buffer is not transmitted between the occurrence of an error and write-back to the final descriptor. If error interrupts are enabled in the EtherC/E-DMAC status interrupt permission register (EESIPR), an interrupt is generated immediately after the final descriptor write-back.
Descriptors T A C T T D L E T F P 1 T F P 0
00 00 00 Inactivates TACT (change 1 to 0) E-DMAC Descriptor read Inactivates TACT Descriptor read Inactivates TACT Descriptor read Inactivates TACT Descriptor read Inactivates TACT and writes TFE, TFS 10 10 10 10 10 11
10 00 00 00 00 00 00 01 10 Buffer
Untransmitted data is not transmitted after error occurrence Descriptor is only processed.
Transmit error occurrence
One frame
Transmitted data Untransmitted data
Figure 21.6 E-DMAC Operation after Transmit Error
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Section 21 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Multi-Buffer Frame Receive Processing If an error occurs during multi-buffer frame reception, the processing shown in figure 21.7 is carried out by the E-DMAC. Where the receive descriptor is shown as inactive (RACT bit = 0) in the figure, buffer data has already been received normally, and where the receive descriptor is shown as active (RACT bit = 1), this indicates a buffer for which reception has not yet been performed. If a frame receive error occurs in the first descriptor part where the RACT bit = 1 in the figure, reception is halted immediately and a status write-back to the descriptor is performed. If error interrupts are enabled in the EtherC/E-DMAC status interrupt permission register (EESIPR), an interrupt is generated immediately after the write-back. If there is a new frame receive request, reception is continued from the buffer after that in which the error occurred.
Descriptors R A C T 0 0 0 Inactivates RACT and writes RFE, RFS E-DMAC 1 Descriptor read Write-back 1 1 1 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 Buffer New frame reception continues from buffer 0 0 1 R D L E 0 0 0 R F P 1 1 0 0 R F P 0 0 0 0 Receive error occurrence Start of frame
Figure 21.7 E-DMAC Operation after Receive Error
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.........
Received data Unreceived data
Section 22 USB Function Module (USB)
Section 22 USB Function Module (USB)
The H8S/2472 Group incorporates a USB function module (USB).
22.1
Features
* The UDC (USB device controller) conforming to USB2.0 and transceiver process USB protocol automatically. Automatic processing of USB standard commands for endpoint 0 (some commands and class/vendor commands require decoding and processing by firmware) * Transfer speed: Supports full-speed (12 Mbps) * Endpoint configuration:
Endpoint Name Endpoint 0 Maximum FIFO Buffer Abbreviation Transfer Type Packet Size Capacity (Byte) EP0s EP0i EP0o Endpoint 1 Endpoint 2 Endpoint 3 EP1 EP2 EP3 Setup Control-in Control-out Bulk-out Bulk-in Interrupt-in 8 8 8 64 64 8 8 8 8 128 128 8 DTC Transfer Possible Possible
Configuration1-Interface0-AlternateSetting0
EndPoint1 EndPoint2 EndPoint3
* Interrupt requests: Generates various interrupt signals necessary for USB transmission/reception * Power mode: Self-powered mode Note: The EtherC operates only in high-speed mode
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Section 22 USB Function Module (USB)
Figure 22.1 shows the block diagram of the USB.
Peripheral bus USB function module
Interrupt requests
Status and control registers D+ UDC FIFO Transceiver D-
Clock for USB (48 MHz) [Legend] UDC: USB device controller
Figure 22.1 Block Diagram of USB
22.2
Input/Output Pins
Table 22.1 shows the USB pin configuration. Table 22.1 Pin Configuration
Pin Name VBUS USD+ USDDrVcc DrVss PUPDPLS UXTAL UEXTAL UXSEL I/O Input I/O I/O Input Input Output Input Input Input Function USB cable connection monitor pin USB data I/O pin USB data I/O pin Power supply pin for USB built-in transceiver Ground pin for USB built-in transceiver Pull-up control pin USB clock pin USB clock pin USB clock select pin
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Section 22 USB Function Module (USB)
22.3
Register Descriptions
The USB has following registers. * Interrupt flag register 0 (IFR0) * Interrupt flag register 1 (IFR1) * Interrupt flag register 2 (IFR2) * Interrupt select register 0 (ISR0) * Interrupt select register 1 (ISR1) * Interrupt select register 2 (ISR2) * Interrupt enable register 0 (IER0) * Interrupt enable register 1 (IER1) * Interrupt enable register 2 (IER2) * EP0i data register (EPDR0i) * EP0o data register (EPDR0o) * EP0s data register (EPDR0s) * EP1 data register (EPDR1) * EP2 data register (EPDR2) * EP3 data register (EPDR3) * EP0o receive data size register (EPSZ0o) * EP1 receive data size register (EPSZ1) * Trigger register (TRG) * Data status register (DASTS) * FIFO clear register (FCLR) * DTC transfer setting register (DMA) * Endpoint stall register (EPSTL) * Configuration value register (CVR) * Control register (CTLR) * Endpoint information register (EPIR) * Transceiver test register 0 (TRNTREG0) * Transceiver test register 1 (TRNTREG1)
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Section 22 USB Function Module (USB)
22.3.1
Interrupt Flag Register 0 (IFR0)
IFR0, together with interrupt flag registers 1and 2 (IFR1and IFR2), indicates interrupt status information required by the application. When an interrupt source is generated, the corresponding bit is set to 1. And then this bit, in combination with interrupt enable register 0 (IER0), generates an interrupt request to the CPU. To clear, write 0 to the bit to be cleared and 1 to the other bits. However, since EP1FULL and EP2EMPTY are status bits, these bits cannot be cleared.
Bit 7 Bit Name BRST Initial Value 0 R/W R/W Description Bus Reset This bit is set to 1 when a bus reset signal is detected on the USB bus. 6 EP1FULL 0 R/W EP1 FIFO Full [Reading] This bit is set when endpoint 1 receives one packet of data successfully from the host, and holds a value of 1 as long as there is valid data in the FIFO buffer. This bit cannot be cleared. [Writing] When the data in endpoint 1 is transferred by the DTC, writing 0 to this bit clears the request for a DTC transfer end interrupt. If the DTC transfer is not used, always write 1 to this bit. 5 EP2TR 0 R/W EP2 Transfer Request This bit is set if there is no valid transmit data in the FIFO buffer when an IN token for endpoint 2 is received from the host. A NAK handshake is returned to the host until data is written to the FIFO buffer and packet transmission is enabled.
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Section 22 USB Function Module (USB)
Bit 4
Bit Name EP2EMPTY
Initial Value 1
R/W R/(W)
Description EP2 FIFO Empty [Reading] This bit is set when at least one of the dual endpoint 2 transmit FIFO buffers is ready for transmit data to be written. This bit cannot be cleared. [Writing] When the data in endpoint 2 is transferred by the DTC, writing 0 to this bit clears the request for a DTC transfer end interrupt. If the DTC transfer is not used, always write 1 to this bit.
3
SETUPTS
0
R/W
Setup Command Receive Complete This bit is set to 1 when endpoint 0 receives successfully a setup command requiring decoding on the application side, and returns an ACK handshake to the host.
2
EP0oTS
0
R/W
EP0o Receive Complete This bit is set to 1 when endpoint 0 receives data from the host successfully, stores the data in the FIFO buffer, and returns an ACK handshake to the host.
1
EP0iTR
0
R/W
EP0i Transfer Request This bit is set if there is no valid transmit data in the FIFO buffer when an IN token for endpoint 0 is received from the host. A NAK handshake is returned to the host until data is written to the FIFO buffer and packet transmission is enabled.
0
EP0iTS
0
R/W
EP0i Transmit Complete This bit is set when data is transmitted to the host from endpoint 0 and an ACK handshake is returned.
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Section 22 USB Function Module (USB)
22.3.2
Interrupt Flag Register 1 (IFR1)
IFR1, together with interrupt flag registers 0 and 2 (IFR0 and IFR2), indicates interrupt status information required by the application. When an interrupt source is generated, the corresponding bit is set to 1. And then this bit, in combination with interrupt enable register 1 (IER1), generates an interrupt request to the CPU. To clear, write 0 to the bit to be cleared and 1 to the other bits.
Bit 7 to 4 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The initial value should not be changed. 3 VBUS MN 0 R This is a status bit which monitors the state of the VBUS pin. This bit reflects the state of the VBUS pin and generates no interrupt request. This bit is always 0 when the PULLUP_E bit in DMA is 0. 2 EP3 TR 0 R/W EP3 Transfer Request This bit is set if there is no valid transmit data in the FIFO buffer when an IN token for endpoint 3 is received from the host. A NAK handshake is returned to the host until data is written to the FIFO buffer and packet transmission is enabled. 1 EP3 TS 0 R/W EP3 Transmit Complete This bit is set when data is transmitted to the host from endpoint 3 and an ACK handshake is returned. 0 VBUSF 0 R/W USB Disconnection Detection When the function is connected to the USB bus or disconnected from it, this bit is set to 1. The VBUS pin of this module is used for detecting connection or disconnection.
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Section 22 USB Function Module (USB)
22.3.3
Interrupt Flag Register 2 (IFR2)
IFR2, together with interrupt flag registers 0 and 1 (IFR0 and IFR1), indicates interrupt status information required by the application. When an interrupt source is generated, the corresponding bit is set to 1. And then this bit, in combination with interrupt enable register 2 (IER2), generates an interrupt request to the CPU. To clear, write 0 to the bit to be cleared and 1 to the other bits.
Bit 7, 6 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The initial value should not be changed. 5 SURSS 0 R Suspend/Resume Status This is a status bit that describes bus state. 0: Normal state 1: Suspended state This bit is a status bit and generates no interrupt request. 4 SURSF 0 R/W Suspend/Resume Detection This bit is set to 1 when the state changed from normal to suspended state or vice versa. The corresponding interrupt output is RESUME, USBINTN2, and USBINTN3. 3 CFDN 0 R/W End Point Information Load End This bit is set to 1 when writing data in the endpoint information register to the EPIR register ends (load end). This module starts the USB operation after the endpoint information is completely set. 2 1 SOF SETC 0 0 R R/W SOF Interrupt Detection This bit is set to 1 when an SOF interrupt is detected. Set_Configuration Command Detection When the Set_Configuration command is detected, this bit is set to 1. 0 SETI 0 R/W Set_Interface Command Detection When the Set_Interface command is detected, this bit is set to 1.
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Section 22 USB Function Module (USB)
22.3.4
Interrupt Select Register 0 (ISR0)
ISR0 selects the vector numbers of the interrupt requests indicated in interrupt flag register 0 (IFR0). If the USB issues an interrupt request to the INTC when a bit in ISR0 is cleared to 0, the interrupt corresponding to the bit will be USBINTN2. If the USB issues an interrupt request to the INTC when a bit in ISR0 is set to 1, the corresponding interrupt will be USBINTN3.
Bit 7 6 5 4 3 2 1 0 Bit Name BRST EP1 FULL EP2 TR Initial Value 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Bus Reset EP1 FIFO Full EP2 Transfer Request EP2 FIFO Empty Setup Command Receive Complete EP0o Receive Complete EP0i Transfer Request EP0i Transmission Complete
EP2 EMPTY 0 SETUP TS EP0o TS EP0i TR EP0i TS 0 0 0 0
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Section 22 USB Function Module (USB)
22.3.5
Interrupt Select Register 1 (ISR1)
ISR1 selects the vector numbers of the interrupt requests indicated in interrupt flag register 1 (IFR1). If the USB issues an interrupt request to the INTC when a bit in ISR0 is cleared to 0, the interrupt corresponding to the bit will be USBINTN2. If the USB issues an interrupt request to the INTC when a bit in ISR0 is set to 1, the corresponding interrupt will be USBINTN3.
Bit 7 to 3 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The initial value should not be changed. 2 1 0 EP3 TR EP3 TS VBUSF 1 1 1 R/W R/W R/W EP3 Transfer Request EP3 Transmission Complete USB Bus Connect
22.3.6
Interrupt Select Register 2 (ISR2)
ISR2 selects the vector numbers of the interrupt requests indicated in interrupt flag register 2 (IFR2). If the USB issues an interrupt request to the INTC when a bit in ISR0 is cleared to 0, the interrupt corresponding to the bit will be USBINTN2. If the USB issues an interrupt request to the INTC when a bit in ISR0 is set to 1, the corresponding interrupt will be USBINTN3.
Bit 7 to 5 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The initial value should not be changed. 4 3 2 1 0 SURSE CFDN SOF SETCE SETIE 1 1 1 1 1 R/W R/W R/W R/W R/W Suspend/Resume Detection End Point Information Load End SOF Interrupt Detection Set_Configuration Command Detection Set_Interface Command Detection
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Section 22 USB Function Module (USB)
22.3.7
Interrupt Enable Register 0 (IER0)
IER0 enables the interrupt requests of interrupt flag register 0 (IFR0). When an interrupt flag is set to 1 while the corresponding bit of each interrupt is set to 1, an interrupt request is sent to the CPU. The interrupt vector number is determined by the contents of interrupt select register 0 (ISR0).
Bit 7 6 5 4 3 2 1 0 Bit Name BRST EP1 FULL EP2 TR EP2 EMPTY SETUP TS EP0o TS EP0i TR EP0i TS Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Bus Reset EP1 FIFO Full EP2 Transfer Request EP2 FIFO Empty Setup Command Receive Complete EP0o Receive Complete EP0i Transfer Request EP0i Transmission Complete
22.3.8
Interrupt Enable Register 1 (IER1)
IER1 enables the interrupt requests of interrupt flag register 1 (IFR1). When an interrupt flag is set to 1 while the corresponding bit of each interrupt is set to 1, an interrupt request is sent to the CPU. The interrupt vector number is determined by the contents of interrupt select register 1 (ISR1).
Bit 7 to 3 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The initial value should not be changed. 2 1 0 EP3 TR EP3 TS VBUSF 0 0 0 R/W R/W R/W EP3 Transfer Request EP3 Transmission Complete USB Bus Connect
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Section 22 USB Function Module (USB)
22.3.9
Interrupt Enable Register 2 (IER2)
IER2 enables the interrupt requests of interrupt flag register 2 (IFR2). When an interrupt flag is set to 1 while the corresponding bit of each interrupt is set to 1, an interrupt request is sent to the CPU. The interrupt vector number is determined by the contents of interrupt select register 2 (ISR2).
Bit 7 Bit Name SSRSME Initial Value 0 R/W R/W Description Resume Detection for Software Standby Cancel For the details of the operation, see section 22.5.3, Suspend and Resume Operations. 6, 5 All 0 R Reserved These bits are always read as 0. The initial value should not be changed. 4 SURSE 0 R/W Suspend/Resume Detection For the details of the operation, see section 22.5.3, Suspend and Resume Operations. 3 2 1 0 CFDN SOF SETCE SETIE 0 0 0 0 R/W R/W R/W R/W End Point Information Load End SOF Interrupt Detection Set_Configuration Command Detection Set_Interface Command Detection
22.3.10 EP0i Data Register (EPDR0i) EPDR0i is an 8-byte transmit FIFO buffer for endpoint 0. EPDR0i holds one packet of transmit data for control-in. Transmit data is fixed by writing one packet of data and setting EP0iPKTE in the trigger register. When an ACK handshake is returned from the host after the data has been transmitted, EP0iTS in interrupt flag register 0 is set. This FIFO buffer can be initialized by means of EP0iCLR in the FCLR register.
Bit 7 to 0 Bit Name D7 to D0 Initial Value R/W Description Data register for control-in transfer
Undefined W
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Section 22 USB Function Module (USB)
22.3.11 EP0o Data Register (EPDR0o) EPDR0o is an 8-byte receive FIFO buffer for endpoint 0. EPDR0o holds endpoint 0 receive data other than setup commands. When data is received successfully, EP0oTS in interrupt flag register 0 is set, and the number of receive bytes is indicated in the EP0o receive data size register. After the data has been read, setting EP0oRDFN in the trigger register enables the next packet to be received.
Bit 7 to 0 Bit Name D7 to D0 Initial Value All 0 R/W R Description Data register for control-out transfer
22.3.12 EP0s Data Register (EPDR0s) EPDR0s is an 8-byte FIFO buffer specifically for receiving endpoint 0 setup commands. Only the setup command to be processed by the application is received. When command data is received successfully, the SETUPTS bit in interrupt flag register 0 is set. As a latest setup command must be received in high priority, if data is left in this buffer, it will be overwritten with new data. If reception of the next command is started while the current command is being read, command reception has priority, the read by the application is forcibly stopped, and the read data is invalid.
Bit 7 to 0 Bit Name D7 to D0 Initial Value All 0 R/W R Description Data register for storing the setup command at the control-out transfer
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Section 22 USB Function Module (USB)
22.3.13 EP1 Data Register (EPDR1) EPDR1 is a 128-byte receive FIFO buffer for endpoint 1. EPDR1 has a dual-buffer configuration, and has a capacity of twice the maximum packet size. When one packet of data is received successfully, EP1FULL in interrupt flag register 0 is set, and the number of receive bytes is indicated in the EP1 receive data size register. After the data has been read, the buffer that was read is enabled to receive data again by writing 1 to the EP1RDFN bit in the trigger register. The receive data in this FIFO buffer can be transferred by the DTC. This FIFO buffer can be initialized by means of EP1CLR in the FCLR register.
Bit 7 to 0 Bit Name D7 to D0 Initial Value All 0 R/W R Description Data register for endpoint 1 transfer
22.3.14 EP2 Data Register (EPDR2) EPDR2 is a 128-byte transmit FIFO buffer for endpoint 2. EPDR2 has a dual-buffer configuration, and has a capacity of twice the maximum packet size. When transmit data is written to this FIFO buffer and EP2PKTE in the trigger register is set, one packet of transmit data is fixed, and the dual-FIFO buffer is switched over. The transmit data for this FIFO buffer can be transferred by the DTC. This FIFO buffer can be initialized by means of EP2CLR in the FCLR register.
Bit 7 to 0 Bit Name D7 to D0 Initial Value R/W Description Data register for endpoint 2 transfer
Undefined W
22.3.15 EP3 Data Register (EPDR3) EPDR3 is an 8-byte transmit FIFO buffer for endpoint 3. EPDR3 holds one packet of transmit data for the interrupt transfer of endpoint 3. Transmit data is fixed by writing one packet of data and setting EP3PKTE in the trigger register. When an ACK handshake is returned from the host after one packet of data has been transmitted successfully, EP3TS in interrupt flag register 0 is set. This FIFO buffer can be initialized by means of EP3CLR in the FCLR register.
Bit 7 to 0 Bit Name D7 to D0 Initial Value R/W Description Data register for endpoint 3 transfer
Undefined W
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Section 22 USB Function Module (USB)
22.3.16 EP0o Receive Data Size Register (EPSZ0o) EPSZ0o indicates the number of bytes received at endpoint 0 from the host.
Bit 7 to 0 Bit Name Initial Value All 0 R/W R Description Number of receive data for endpoint 0
22.3.17 EP1 Receive Data Size Register (EPSZ1) EPSZ1 is a receive data size resister for endpoint 1. EPSZ1 indicates the number of bytes received from the host. The FIFO for endpoint 1 has a dual-buffer configuration. The size of the received data indicated by this register is the size of the currently selected side (can be read by CPU).
Bit 7 to 0 Bit Name Initial Value All 0 R/W R Description Number of received bytes for endpoint 1
22.3.18 Trigger Register (TRG) TRG generates one-shot triggers to control the transfer sequence for each endpoint.
Bit 7 6 Bit Name EP3 PKTE Initial Value Undefined Undefined R/W W Description Reserved The initial value should not be changed. EP3 Packet Enable After one packet of data has been written to the endpoint 3 transmit FIFO buffer, the transmit data is fixed by writing 1 to this bit. 5 EP1 RDFN Undefined W EP1 Read Complete Write 1 to this bit after one packet of data has been read from the endpoint 1 FIFO buffer. The endpoint 1 receive FIFO buffer has a dual-buffer configuration. Writing 1 to this bit initializes the FIFO that was read, enabling the next packet to be received.
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Section 22 USB Function Module (USB)
Bit 4
Bit Name EP2 PKTE
Initial Value Undefined
R/W W
Description EP2 Packet Enable After one packet of data has been written to the endpoint 2 transmit FIFO buffer, the transmit data is fixed by writing 1 to this bit.
3 2
Undefined
W
Reserved The initial value should not be changed. EP0s Read Complete Write 1 to this bit after data for the EP0s command FIFO has been read. Writing 1 to this bit enables transfer of data in the following data stage. A NAK handshake is returned in response to transfer requests from the host in the data stage until 1 is written to this bit.
EP0s RDFN Undefined
1
EP0o RDFN Undefined
W
EP0o Read Complete Writing 1 to this bit after one packet of data has been read from the endpoint 0 transmit FIFO buffer initializes the FIFO buffer, enabling the next packet to be received.
0
EP0i PKTE
Undefined
W
EP0i Packet Enable After one packet of data has been written to the endpoint 0 transmit FIFO buffer, the transmit data is fixed by writing 1 to this bit.
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Section 22 USB Function Module (USB)
22.3.19 Data Status Register (DASTS) DASTS indicates whether the transmit FIFO buffers contain valid data. A bit in this register is set when data is written to the corresponding FIFO buffer and the packet enable bit is set. A bit in this register is cleared when all data has been transmitted to the host, or when the FIFO clear bit for the corresponding endpoint in the FIFO clear register (FCLR) is set.
Bit 7 6 5 Bit Name EP3 DE Initial Value 0 0 0 R/W R R R Description Reserved These bits are always read as 0. The initial value should not be changed. EP3 Data Present This bit is set when the endpoint 3 FIFO buffer contains valid data. 4 EP2 DE 0 R EP2 Data Present This bit is set when the endpoint 2 FIFO buffer contains valid data. 3 to 1 0 EP0i DE All 0 0 R R Reserved These bits are always read as 0. EP0i Data Present This bit is set when the endpoint 0 FIFO buffer contains valid data.
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Section 22 USB Function Module (USB)
22.3.20 FIFO Clear Register (FCLR) FCLR is a register to initialize the FIFO buffers for each endpoint. Writing 1 to a bit clears all the data in the corresponding FIFO buffer. Note that the corresponding interrupt flag is not cleared. Do not clear a FIFO buffer during transfer.
Bit 7 6 Bit Name EP3 CLR Initial Value Undefined Undefined R/W W Description Reserved The initial value should not be changed. EP3 Clear Writing 1 to this bit initializes the endpoint 3 transmit FIFO buffer. 5 EP1 CLR Undefined W EP1 Clear Writing 1 to this bit initializes both sides of the endpoint 1 receive FIFO buffer. 4 EP2 CLR Undefined W EP2 Clear Writing 1 to this bit initializes both sides of the endpoint 2 transmit FIFO buffer. 3 to 1 0 EP0i CLR All 0 Undefined R W Reserved The initial value should not be changed. EP0i Clear Writing 1 to this bit initializes the endpoint 0 transmit FIFO buffer.
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Section 22 USB Function Module (USB)
22.3.21 DTC Transfer Setting Register (DMA) DMA supports the DTC transfer that can be carried out between the endpoint 1 and 2 data registers and memory by the data transfer controller (DTC). Dual address transfer is performed in byte units. To initiate transfer by the DTC, necessary settings must be made to the DTC in addition to the setting of this register.
Bit 7 to 3 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The initial value should not be changed. 2 PULLUP_E 0 R/W PULLUP Enable This pin performs pull-up control for the D+ pin, with use of PUPDPLS as the pull-up control pin. 0: D+ pull-up is disabled. (The PULLUP pin is driven low.) 1: D+ pull-up is enabled. (The PULLUP pin is driven high.)
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Section 22 USB Function Module (USB)
Bit 1
Bit Name EP2DMAE
Initial Value 0
R/W R/W
Description Endpoint 2 DTC Transfer Enable When this bit is set, DTC transfer is enabled from memory to the endpoint 2 transmit FIFO buffer. If there is at least one byte of space in the FIFO buffer, the DTC start interrupt signal (USBINTN1) is asserted. In DTC transfer, when 64 bytes are written to the FIFO buffer the EP2 packet enable bit is set automatically, allowing 64 bytes of data to be transferred, and if there is still space in the other of the two FIFOs, the DTC start interrupt signal (USBINTN1) is asserted again. However, if the size of the data packet to be transmitted is less than 64 bytes, the EP2 packet enable bit is not set automatically, and so should be set by the CPU on a DTC transfer end interrupt. As EP2-related interrupt requests to the CPU are not automatically masked, interrupt requests should be masked as necessary in the interrupt enable register. * Operating procedure 1. Set the number of transfers in the DTC. 2. Set the DTC to be activated by USBINTN1. 3. Write 1 to this bit. 4. Activate the DTC. 5. DTC transfer is performed. 6. DTC transfer end interrupt is generated. 7. Write 0 to the EP1DMAE bit in DMA. 8. Write 0 to the EP1FULL bit in IFR0. See section 22.8.3, DTC Transfer for Endpoint 2.
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Section 22 USB Function Module (USB)
Bit 0
Bit Name EP1DMAE
Initial Value 0
R/W R/W
Description Endpoint 1 DTC Transfer Enable When this bit is set, the DTC start interrupt signal (USBINTN0) is asserted and DTC transfer is enabled from the endpoint 1 receive FIFO buffer to memory. If there is at least one byte of receive data in the FIFO buffer, the DTC start interrupt signal (USBINTN0) is asserted. In DTC transfer, when all the received data is read, EP1 is automatically read and the completion trigger operates. EP1-related interrupt requests to the CPU are not automatically masked. * Operating procedure: 1. Set the number of transfers in the DTC. 2. Set the DTC to be activated by USBINTN0. 3. Write 1 to this bit. 4. Activate the DTC. 5. DTC transfer is performed. 6. DTC transfer end interrupt is generated. 7. Write 0 to the EP2DMAE bit in DMA. 8. Write 0 to the EP2EMPTY bit in IFR0. See section 22.8.2, DTC Transfer for Endpoint 1.
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Section 22 USB Function Module (USB)
22.3.22 Endpoint Stall Register (EPSTL) The bits in EPSTL are used to forcibly stall the endpoints on the application side. While a bit is set to 1, the corresponding endpoint returns a stall handshake to the host. The stall bit for endpoint 0 is cleared automatically on reception of 8-byte command data for which decoding is performed by the function and the EP0 STL bit is cleared. When the SETUPTS flag in the IFR0 register is set to 1, writing 1 to the EP0 STL bit is ignored. For detailed operation, see section 22.7, Stall Operations.
Bit 7 to 4 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The initial value should not be changed. 3 EP3STL 0 R/W EP3 Stall When this bit is set to 1, endpoint 3 is placed in the stall state. 2 EP2STL 0 R/W EP2 Stall When this bit is set to 1, endpoint 2 is placed in the stall state. 1 EP1STL 0 R/W EP1 Stall When this bit is set to 1, endpoint 1 is placed in the stall state. 0 EP0STL 0 R/W EP0 Stall When this bit is set to 1, endpoint 0 is placed in the stall state.
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Section 22 USB Function Module (USB)
22.3.23 Configuration Value Register (CVR) This register stores the Configuration, Interface, or Alternate set value when the Set Configuration or Set Interface command from the host is correctly received.
Bit 7 6 5 4 3 Bit Name CNFV1 CNFV0 INTV1 INTV0 0 R All 0 R Initial Value All 0 R/W R Description These bits store Configuration Setting value when they receive Set Configuration command. CNFV is updated when the SETC bit in IFR2 is set to 1. These bits store Interface Setting value when they receive Set Interface command. INTV is updated when the SETI bit in IFR2 is set to 1. Reserved This bit is always read as 0. The initial value should not be changed. 2 1 0 ALTV2 ALTV1 ALTV0 0 0 0 R R R These bits store Alternate Setting value when they receive Set Interface command. ALTV2 to ALTV0 are updated when the SETI bit in IFR2 is set to 1.
22.3.24 Control Register (CTLR) This register sets functions by setting bits ASCE, RSME, and, RWUPS.
Bit 7 to 5 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The initial value should not be changed. 4 RWUPS 0 R Remote Wakeup Status This status bit indicates remote wakeup command from USB host is enabled or disabled. This bit is set to 0 when remote wakeup command from UBM host is disabled by Device_Remote_Wakeup due to Set Feature or Clear Feature request. This bit is set to 1 when remote wakeup command is enabled.
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Section 22 USB Function Module (USB)
Bit 3
Bit Name RSME
Initial Value 0
R/W R/W
Description Resume Enable This bit releases the suspend state (or executes remote wakeup). When RSME is set to 1, resume request starts. If RSME is once set to 1, clear this bit to 0 again afterwards. In this case, the value 1 set to RSME must be kept for at least one clock period of 12-MHz clock.
2
0
R
Reserved This bit is always read as 0. The initial value should not be changed.
1
ASCE
0
R/W
Automatic Stall Clear Enable Setting the ASCE bit to 1 automatically clears the stall setting bit (the EPxSTL (x = 1, 2, or 3) bit in EPSTLR0 or EPSTR1) of the end point that has returned the stall handshake to the host. The automatic stall clear enable is common to the all end points. Thus the individual control of the end point is not possible. When the ASCE bit is set to 0, the stall setting bit is not automatically cleared. This bit must be released by the users. To enable this bit, make sure that the ASCE bit should be set to 1 before the EPxSTL (x = 1, 2, or 3) bit in EPSTL is set to 1.
0
0
R
Reserved This bit is always read as 0. The initial value should not be changed.
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Section 22 USB Function Module (USB)
22.3.25 Endpoint Information Register (EPIR) This register sets the information for each endpoint. Each endpoint needs five bytes to store the information. Writing data should be done in sequence starting at logical endpoint 0. Do not write data of more than 50 bytes (five bytes multiplied by ten endpoints) to this register. The information should be written to this register only once at a power-on reset and no data should be written after that. Description of writing data for one endpoint is shown below. Although this register consists of one register to which data is written sequentially for one address, the write data for the endpoint 0 is described as EPIR00 to EPIR05 (EPIR endpoint number in write order) to make the explanation understood easier. Write should start at EPIR00. * EPIR00
Bit 7 to 4 Bit Name D7 to D4 Initial Value Undefined R/W W Description Endpoint Number [Enable setting range] 0 to 3 3, 2 D3, D2 Undefined W Endpoint Configuration Number [Enable setting range] 0 or 1 1, 0 D1, D0 Undefined W Endpoint Interface Number [Enable setting range] 0 to 3
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Section 22 USB Function Module (USB)
* EPIR01
Bit 7, 6 Bit Name D7, D6 Initial Value Undefined R/W W Description Endpoint Alternate Number [Possible setting range] 0 or 1 5, 4 D5, D4 Undefined W Endpoint Transmission [Possible setting range] 0: Control 1: Setting prohibited 2: Bulk 3: Interrupt 3 D3 Undefined W Endpoint Transmission Direction [Possible setting range] 0: Out 1: In 2 to 0 D2 to D0 Undefined W Reserved [Possible setting range] Fixed to 0.
* EPIR02
Bit 7 to 1 Bit Name D7 to D1 Initial Value Undefined R/W W Description Endpoint Maximum Packet Size [Possible setting range] 0 to 64 0 D0 Undefined W Reserved [Possible setting range] Fixed to 0.
* EPIR03
Bit 7 to 0 Bit Name D7 to D0 Initial Value Undefined R/W W Description Reserved [Possible setting range] Fixed to 0.
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Section 22 USB Function Module (USB)
* EPIR04
Bit 7 to 0 Bit Name D7 to D0 Initial Value Undefined R/W W Description Endpoint FIFO Number [Possible setting range] 0 to 3
The endpoint number is the endpoint number the USB host uses. The endpoint FIFO number corresponds to the endpoint number described in this manual. Thus data transfer between the USB host and the endpoint FIFO can be enabled by putting the endpoint number and the endpoint FIFO number in one-to-one correspondence. Note that the setting value is subject to a limitation described below. Since each endpoint FIFO number is optimized by the exclusive software that corresponds to the transfer system, direction, and the maximum packet size, make sure to set the endpoint FIFO number to the data described in table 22.2. 1. The endpoint FIFO number 1 cannot designate other than the maximum packed size of 8 bytes, control transfer method, and out transfer direction. 2. The endpoint number 0 and the endpoint FIFO number must have one-on one relationship. 3. The maximum packet size for the endpoint FIFO number 0 is 8 bytes only. 4. The endpoint FIFO number 0 can specify only the maximum packet size and the data for the rest should be all 0. 5. The maximum packet size for the endpoint FIFO numbers 1 and 2 is limited to 64 bytes. 6. The maximum packet size for the endpoint FIFO numbers 3 is limited to 8 bytes. 7. The maximum number of endpoint information setting is ten. 8. Up to ten endpoint information setting should be made. 9. Write 0 to the endpoints not in use. Table 22.2 shows the example of limitations for the maximum packet size, the transfer method, and the transfer direction. Table 22.2 Example of Limitations for Setting Values
Endpoint FIFO Number 0 1 2 3 Maximum Packet Size 8 bytes 64 bytes 64 bytes 8 bytes Transfer Method Control Bulk Bulk Interrupt Transfer Direction Out In In
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Section 22 USB Function Module (USB)
Table 22.3 shows a specific example of setting. Table 22.3 Example of Setting
Endpoint Number Conf. 0 1 2 3 1 1 1 1 1 Int. 0 0 0 1 1 Alt. 0 0 0 0 1 Transfer Method Control Bulk Bulk Interrupt Transfer Direction In/Out Out In In Maximum Packet Size 8 bytes 64 bytes 64 bytes 8 bytes Endpoint FIFO Number 0 1 2 3
N 0 1 2 3 4 5 6 7 8 9
EPIR[N]0 00 14 24 34 00 00 00 00 00 00
EPIR[N]1 00 20 28 38 00 00 00 00 00 00
EPIR[N]2 10 80 80 10 00 00 00 00 00 00
EPIR[N]3 00 00 00 00 00 00 00 00 00 00
EPIR[N]4 00 01 02 03 00 00 00 00 00 00
Configuration 1
Interface 0
Alternate Setting 0
Endpoint Number 0 1 2 3
Endpoint FIFO Number 0 1 2 3
Attribute Control BulkOut BulkIn InterruptIn
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Section 22 USB Function Module (USB)
22.3.26
Transceiver Test Register 0 (TRNTREG0)
TRNTREG0 controls the built-in transceiver output signals. Setting the PTSTE bit to 1 specifies the transceiver output signals (USD+ and USD-) arbitrarily. Table 22.4 shows the relationship between TRNTREG0 setting and pin output.
Bit 7 Bit Name PTSTE Initial Value 0 R/W R/W Description Pin Test Enable Enables the test control for the built-in transceiver output pins (USD+ and USD-). 6 to 4 All 0 R Reserved These bits are always read as 0. The initial value should not be changed. 3 2 1 0 SUSPEND txenl txse0 txdata 0 0 0 0 R/W R/W R/W R/W Built-In Transceiver Output Signal Setting SUSPEND: Sets the (SUSPEND) signal of the built-in transceiver. txenl: txse0: txdata: Sets the output enable (txenl) signal of the built-in transceiver. Sets the Signal-ended 0 (txse0) signal of the built-in transceiver. Sets the (txdata) signal of the built-in transceiver.
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Section 22 USB Function Module (USB)
Table 22.4 Relationship between TRNTREG0 Setting and Pin Output
Pin Input VBUS 0 1 1 1 1 1 PTSTE X 0 1 1 1 1 Register Setting txenl X X 0 0 0 1 txse0 X X 0 0 1 X txdata X X 0 1 x X USD+ Hi-Z 0 1 0 Hi-Z Pin Output USDHi-Z 1 0 0 Hi-Z
[Legend] X: Don't care. : Cannot be controlled. Indicates state in normal operation according to the USB operation and port settings.
22.3.27 Transceiver Test Register 1 (TRNTREG1) TRNTREG1 is a test register that can monitor the built-in transceiver input signal. Setting bits PTSTE and txenl in TRNTREG0 to 1 enables monitoring the built-in transceiver input signal. Table 22.5 shows the relationship between pin input and TRNTREG1 monitoring value.
Bit 7 to 3 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The initial value should not be changed. 2 1 0 xver_data dpls dmns * * * R R R Built-In Transceiver Input Signal Monitor xver_data: Monitors the differential input level (xver_data) signal of the built-in transceiver. dpls: dmns: Note: * Monitors the USD+ (dpls) signal of the builtin transceiver. Monitors the USD- (dmns) signal of the builtin transceiver.
Determined by the state of pins, VBUS, USD+, and USD-
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Section 22 USB Function Module (USB)
Table 22.5 Relationship between Pin Input and TRNTREG1 Monitoring Value
Register Setting Pin Input TRNTREG1 Monitoring Value
PTSTE
SUSPEND
VBUS
USD+
USD-
xver_data dpls 0 X 0 1 X 0 0 0 0 0 0 0 0 1 1 0 0 1 1 1
dmns Remarks 0 0 1 0 1 0 1 0 1 1
Can be monitored when VBUS = 0 Cannot be monitored when PTSTE = 0 Can be monitored when PTSTE = 1
0 1 1 1 1 1 1 1 1 1
X 0 0 0 0 1 1 1 1 X
X 1 1 1 1 1 1 1 1 0
X 0 0 1 1 0 0 1 1 X
X 0 1 0 1 0 1 0 1 X
[Legend] X: Don't care.
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Section 22 USB Function Module (USB)
22.4
Interrupt Sources
This module has five interrupt signals. Table 22.6 shows the interrupt sources and their corresponding interrupt request signals. The USBINTN interrupt signals are active low and can only be detected by level sensing. Table 22.6 Interrupt Sources
Register IFR0 Bit 0 1 2 3 4 Bulk_in transfer (EP2) Transfer Mode Control transfer (EP0) Interrupt Source EP0i_TS* EP0i_TR* EP0o_TS* SETUP_TS* EP2_EMPTY Description EP0i transfer complete EP0i transfer request EP0o receive complete Setup command receive complete EP2 FIFO empty Interrupt Request Signal USBINTN2 or USBINTN3 USBINTN2 or USBINTN3 USBINTN2 or USBINTN3 USBINTN2 or USBINTN3 USBINTN2 or USBINTN3 USBINTN2 or USBINTN3 USBINTN2 or USBINTN3 USBINTN2 or USBINTN3 DTC Activation x x x x USBINTN1
5 6 Bulk_out transfer (EP1) Status Status
EP2_TR EP1_FULL
EP2 transfer request EP1 FIFO Full
x USBINTN0
7 IFR1 0 1 2 3 4 5 6 7
BRST VBUSF
Bus reset
x x x x x --
USB disconnection USBINTN2 or detection USBINTN3 EP3 transfer complete EP3 transfer request VBUS connection status -- USBINTN2 or USBINTN3 USBINTN2 or USBINTN3 -- --
Interrupt_in EP3_TS transfer (EP3) EP3_TR Status -- VBUSMN Reserved
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Section 22 USB Function Module (USB) Transfer Mode Status Interrupt Source SETI SETC -- Status SOF CFDN SURSF Interrupt Request Signal
Register IFR2
Bit 0 1 2 3 4
Description
DTC Activation x x x x x
Set_Interface USBINTN2 or command detection USBINTN3 Set_Configuration USBINTN2 or command detection USBINTN3 SOF interrupt detection USBINTN2 or USBINTN3
Endpoint information USBINTN2 or load end USBINTN3 Suspend/resume detection USBINTN2, USBINTN3, or RESUME -- --
5 6 7 --
SURSS Reserved
Suspend/resume status --
x --
Note:
*
EP0 interrupts must be assigned to the same interrupt request signal.
* USBINTN0 signal DTC start interrupt signal only EP1. See section 22.8, DTC Transfer. * USBINTN1 signal DTC start interrupt signal only EP1. See section 22.8, DTC Transfer. * USBINTN2 signal The USBINTN2 signal requests interrupt sources for which the corresponding bits in interrupt select registers 0 to 2 (ISR0 to ISR2) are cleared to 0. The USBINTN2 is driven low if a corresponding bit in the interrupt flag register is set to 1. * USBINTN3 signal The USBINTN3 signal requests interrupt sources for which the corresponding bits in interrupt select registers 0 to 2 (ISR0 to ISR2) are cleared to 0. The USBINTN3 is driven low if a corresponding bit in the interrupt flag register is set to 1. * RESUME signal The RESUME signal is a resume interrupt signal for canceling software standby mode. The RESUME signal is driven low at the transition to the resume state for canceling software standby mode.
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Section 22 USB Function Module (USB)
22.5
22.5.1
Operation
Operation at Cable Connection
USB function Cable disconnected VBUS pin = 0 V UDC core reset
Application USB module interrupt setting As soon as preparations are completed, enable D+ pull-up in general output port Initial settings
USB cable connection
No
General output port D+ pull-up enabled? Yes Interrupt request IFR1.VBUSF = 1 USB bus connection interrupt Clear VBUSF flag (IFR1.VBUSF)
UDC core reset release
Firmware preparations for start of USB communication
Bus reset reception IFR0.BRST = 1 Bus reset interrupt
Interrupt request
Clear bus reset flag (IFR0.BRST)
Wait for setup command reception complete interrupt
Clear FIFOs (EP0, EP1, EP2, EP3)
Wait for setup command reception complete interrupt
Figure 22.2 Operation at Cable Connection The above flowchart shows the operation in the case of in section 22.9, Example of USB External Circuitry. In applications that do not require USB cable connection to be detected, processing by the USB bus connection interrupt is not necessary. Preparations should be made with the bus-reset interrupt.
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Section 22 USB Function Module (USB)
22.5.2
Operation at Cable Disconnection
USB function Cable connected VBUS pin = 1
Application
USB cable disconnection
VBUS pin = 0
UDC core reset
End
Figure 22.3 Operation at Cable Disconnection The above flowchart shows the operation in section 22.9, Example of USB External Circuitry.
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Section 22 USB Function Module (USB)
22.5.3 (1)
Suspend and Resume Operations
Suspend Operation
When the USB bus enters the suspend state from the non-suspend state, processing should proceed as shown below.
USB function USB cable connected
Application Clear SURSF in IFR2 to 0
Bus idle of 3 ms or more occurs
Check if SURSS in IFR2 is set to 1
Suspend/resume interrupt occurs (IFR2/SURSF = 1)
Remote wakeup enabled? (CTLR/RWUPS = 1?)
No
USBINT2 USBINT3
Yes Check remote-wakeup function enabled Check remote-wakeup function disabled
System needs to enter power-down mode? Yes
No
Need to enter software standby mode? Yes Clear SURSE in IER2 to 0
No
Set SURSE in IER2 to 1
Set SSRSME in IER2 to 1
Clear SSRSME in IER2 to 0
Enter software standby mode
USB module stop
Wait for suspend/ resume interrupt
Figure 22.4 Suspend Operation
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Section 22 USB Function Module (USB)
(2)
Resume Operation from Up-Stream
When the USB bus enters the non-suspend state from the suspend state by resume signal output from up-stream, processing should proceed as shown below.
USB function USB cable connected USB bus in suspend state
Application
Resume interrupts is requested from the up-stream. Suspend/resume interrupt occurs. (IFR2/SURSF = 1)
RESUME Yes Software standby mode ? No
Cancel software standby mode
Oscillation stabilization time has passed?
No
Yes
USB module stopped? Yes Start USB operating clock oscillation Cancel USB module stop
No
Clear SURSF in IFR2 to 0
Check if SURSS in IFR2 is cleared to 0
Set SURSE in IER2 to 1
Clear SSRSME in IER2 to 0
Return to normal state
Figure 22.5 Resume Operation from Up-Stream
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Section 22 USB Function Module (USB)
(3)
Transition from Suspend State to Software Standby Mode and Canceling Software Standby Mode
When the USB bus enters from the suspend state to software standby mode, processing should proceed as shown below. When canceling software standby mode, ensure enough time for the system clock oscillation to be settled.
Transition from suspend state to software standby mode (1) Detect that USB bus is in suspend state (8) Canceling software standby mode
Detect that USB bus is in resume state
(2)
Set SURSF in IFR2 to 1
(9)
RESUME interrupt
(3)
USBINTN interrupt
(10)
Cancel software standby mode Wait for system clock oscillation to be settled
(4)
Clear SURSF in IFR2 to 0 Check if SURSS in IFR2 is set to 1 (11) Clear SURSF in IER2 to 0 Set SSRSME in IER2 to 1 (12) Shift to software standby mode (execute SLEEP instruction)
Clear SURSF in IFR2 to 0 Check if SURSS in IFR2 is cleared to 0
(5)
Set SURSF in IER2 to 1 Clear SSRSME in IER2 to 0
(6)
USB communications can be resumed through USB registers
(7)
Stop all clocks of LSI
Denotation of figures : Operation by firmware setting : Automatic operation by LSI hardware
Figure 22.6 Flow of Transition to and Canceling Software Standby Mode
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Section 22 USB Function Module (USB)
(1) USB bus state Normal (3) USBINTN interrupt Suspend
(8) Resume normal
SURSF
(2)
(4)
(11)
SURSS (4) SSRSME = 1 (5)
(11)
(12)
RESUME interrupt
(9)
Software standby
(6)
(10)
Oscillator USB dedicated clock (cku) Peripheral module clock ()
(7)
(7)
Software standby
Oscillation settling time
Figure 22.7 Timing of Transition to and Canceling Software Standby Mode
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Section 22 USB Function Module (USB)
(4)
Remote-Wakeup Operation
When the USB bus enters the non-suspend (resume) state from the suspend state by the remotewakeup signal output from this function, processing should proceed as shown below.
USB function USB cable connected USB bus in suspend state
Application
Remote wakeup enabled? (CTLR/RWUPS = 1?)
No
Yes Bus wakeup source generated Wait for resume from up-stream
Yes Cancel software standby mode
Software standby mode ? No
Oscillation stabilization time has passed?
No
Yes
USB module stopped? Yes Start USB operating clock oscillation Resume output signal Suspend/resume interrupt occurs. (IFR2/SURSF = 1) Cancel USB module stop
No
Remote wakeup execution (CTLR/RSME= 1) RESUME Clear SURSF in IFR2 to 0
Check if SURSS in IFR2 is cleared to 0
Return to normal state
Figure 22.8 Remote-Wakeup
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Section 22 USB Function Module (USB)
22.5.4
Control Transfer
Control transfer consists of three stages: setup, data (not always included), and status (figure 22.9). The data stage comprises a number of bus transactions. Operation flowcharts for each stage are shown below.
Setup stage Control-in SETUP(0)
DATA0
Data stage IN(1)
DATA1
Status stage ... IN(0/1)
DATA0/1
IN(0)
DATA0
OUT(1)
DATA1
Control-out
SETUP(0)
DATA0
OUT(1)
DATA1
OUT(0)
DATA0
...
OUT(0/1)
DATA0/1
IN(1)
DATA1
No data
SETUP(0)
DATA0
IN(1)
DATA1
Figure 22.9 Transfer Stages in Control Transfer
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Section 22 USB Function Module (USB)
(1)
Setup Stage
USB function SETUP token reception
Application
Receive 8-byte command data in EP0s
Command to be processed by application? Yes Set setup command reception complete flag (IFR0.SETUP TS = 1)
No
Automatic processing by this module
Interrupt request
Clear SETUP TS flag (IFR0.SETUP TS = 0) Clear EP0i FIFO (FCLR.EP0iCLR = 1) Clear EP0o FIFO (FCLR.EP0oCLR = 1)
To data stage
Read 8-byte data from EP0s
Decode command data Determine data stage direction*1
Write 1 to EP0s read complete bit (TRG.EP0s RDFN = 1) *2 To control-in data stage To control-out data stage
Notes: 1. In the setup stage, the application analyzes command data from the host requiring processing by the application, and determines the subsequent processing (for example, data stage direction, etc.). 2. When the transfer direction is control-out, the EP0i transfer request interrupt required in the status stage should be enabled here. When the transfer direction is control-in, this interrupt is not required and should be disabled.
Figure 22.10 Setup Stage Operation
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Section 22 USB Function Module (USB)
(2)
Data Stage (Control-In)
USB function IN token reception
Application From setup stage
1 written to TRG.EP0s RDFN? Yes Valid data in EP0i FIFO? Yes Data transmission to host ACK Set EP0i transmission complete flag (IFR0.EP0i TS = 1)
No NAK
Write data to EP0i data register (EPDR0i)
No NAK
Write 1 to EP0i packet enable bit (TRG.EP0i PKTE = 1)
Interrupt request
Clear EP0i transmission complete flag (IFR0.EP0i TS = 0) Write data to EP0i data register (EPDR0i) Write 1 to EP0i packet enable bit (TRG.EP0i PKTE = 1)
Figure 22.11 Data Stage (Control-In) Operation The application first analyzes command data from the host in the setup stage, and determines the subsequent data stage direction. If the result of command data analysis is that the data stage is intransfer, one packet of data to be sent to the host is written to the FIFO. If there is more data to be sent, this data is written to the FIFO after the data written first has been sent to the host (EP0iTS bit in IFR0 = 1). The end of the data stage is identified when the host transmits an OUT token and the status stage is entered. Note: If the size of the data transmitted by the function is smaller than the data size requested by the host, the function indicates the end of the data stage by returning to the host a packet shorter than the maximum packet size. If the size of the data transmitted by the function is an integral multiple of the maximum packet size, the function indicates the end of the data stage by transmitting a zero-length packet.
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Section 22 USB Function Module (USB)
(3)
Data Stage (Control-Out)
USB function OUT token reception
Application
1 written to TRG.EP0s RDFN? Yes
No NAK
Data reception from host ACK Set EP0o reception complete flag (IFR0.EP0o TS = 1) Interrupt request Clear EP0o reception complete flag (IFR0.EP0o TS = 0) Read data from EP0o receive data size register (EPSZ0o) No NAK
OUT token reception
1 written to TRG.EP0o RDFN? Yes
Read data from EP0o data register (EPDR0o)
Write 1 to EP0o read complete bit (TRG.EP0o RDFN = 1)
Figure 22.12 Data Stage (Control-Out) Operation The application first analyzes command data from the host in the setup stage, and determines the subsequent data stage direction. If the result of command data analysis is that the data stage is outtransfer, the application waits for data from the host, and after data is received (EP0oTS bit in IFR0 = 1), reads data from the FIFO. Next, the application writes 1 to the EP0o read complete bit, empties the receive FIFO, and waits for reception of the next data. The end of the data stage is identified when the host transmits an IN token and the status stage is entered.
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Section 22 USB Function Module (USB)
(4)
Status Stage (Control-In)
USB function OUT token reception
Application
0-byte reception from host ACK Set EP0o reception complete flag (IFR0.EP0o TS = 1) Interrupt request Clear EP0o reception complete flag (IFR0.EP0o TS = 0) Write 1 to EP0o read complete bit (TRG.EP0o RDFN = 1)
End of control transfer
End of control transfer
Figure 22.13 Status Stage (Control-In) Operation The control-in status stage starts with an OUT token from the host. The application receives 0byte data from the host, and ends control transfer.
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Section 22 USB Function Module (USB)
(5)
Status Stage (Control-Out)
USB function IN token reception
Application
Valid data in EP0i FIFO? Yes 0-byte transmission to host ACK Set EP0i transmission complete flag (IFR0.EP0i TS = 1)
No NAK
Interrupt request
Clear EP0i transfer request flag (IFR0.EP0i TR = 0)
Write 1 to EP0i packet enable bit (TRG.EP0i PKTE = 1)
Interrupt request
Clear EP0i transmission complete flag (IFR0.EP0i TS = 0)
End of control transfer
End of control transfer
Figure 22.14 Status Stage (Control-Out) Operation The control-out status stage starts with an IN token from the host. When an IN-token is received at the start of the status stage, there is not yet any data in the EP0i FIFO, and so an EP0i transfer request interrupt is generated. The application recognizes from this interrupt that the status stage has started. Next, in order to transmit 0-byte data to the host, 1 is written to the EP0i packet enable bit but no data is written to the EP0i FIFO. As a result, the next IN token causes 0-byte data to be transmitted to the host, and control transfer ends. After the application has finished all processing relating to the data stage, 1 should be written to the EP0i packet enable bit.
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Section 22 USB Function Module (USB)
22.5.5
EP1 Bulk-Out Transfer (Dual FIFOs)
USB function
OUT token reception
Application
FIFO FULL processing
Either of EP1 FIFOs empty? Yes
No
NAK
Read EP1 receive data size register (EPSZ1)
Interrupt request
Read EP1 data register (EPDR1)
Data reception from host
ACK
Set EP1 read complete bit (TRG.EP1 RDFN = 1)
Set EP1 FIFO full status (IFR0.EP1 FULL = 1)
Clear EP1 FIFO full status (IFR0.EP1 FULL = 0)
Resume
Figure 22.15 EP1 Bulk-Out Transfer Operation EP1 has two 64-byte FIFOs, but the user can receive data and read receive data without being aware of this dual-FIFO configuration. When one FIFO is full after reception is completed, the EP1FULL bit in IFR0 is set. After the first receive operation into one of the FIFOs when both FIFOs are empty, the other FIFO is empty, and so the next packet can be received immediately. When both FIFOs are full, NAK is returned to the host automatically. When reading of the receive data is completed following data reception, 1 is written to the EP1RDFN bit in TRG and 0 is written to the EP1FULL bit in IFR0. This operation empties the FIFO that has just been read, and makes it ready to receive the next packet.
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Section 22 USB Function Module (USB)
22.5.6
EP2 Bulk-In Transfer (Dual FIFOs)
USB function
IN token reception
Application
Transfer processing
Valid data in either of EP2 FIFOs?
No
Interrupt request
NAK Yes
Clear EP2 transfer request flag (IFR0.EP2 TR = 0)
Data transmission to host
Enable EP2 FIFO empty interrupt (IER0.EP2 EMPTY = 1)
ACK
Resume
No
Either of EP2 FIFOs empty?
Transfer data set processing
Yes
Interrupt request Set EP2 empty status (IFR0.EP2 EMPTY = 1)
Write one packet of data to EP2 data register (EPDR2)
Set EP2 packet enable bit (TRG.EP2 PKTE = 1)
Clear EP2 empty status (TRG.EP2 EMPTY = 0)
Resume
Figure 22.16 EP2 Bulk-In Transfer Operation EP2 has two 64-byte FIFOs, but the user can transmit data and write transmit data without being aware of this dual-FIFO configuration. However, one data write is performed for one FIFO. For example, even if both FIFOs are empty, it is not possible to perform EP2PKTE at one time after consecutively writing 128 bytes of data. EP2PKTE must be performed for each 64-byte write.
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Section 22 USB Function Module (USB)
When performing bulk-in transfer, as there is no valid data in the FIFOs on reception of the first IN token, an EP2TR bit interrupt in IFR0 is requested. With this interrupt, 1 is written to the EP2EMPTY bit in IER0, and the EP2 FIFO empty interrupt is enabled. At first, both EP2 FIFOs are empty, and so an EP2 FIFO empty interrupt is generated immediately. The data to be transmitted is written to the data register using this interrupt. After the first transmit data write for one FIFO, the other FIFO is empty, and so the next transmit data can be written to the other FIFO immediately. When both FIFOs are full, EP2 EMPTY is cleared to 0. If at least one FIFO is empty, the EP2EMPTY bit in IFR0 is set to 1. When ACK is returned from the host after data transmission is completed, the FIFO used in the data transmission becomes empty. If the other FIFO contains valid transmit data at this time, transmission can be continued. When transmission of all data has been completed, write 0 to the EP2EMPTY bit in IER0 and disable interrupt requests.
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Section 22 USB Function Module (USB)
22.5.7
EP3 Interrupt-In Transfer
USB function
Application
Is there data for transmission to host? IN token reception Yes Write data to EP3 data register (EPDR3) Valid data in EP3FIFO? Yes Data transmission to host ACK Set EP3 transmission complete flag (IFR1.EP3 TS = 1) Interrupt request Clear EP3 transmission complete flag (IFR1.EP3 TS = 0) No NAK Write 1 to EP3 packet enable bit (TRG.EP3 PKTE = 1)
No
Is there data for transmission to host? Yes Write data to EP3 data register (EPDR3) Write 1 to EP3 packet enable bit (TRG.EP3 PKTE = 1)
No
Note: This flowchart shows just one example of interrupt transfer processing. Other possibilities include an operation flow in which, if there is data to be transferred, the EP3 DE bit in the data status register is referenced to confirm that the FIFO is empty, and then data is written to the FIFO.
Figure 22.17 Operation of EP3 Interrupt-In Transfer
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Section 22 USB Function Module (USB)
22.6
Processing of USB Standard Commands and Class/Vendor Commands
Processing of Commands Transmitted by Control Transfer
22.6.1
A command transmitted from the host by control transfer may require decoding and execution of command processing on the application side. Whether command decoding is required on the application side is indicated in table 22.7 below. Table 22.7 Command Decoding on Application Side
Decoding not Necessary on Application Side Clear Feature Get Configuration Get Interface Get Status Set Address Set Configuration Set Feature Set Interface Decoding Necessary on Application Side Get Descriptor Class/Vendor command Set Descriptor Sync Frame
If decoding is not necessary on the application side, command decoding and data stage and status stage processing are performed automatically. No processing is necessary by the user. An interrupt is not generated in this case. If decoding is necessary on the application side, this module stores the command in the EP0s FIFO. After reception is completed successfully, the IFR0/SETUP TS flag is set and an interrupt request is generated. In the interrupt routine, eight bytes of data must be read from the EP0s data register (EPDR0s) and decoded by firmware. The necessary data stage and status stage processing should then be carried out according to the result of the decoding operation.
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Section 22 USB Function Module (USB)
22.7
22.7.1
Stall Operations
Overview
This section describes stall operations in this module. There are two cases in which the USB function module stall function is used: * When the application forcibly stalls an endpoint for some reason * When a stall is performed automatically within the USB function module due to a USB specification violation The USB function module has internal status bits that hold the status (stall or non-stall) of each endpoint. When a transaction is sent from the host, the module references these internal status bits and determines whether to return a stall to the host. These bits cannot be cleared by the application; they must be cleared with a Clear Feature command from the host. However, the internal status bit for EP0 is automatically cleared only when the setup command is received. 22.7.2 Forcible Stall by Application
The application uses the EPSTL register to issue a stall request for the USB function module. When the application wishes to stall a specific endpoint, it sets the corresponding bit in EPSTL (11 in figure 22.18). The internal status bits are not changed at this time. When a transaction is sent from the host for the endpoint for which the EPSTL bit was set, the USB function module references the internal status bit, and if this is not set, references the corresponding bit in EPSTL (1-2 in figure 22.18). If the corresponding bit in EPSTL is set, the USB function module sets the internal status bit and returns a stall handshake to the host (1-3 in figure 22.18). If the corresponding bit in EPSTL is not set, the internal status bit is not changed and the transaction is accepted. Once an internal status bit is set, it remains set until cleared by a Clear Feature command from the host, without regard to the EPSTL register. Even after a bit is cleared by the Clear Feature command (3-1 in figure 22.18), the USB function module continues to return a stall handshake while the bit in EPSTL is set, since the internal status bit is set each time a transaction is executed for the corresponding endpoint (1-2 in figure 22.18). To clear a stall, therefore, it is necessary for the corresponding bit in EPSTL to be cleared by the application, and also for the internal status bit to be cleared with a Clear Feature command (2-1, 2-2, and 2-3 in figure 22.18).
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Section 22 USB Function Module (USB)
(1) Transition from normal operation to stall (1-1) USB Internal status bit 0 EPSTL 01 1. 1 written to EPSTL by application
(1-2) Reference Transaction request Internal status bit 0 EPSTL 1 1. IN/OUT token received from host 2. EPSTL referenced
(1-3) Stall STALL handshake Internal status bit 01 To (2-1) or (3-1) (2) When Clear Feature is sent after EPSTL is cleared (2-1) Transaction request Internal status bit 1 EPSTL 10 EPSTL 1
1. 1 set in EPSTL 2. Internal status bit set to 1 3. Transmission of STALL handshake
1. EPSTL cleared to 0 by application 2. IN/OUT token received from host 3. Internal status bit already set to 1 4. EPSTL not referenced 5. Internal status bit not changed
(2-2) STALL handshake Internal status bit 1 EPSTL 0 1. Transmission of STALL handshake
(2-3) Clear Feature command Internal status bit 10 EPSTL 0 1. Internal status bit cleared to 0
Normal status restored (3) When Clear Feature is sent before EPSTL is cleared to 0 (3-1) Clear Feature command Internal status bit 10 To (1-2) EPSTL 1 1. Internal status bit cleared to 0 2. EPSTL not changed
Figure 22.18 Forcible Stall by Application
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Section 22 USB Function Module (USB)
22.7.3
Automatic Stall by USB Function Module
When a stall setting is made with the Set Feature command, or in the event of a USB specification violation, the USB function module automatically sets the internal status bit for the relevant endpoint without regard to the EPSTL register, and returns a stall handshake (1-1 in figure 22.19). Once an internal status bit is set, it remains set until cleared by a Clear Feature command from the host, without regard to the EPSTL register. After a bit is cleared by the Clear Feature command, EPSTL is referenced (3-1 in figure 22.19). The USB function module continues to return a stall handshake while the internal status bit is set, since the internal status bit is set even if a transaction is executed for the corresponding endpoint (2-1 and 2-2 in figure 22.19). To clear a stall, therefore, the internal status bit must be cleared with a Clear Feature command (3-1 in figure 22.19). If set by the application, EPSTL should also be cleared (2-1 in figure 22.19).
(1) Transition from normal operation to stall (1-1) STALL handshake Internal status bit 01 To (2-1) or (3-1) EPSTL 0 1. In case of USB specification violation, etc., USB function module stalls endpoint automatically
(2) When transaction is performed when internal status bit is set, and Clear Feature is sent (2-1) Transaction request Internal status bit 1 EPSTL 0 1. EPSTL cleared to 0 by application 2. IN/OUT token received from host 3. Internal status bit already set to 1 4. EPSTL not referenced 5. Internal status bit not changed 1. Transmission of STALL handshake
(2-2) STALL handshake Internal status bit 1 EPSTL 0
Stall status maintained (3) When Clear Feature is sent before transaction is performed (3-1) Clear Feature command Internal status bit 10 EPSTL 0 1. Internal status bit cleared to 0 2. EPSTL not changed
Normal status restored
Figure 22.19 Automatic Stall by USB Function Module
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Section 22 USB Function Module (USB)
22.8
22.8.1
DTC Transfer
Overview
DTC transfer can be performed for endpoints 1 and 2 in this module. Note that longword data cannot be transferred. When endpoint 1 holds at least one byte of valid receive data, a DTC request for endpoint 1 is generated. When endpoint 2 holds no valid data, a DTC request for endpoint 2 is generated. If the DTC transfer is enabled by setting the EP1DMAE bit in the DTC transfer setting register to 1, zero-length data reception at endpoint 1 is ignored. When the DTC transfer is enabled, the RDFN bit for EP1 and PKTE bit for EP2 do not need to be set to 1 in TRG (note that the PKTE bit must be set to 1 when the transfer data is less than the maximum number of bytes). When all the data received at EP1 is read, the FIFO automatically enters the EMPTY state. When the maximum number of bytes (64 bytes) are written to the EP2 FIFO, the FIFO automatically enters the FULL state, and the data in the FIFO can be transmitted (see figures 22.20 and 22.21). Since the request for a DTC transfer end interrupt is not automatically cleared, it should be cleared within the interrupt processing.
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Section 22 USB Function Module (USB)
22.8.2
DTC Transfer for Endpoint 1
When the data received at EP1 is transferred by the DTC, the USB function module automatically performs the same processing as writing 1 to the RDFN bit in TRG if the currently selected FIFO becomes empty. Accordingly, in DTC transfer, do not write 1 to the RDFN bit in TRG. If the user writes 1 to the RDFN bit in DTC transfer, correct operation cannot be guaranteed. To end the DTC transfer, write 0 to the EP1FULL bit in IFR0, after clearing the EP1DMAE bit in DMA to 0 within the processing routine for a DTC transfer end interrupt. If this procedure is omitted, the DTC transfer end interrupt is not cleared. To perform the DTC transfer again, in addition to the said procedure, set the number of transfers in the DTC, set the interrupt source, and then set the EP1DMAE bit in DMA to 1. Figure 22.20 shows an example of receiving 150 bytes of data from the host. In this case, internal processing which is the same as writing 1 to the RDFN bit in TRG is automatically performed three times. This internal processing is performed when the currently selected data FIFO becomes empty. Accordingly, this processing is automatically performed both when 64-byte data is sent and when data less than 64 bytes is sent.
64 bytes
64 bytes
22 bytes
RDFN (Automatically performed)
RDFN RDFN (Automatically (Automatically performed) performed)
Figure 22.20 RDFN Bit Operation for EP1
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Section 22 USB Function Module (USB)
22.8.3
DTC Transfer for Endpoint 2
When the transmit data at EP2 is transferred by the DTC, the USB function module automatically performs the same processing as writing 1 to the PKTE bit in TRG if the currently selected FIFO (64 bytes) becomes full. Accordingly, to transfer data of a multiple of 64 bytes, the user need not write 1 to the PKTE bit. To transfer data of less than 64 bytes, the user must write 1 to the PKTE bit on a DTC transfer end interrupt. If the user writes 1 to the PKTE bit when the maximum number of bytes (64 bytes) are transferred, correct operation cannot be guaranteed. To end the DTC transfer, write 0 to the EP2EMPTY bit in IFR0, after clearing the EP2DMAE bit in DMA to 0 within the processing routine for a DTC transfer end interrupt. If this procedure is omitted, the DTC transfer end interrupt is not cleared. To perform the DTC transfer again, in addition to the said procedure, set the number of transfers, set the DTCERF register, and then set the EP2DMAE bit in DMA to 1. Figure 22.21 shows an example for transmitting 150 bytes of data to the host. In this case, internal processing which is the same as writing 1 to the PKTE bit in TRG is automatically performed twice. This internal processing is performed when the currently selected data FIFO becomes full. Accordingly, this processing is automatically performed only when 64-byte data is sent. When the last 22 bytes are sent, the internal processing for writing 1 to the PKTE bit is not performed, and the user must write 1 to the PKTE bit by software. In this case, the application has no more data to transfer but the USB function module continues to output DTC requests for EP2 as long as the FIFO has an empty space. Therefore, when all data has been transferred, write 0 to the EP2DMAE bit in DMA to cancel DTC transfer requests, and then write 0 to the EP2EMPTY bit in IFR0 to clear the request for a DTC transfer end interrupt.
64 bytes
64 bytes
22 bytes
PKTE (Automatically performed)
PKTE is PKTE (Automatically not performed performed) Execute by DMA transfer end interrupt (user)
Figure 22.21 PKTE Bit Operation for EP2
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Section 22 USB Function Module (USB)
22.8.4
DTC Transfer End Interrupt
When the DTC transfer end interrupt is generated, handle the processing below. (1) Endpoint 1
* Clear the EP1DMAE bit in DMA to 0. * Write H'BF to the IFR0 register. Write 0 to the EP1FULL bit. The bit manipulation instruction should not be used for this setting. When the DTC transfer is continuously performed: * Set CRA and CRB of the DTC the number of transfers. * Set the DTCERF register. * Set 1 to the EP1DMAE bit in DMA. (2) Endpoint 2
* Clear the EP2DMAE bit in DMA to 0. * Write H'EF to the IFR0 register. Write 0 to the EP2EMPTY bit. The bit manipulation instruction should not be used for this setting. When the DTC transfer is continuously performed: * Set CRA and CRB of the DTC the number of transfers. * Set the DTCERF register. * Set 1 to the EP2DMAE bit in DMA.
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Section 22 USB Function Module (USB)
22.9
Example of USB External Circuitry
1. USB Transceiver This module supports the built-in transceiver only, not the external transceiver. 2. D+ Pull-Up Control The PUPDPLS pin is used for D+ pull-up control. PUPDPLS is driven high by the PULLUP_E bit of the DMA register when the USB cable VBUS is connected. Thus, USB host/hub connection notification (D+ pill-up) is enabled. 3. Detection of USB Cable Connection/Disconnection As USB states, etc., are managed by hardware in this module, a VBUS signal that recognizes connection/disconnection is necessary. The power supply signal (VBUS) in the USB cable is used for this purpose. However, if the cable is connected to the USB host/hub when the function (system installing this LSI) power is off, a voltage (5 V) will be applied from the USB host/hub. Therefore, an IC (such as an HD74LV1G08A or 2G08A) that allows voltage application when the system power is off should be connected externally.
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Section 22 USB Function Module (USB)
USB PULLUP_E
On-chip transceiver Vcc (3.3 V) DrVCC (3.3 V)
PM4
VBUS*2
USD+
USD-
DrVSS
Vss
Vcc
3.3 V
*1 Vcc
*1 External pull-up control circuit supporting full-speed
1.5 k
VBUS (5 V) D+
D-
GND
USB connector
Notes:
1. To protect this LSI from being damaged, use the IC (such as HD74LV-A Series) which can be applied voltage even when the system power is turned off. 2. Prevent noise from the VBUS pin while the USB is performing communication.
Figure 22.22 Example of Circuitry in Self-Powered Mode
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Section 22 USB Function Module (USB)
22.10
Usage Notes
22.10.1 Receiving Setup Data Note the following for EPDR0s that receives 8-byte setup data: 1. As a latest setup command must be received in high priority, the write from the USB bus takes priority over the read from the CPU. If the next setup command reception is started while the CPU is reading data after the data is received, the read from the CPU is forcibly terminated. Therefore, the data read after reception is started becomes invalid. 2. EPDR0s must always be read in 8-byte units. If the read is terminated at a midpoint, the data received at the next setup cannot be read correctly. 22.10.2 Clearing the FIFO If a USB cable is disconnected during data transfer, the data being received or transmitted may remain in the FIFO. When disconnecting a USB cable, clear the FIFO. While a FIFO is transferring data, it must not be cleared. 22.10.3 Overreading and Overwriting the Data Registers Note the following when reading or writing to a data register of this module. (1) Receive data registers
The receive data registers must not be read exceeding the valid amount of receive data, that is, the number of bytes indicated by the receive data size register. Even for EPDR1 which has double FIFO buffers, the maximum data to be read at one time is 64 bytes. After the data is read from the current valid FIFO buffer, be sure to write 1 to EP1RDFN in TRG, which switches the valid buffer, updates the receive data size to the new number of bytes, and enables the next data to be received. (2) Transmit data registers
The transmit data registers must not be written to exceeding the maximum packet size. Even for EPDR2 which has double FIFO buffers, write data within the maximum packet size at one time. After the data is written, write 1 to PKTE in TRG to switch the valid buffer and enable the next data to be written. Data must not be continuously written to the two FIFO buffers.
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Section 22 USB Function Module (USB)
22.10.4 Assigning Interrupt Sources to EP0 The EP0-related interrupt sources indicated by the interrupt source bits (bits 0 to 3) in IFR0 must be assigned to the same interrupt signal with ISR0. The other interrupt sources have no limitations. 22.10.5 Clearing the FIFO When DTC Transfer is Enabled The endpoint 1 data register (EPDR1) cannot be cleared when DTC transfer for endpoint 1 is enabled (EP1DMAE in DMA = 1). Cancel DTC transfer before clearing the register. 22.10.6 Notes on TR Interrupt Note the following when using the transfer request interrupt (TR interrupt) for IN transfer to EP0i, EP2, or EP3. The TR interrupt flag is set if the FIFO for the target EP has no data when the IN token is sent from the USB host. However, at the timing shown in figure 22.24, multiple TR interrupts occur successively. Take appropriate measures against malfunction in such a case. Note: This module determines whether to return NAK if the FIFO of the target EP has no data when receiving the IN token, but the TR interrupt flag is set after a NAK handshake is sent. If the next IN token is sent before PKTE of TRG is written to, the TR interrupt flag is set again.
TR interrupt routine CPU Clear Writes TRG. TR flag transmit data PKTE
TR interrupt routine
Host
IN token
IN token
IN token
USB
Determines whether to return NAK NAK Sets TR flag
Determines whether to return NAK NAK
Transmits data ACK
Sets TR flag (Sets the flag again)
Figure 22.23 TR Interrupt Flag Set Timing
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Section 22 USB Function Module (USB)
22.10.7 Restrictions on Peripheral Module Clock () Operating Frequency The USB clock select pin (UXSEL) can be used to select the clock source. To set the USB dedicated clock (cku) at 48 MHz, specify the peripheral module clock () as shown in table 22.8. Operation cannot be guaranteed if any frequency other than in the following table is specified. When UXSEL is set to 0, connect UEXTAL to the system power supply (0 V). The USB operates only in high-speed mode and does not operate in medium-speed mode. Table 22.8 Selection of Peripheral Module Clock () when USB Connection is Made
UXSEL 0 1 UEXTAL Input Frequency 8.00 MHz EXTAL Input Frequency 8.00 MHz 8.50 MHz USB Dedicated Clock (cku: 48 MHz) EXTAL x 6 UEXTAL x 6 EXTAL x 4 (32 MHz) EXTAL x 4 (34 MHz)
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Section 23 A/D Converter
Section 23 A/D Converter
This LSI includes a successive-approximation-type 10-bit A/D converter that allows up to eight analog input channels to be selected. A block diagram of the A/D converter is shown in figure 23.1.
23.1
* * * *
Features
10-bit resolution Eight input channels Conversion time: 4.7 s per channel (at 34-MHz operation) Two operating modes Single mode: Single-channel A/D conversion Scan mode: Continuous A/D conversion on 1 to 4 channels or continuous A/D conversion on 1 to 8 channels
* Eight data registers Conversion results are held in a 16-bit data register for each channel * * Sample and hold function Three ways of starting A/D conversion Software Trigger from TMR_0 External trigger signal * * Interrupt request A/D conversion end interrupt (ADI) request can be generated Module stop mode can be set
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Section 23 A/D Converter
Module data bus
Bus interface
Internal data bus
AVCC AVref* AVSS 10-bit D/A
Successive approximations register
A D D R A
A D D R B
A D D R C
A D D R D
A D D R E
A D D R F
A D D R G
A D D R H
A D C S R
A D C R
AN0 AN1
Multiplexer
+
AN2 AN3 AN4 AN5 AN6 AN7
Comparator Sample-and-hold circuit
Control circuit
ADI interrupt signal ADTRG [Legend] ADCR: A/D control register ADCSR: A/D control/status register ADDRA: A/D data register A ADDRB: A/D data register B ADDRC: A/D data register C Conversion start trigger from TMR_0
ADDRD: A/D data register D ADDRE: A/D data register E ADDRF: A/D data register F ADDRG: A/D data register G ADDRH: A/D data register H
Note: * Supported only by the H8S/2472 Group and the H8S/2462 Group.
Figure 23.1 Block Diagram of the A/D Converter
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Section 23 A/D Converter
23.2
Input/Output Pins
Table 23.1 summarizes the pins used by the A/D converter. Table 23.1 Pin Configuration
Pin Name Analog input pin 0 Analog input pin 1 Analog input pin 2 Analog input pin 3 Analog input pin 4 Analog input pin 5 Analog input pin 6 Analog input pin 7 A/D external trigger input pin Symbol AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 ADTRG I/O Input Input Input Input Input Input Input Input Input Input Input Input External trigger input for starting A/D conversion Analog block power supply Analog block ground Reference voltage for A/D converter Supported only by the H8S/2472 Group and the H8S/2462 Group. Function Analog input pins
Analog power supply AVcc pin Analog ground pin Reference power supply pin AVss AVref
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Section 23 A/D Converter
23.3
Register Descriptions
The A/D converter has the following registers. * A/D data register A (ADDRA) * A/D data register B (ADDRB) * A/D data register C (ADDRC) * A/D data register D (ADDRD) * A/D data register E (ADDRE) * A/D data register F (ADDRF) * A/D data register G (ADDRG) * A/D data register H (ADDRH) * A/D control/status register (ADCSR) * A/D control register (ADCR) 23.3.1 A/D Data Registers A to H (ADDRA to ADDRH)
The ADDR are eight 16-bit read-only registers, ADDRA to ADDRH, which store the results of A/D conversion. The ADDR registers, which store a conversion result for each channel, are shown in table 23.2. The converted 10-bit data is stored to bits 15 to 6. The lower 6-bit data is always read as 0. The data bus between the CPU and the A/D converter is 16-bit width and can be read directly from the CPU. The ADDR must always be accessed in 16-bit unit. They cannot be accessed in 8bit unit. The results of A/D conversion are stored in each registers, when the ADF flag is set to 1.
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Section 23 A/D Converter
Table 23.2 Analog Input Channels and Corresponding ADDR Registers
A/D Data Register to Store A/D Conversion Results ADDRA ADDRB ADDRC ADDRD ADDRE ADDRF ADDRG ADDRH
Analog Input Channel AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7
23.3.2
A/D Control/Status Register (ADCSR)
The ADCSR controls the operation of the A/D conversion.
Bit 7 Bit Name ADF Initial Value 0 R/W Description
R/(W)* A/D End Flag A status flag that indicates the end of A/D conversion. This flag indicates that the results of A/D conversion are stored in the A/D data registers. [Setting conditions] * * When A/D conversion ends in single mode When A/D conversion ends on all channels specified in scan mode When 0 is written after reading ADF = 1 When DTC starts by an ADI interrupt and ADDR is read
[Clearing conditions] * * 6 ADIE 0 R/W
A/D Interrupt Enable Enables ADI interrupt by ADF when this bit is set to 1
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Section 23 A/D Converter
Bit 5
Bit Name ADST
Initial Value R/W 0 R/W
Description A/D Start Clearing this bit to 0 stops A/D conversion and enters the idle state. Setting this bit to 1 starts A/D conversion. In single mode, this bit is cleared to 0 automatically when conversion on the specified channel ends. In scan mode, conversion continues sequentially on the specified channels until this bit is cleared to 0 by software, a reset, or a transition to the hardware standby mode.
4 3

0 0
R R/W
Reserved This is a read-only bit and cannot be modified. Reserved This bit is always read as 0. The initial value should not be changed.
2 1 0
CH2 CH1 CH0
All 0
R/W
Channel Select 2 to 0 Select analog input channels together with the SCANE bit and the SCANS bit of ADCR. When SCANE = 0, When SCANE = 1 and SCANS = x and SCANS = 0 000: AN0 001: AN1 010: AN2 011: AN3 100: AN4 101: AN5 110: AN6 111: AN7 000: AN0 010: AN0 to AN2 011: AN0 to AN3 100: AN4 110: AN4 to AN6 111: AN4 to AN7 When SCANE = 1 and SCANS = 1 000: AN0 010: AN0 to AN2 011: AN0 to AN3 100: AN0 to AN4 110: AN0 to AN6 111: AN0 to AN7
001: AN0 and AN1 001: AN1 and AN1
101: AN4 and AN5 101: AN0 to AN5
Note: * Only 0 can be written to clear the flag. [Legend] x: Don't care
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Section 23 A/D Converter
23.3.3
A/D Control Register (ADCR)
The ADCR sets the operation mode of A/D converter and the conversion time.
Bit 7 6 0 Bit Name TRGS1 TRGS0 EXTRGS Initial Value 0 0 0 R/W R/W R/W R/W Description Timer Trigger Select 1 and 0, Extended Trigger Select Enable starting of A/D conversion by a trigger signal. 00 0: Disables starting by trigger signals. 10 0: Enables starting by a trigger from TMR_0. 10 1: Enables starting by the ADTRG pin input. Other than above: Setting prohibited 5 4 SCANE SCANS 0 0 R/W R/W Scan Mode Select the operation mode of A/D conversion 0x: Single mode 10: Scan mode (consecutive A/D conversion of channels 1 to 4) 11: Scan mode (consecutive A/D conversion of channels 1 to 8) 3 2 CKS1 CKS0 0 0 R/W R/W Clock Select 1 and 0 Set the A/D conversion time. Setting should be made while the conversion is stopped (ADST = 0). 00: Setting prohibited 01: Conversion time = 80 states (max) (20 MHz or less) 10: Conversion time = 160 states (max) 11: Conversion time = 320 states (max) 1 ADSTCLR 0 R/W A/D Start Clear Sets automatic clearing of the ADST bit in scan mode. 0: Disables automatic clearing of ADST in scan mode. 1: ADST is automatically cleared when A/D conversion for all the selected channels has been completed in scan mode. [Legend] x: Don't care
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Section 23 A/D Converter
23.4
Operation
The A/D converter operates by successive approximation with 10-bit resolution. It has two operating modes: single mode and scan mode. When changing the operating mode or analog input channel, to prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. The ADST bit can be set to 1 at the same time as the operating mode or analog input channel is changed. 23.4.1 Single Mode
In single mode, A/D conversion is performed only once on the specified single channel. Operations are as follows. 1. A/D conversion on the specified channel is started when the ADST bit in ADCSR is set to 1, by software or by the input of trigger signal. 2. When A/D conversion is completed, the result is transferred to the A/D data register corresponding to the channel. 3. On completion of A/D conversion, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt request is generated. 4. The ADST bit remains set to 1 during A/D conversion. When conversion ends, the ADST bit is automatically cleared to 0, and the A/D converter enters the idle state. If the ADST bit is cleared during A/D conversion, the A/D converter stops conversion and enters the idle state.
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Section 23 A/D Converter
Set* ADIE A/D conversion starts Set* Set*
ADST
Clear* ADF State of channel 0 (AN0) State of channel 1 (AN1) State of channel 2 (AN2) State of channel 3 (AN3) ADDRA Read the result of conversion ADDRB ADDRC ADDRD Note : * indicates execution of a software instruction. Result of A/D conversion 1
Clear*
Idle Idle Idle Idle A/D conversion 1 Idle A/D conversion 2 Idle
Read the result of conversion Result of A/D conversion 2
Figure 23.2 Example of A/D Converter Operation (When Channel 1 is Selected in Single Mode) 23.4.2 Scan Mode
In scan mode, A/D conversion is performed sequentially on the specified channels (four channels or eight channel maximum). Operations are as follows. 1. When the ADST bit in ADCSR is set to 1 by software or by the input of trigger signal, A/D conversion starts from the first channel of the selected channel. Consecutive A/D conversion of either four channels maximum (SCANE and SCANS = B'10) or eight channels maximum (SCANE and SCANS = B'11) can be selected. In the case of consecutive A/D conversion on four channels, the operation starts from AN0 when CH2 = B'0, and starts from AN4 when CH2 = B'1. In the case of consecutive A/D conversion on eight channels, the operation starts from AN0. 2. When A/D conversion for each channel is completed, the result is sequentially transferred to the A/D data register corresponding to each channel. 3. When conversion of all the selected channels is completed, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt is requested after A/D conversion ends. Conversion of the first channel in the group starts again.
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Section 23 A/D Converter
4. The ADST bit is not automatically cleared to 0 and steps 2 to 3 are repeated as long as the ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops and the A/D converter enters the idle state. After that, when the ADST bit is set to 1, the operation starts from the first channel again.
Continuous execution of A/D conversion
Set*1 Clear*1
ADST
Clear*1
ADF
A/D conversion time
State of channel 0 (AN0) State of channel 1 (AN1) State of channel 2 (AN2) State of channel 3 (AN3)
Idle
A/D conversion 1
Idle
A/D conversion 4
Idle
Idle
A/D conversion 2
Idle
A/D conversion 5 *2
Idle
Idle
A/D conversion 3
Idle
Idle Transfer
ADDRA
Result of A/D conversion 1
Result of A/D conversion 4
ADDRB
Result of A/D conversion 2
ADDRC
Result of A/D conversion 3
ADDRD
Notes : 1. indicates execution of a software instruction. 2. The data being converted is ignored
Figure 23.3 Example of A/D Converter Operation (When Channels AN0 to AN3 are Selected in Scan Mode)
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Section 23 A/D Converter
23.4.3
Input Sampling and A/D Conversion Time
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input when the A/D conversion start delay time (tD) has passed after the ADST bit in ADCSR is set to 1, then starts A/D conversion. Figure 23.4 shows the A/D conversion timing. Tables 23.3 and 23.4 show the A/D conversion time. As indicated in figure 23.4, the A/D conversion time (tCONV) includes tD and the input sampling time (tSPL). The length of tD varies depending on the timing of the write access to ADCSR. The total conversion time therefore varies within the ranges indicated in table 23.3. In scan mode, the values given in table 23.3 apply to the first conversion time. The values given in table 23.4 apply to the second and subsequent conversions. In either case, bits CKS1 and CKS0 in ADCR should be set so that the conversion time is within the ranges indicated by the A/D conversion characteristics.
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Section 23 A/D Converter
(1)
Address
(2)
Write signal
Input sampling timing
ADF tD tSPL tCONV [Legend] (1): ADCSR write cycle (2): ADCSR address tD: A/D conversion start delay tSPL: Input sampling time tCONV: A/D conversion time
Figure 23.4 A/D Conversion Timing
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Section 23 A/D Converter
Table 23.3 A/D Conversion Characteristics (Single Mode)
CKS1 = 0 CKS0 = 1 Item A/D conversion start delay time Symbol Min. tD (6) 77 Typ. 30 Max. (9) 80 Min. (10) 153 CKS0 = 0 Typ. 60 Max. (17) 160 Min. (18) 305 CKS1 = 1 CKS0 = 1 Typ. 120 Max. (33) 320
Input sampling time tSPL A/D conversion time tCONV
Note:
Values in the table are the number of states.
Table 23.4 A/D Conversion Characteristics (Scan Mode)
CKS1 0 CKS0 0 1 1 0 1 Conversion Time (Number of States) Setting prohibited 80 (Fixed) 160 (Fixed) 320 (Fixed)
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Section 23 A/D Converter
23.4.4
Timing of External Trigger Input
A/D conversion can also be started by an externally input trigger signal. Setting the TRGS1 and TRGS0 bits in ADCR to B'11 selects the signal on the ADTRG pin as an external trigger. The ADST bit in ADCSR is set to 1 on the falling edge of ADTRG, initiating A/D conversion. Other operations are the same as those in the case where the ADST bit is set to 1 by software, regardless of whether the converter is in single mode or scan mode. The timing of this operation is shown in figure 23.5.
ADTRG
Internal trigger signal
ADST A/D conversion time
Figure 23.5 Timing of External Trigger Input
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Section 23 A/D Converter
23.5
Interrupt Source
The A/D converter generates an A/D conversion end interrupt (ADI) at the end of A/D conversion. Setting the ADIE bit to 1 enables ADI interrupt requests while the ADF bit in ADCSR is set to 1 after A/D conversion ends. The ADI interrupt can be used to activate the DTC. Reading the converted data by the DTC activated by the ADI interrupt allows consecutive conversion to be performed without software overhead. Table 23.5 A/D Converter Interrupt Source
Name ADI Interrupt Source A/D conversion end Interrupt Flag ADF DTC Activation Possible
23.6
A/D Conversion Accuracy Definitions
This LSI's A/D conversion accuracy definitions are given below. * Resolution The number of A/D converter digital output codes * * Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure23.6). Offset error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from the minimum voltage value B'00 0000 0000 (H'000) to B'00 0000 0001 (H'001) (see figure 23.7). * Full-scale error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from B'11 1111 1110 (H'3FE) to B'11 1111 1111 (H'3FF) (see figure 23.7). * Nonlinearity error The error with respect to the ideal A/D conversion characteristics between the zero voltage and the full-scale voltage. Does not include the offset error, full-scale error, or quantization error (see figure 23.7). * Absolute accuracy The deviation between the digital value and the analog input value. Includes the offset error, full-scale error, quantization error, and nonlinearity error.
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Section 23 A/D Converter
Digital output
H'3FF H'3FE H'3FD H'004 H'003 H'002 H'001 H'000
Ideal A/D conversion characteristic
Quantization error
1 2 1024 1024
1022 1023 FS 1024 1024 Analog input voltage
Figure 23.6 A/D Conversion Accuracy Definitions
Full-scale error
Digital output
Ideal A/D conversion characteristic
Nonlinearity error Actual A/D conversion characteristic
FS
Offset error
Analog input voltage
Figure 23.7 A/D Conversion Accuracy Definitions
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Section 23 A/D Converter
23.7
23.7.1
Usage Notes
Setting of Module Stop Mode
Operation of the A/D converter can be enabled or disabled by setting the module stop control register. By default, the A/D converter is stopped. Registers of the A/D converter only become accessible when it is released from module stop mode. See section 28, Power-Down Modes, for details. 23.7.2 Permissible Signal Source Impedance
This LSI's analog input is designed so that the conversion accuracy is guaranteed for an input signal for which the signal source impedance is 5 k or less. This specification is provided to enable the A/D converter's sample-and-hold circuit input capacitance to be charged within the sampling time; if the sensor output impedance exceeds 5 k, charging may be insufficient and it may not be possible to guarantee the A/D conversion accuracy. However, if a large capacitance is provided externally in single mode, the input load will essentially comprise only the internal input resistance of 10 k, and the signal source impedance is ignored. However, since a low-pass filter effect is obtained in this case, it may not be possible to follow an analog signal with a large differential coefficient (voltage fluctuation ratio of 5 mV/s or greater for example) (see figure 23.8). When converting a high-speed analog signal or converting in scan mode, a low-impedance buffer should be inserted.
This LSI Sensor output impedance up to 5 k Sensor input Low-pass filter C up to 0.1 F
Cin = 15 pF
A/D converter equivalent circuit
10 k
20 pF
Figure 23.8 Example of Analog Input Circuit
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Section 23 A/D Converter
23.7.3
Influences on Absolute Accuracy
Adding capacitance results in coupling with GND, and therefore noise in GND may adversely affect the absolute accuracy. Be sure to make the connection to an electrically stable GND such as AVss. Care is also required to insure that filter circuits do not communicate with digital signals on the mounting board, so acting as antennas. 23.7.4 Setting Range of Analog Power Supply and Other Pins
If conditions shown below are not met, the reliability of this LSI may be adversely affected. * Analog input voltage range The voltage applied to analog input pin ANn during A/D conversion should be in the range AVss VAN AVref. * Relation between AVcc, AVss and Vcc, Vss The relationship between AVcc, AVss and Vcc, Vss should be Avcc = Vcc 0.3V and AVss = Vss. When the A/D converter is not used, set AVcc = Vcc and Avss = Vss. * AVref pin reference voltage specification range The reference voltage of the AVref pin should be in the range AVref AVcc. 23.7.5 Notes on Board Design
In board design, digital circuitry and analog circuitry should be as mutually isolated as possible, and layout in which digital circuit signal lines and analog circuit signal lines cross or are in close proximity should be avoided as far as possible. Failure to do so may result in incorrect operation of the analog circuitry due to inductance, adversely affecting A/D conversion values. Also, digital circuitry must be isolated from the analog input signals (AN0 to AN7), the analog reference voltage (AVref) and analog power supply (AVcc) by the analog ground (AVss). Also, the analog ground (AVss) should be connected at one point to a stable digital ground (Vss) on the board.
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Section 23 A/D Converter
23.7.6
Notes on Noise Countermeasures
In order to prevent damage due to an abnormal voltage such as an excessive surge at the analog input pins (AN0 to AN7), a protection circuit should be connected between AVcc and AVss as shown in figure 23.9. Also, the bypass capacitors connected to AVcc and the filter capacitors connected to AN0 to AN7 must be connected to AVss. When a filter capacitor is connected, the input currents at the analog input pins (AN0 to AN7) are averaged which may cause an error. Also, when A/D conversion is performed frequently, as in scan mode, if the current charged and discharged by the capacitance of the sample-and-hold circuit in the A/D converter exceeds the current input via the input impedance (Rin), an error will arise in the analog input pin voltage. Therefore, careful consideration is required upon deciding the circuit constants.
AVcc AVref
*1 *1
Rin *2
100 AN0 to AN7 0.1 F AVss
Notes: Values are reference values.
*1
10 F
0.01 F
*2
Rin: Input impedance
Figure 23.9 Example of Analog Input Protection Circuit Table 23.6 Standard of Analog Pins
Item Analog input capacitance Acceptable signal source impedance Min. Max. 20 5 Unit pF k
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Section 23 A/D Converter
10 k AN0 to AN7 20 pF
To A/D converter
Note: Values are reference values.
Figure 23.10 Analog Input Pin Equivalent Circuit 23.7.7 Note on the Usage in Software Standby Mode
If this LSI enters software standby mode with the A/D conversion enabled, the content of the A/D converter is retained and about the same amount of analog supply current may flow as that flows when A/D conversion in progress. If the analog supply current must be reduced in software standby mode, clear the ADST bit to disable the A/D conversion.
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Section 24 RAM
Section 24 RAM
This LSI has 40 Kbytes of on-chip high-speed static RAM. The RAM is connected to the CPU by a 16-bit data bus, enabling one-state access by the CPU to both byte data and word data. The on-chip RAM can be enabled or disabled by means of the RAME bit in the system control register (SYSCR). For details on SYSCR, see section 3.2.2, System Control Register (SYSCR).
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Section 24 RAM
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Section 25 Flash Memory
Section 25 Flash Memory
The flash memory has the following features. Figure 25.1 shows a block diagram of the flash memory.
25.1
* Size
Features
512 Kbytes (ROM address: H'000000 to H'07FFFF) * Programming/erasing interface by the download of on-chip program This LSI has a dedicated programming/erasing program. After downloading this program to the on-chip RAM, programming/erasing can be performed by setting the argument parameter. * Programming/erasing time The flash memory programming time is 1 ms (typ) in 128-byte simultaneous programming and approximately 7.8 s per byte. The erasing time is 600 ms (typ) per 64-Kbyte block. * Number of programming The number of flash memory programming can be up to 100 times at the minimum. (The value ranged from 1 to 100 is guaranteed.) * Four on-board programming modes SCI boot mode This mode uses an on-chip SCI_1 interface to program and erase the user MAT. This mode can automatically adjust the bit rate between the host and this LSI. USB boot mode (only in the H8S/2472 Group) This mode uses an on-chip USB to program and erase the user MAT. User program mode The user MAT can be programmed by using the optional interface. User boot mode The user boot program of the optional interface can be made and the user MAT can be programmed. * Programming/erasing protection Sets protection against flash memory programming/erasing via hardware, software, or error protection. * Programmer mode This mode uses the PROM programmer. The user MAT and user boot MAT can be programmed.
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Section 25 Flash Memory
Internal address bus Internal data bus (16 bits)
FCCS
Module bus
FPCS FECS FKEY FMATS FTDAR
Control unit Memory MAT unit User MAT: 512 Kbytes User boot MAT: 16 Kbytes
Flash memory
FWE pin Mode pin [Legend] FCCS: FPCS: FECS: FKEY: FMATS: FTDAR:
Operating mode
Flash code control status register Flash program code select register Flash erase code select register Flash key code register Flash MAT select register Flash transfer destination address register
Note: To read from or write to the registers, the FLSHE bit in the serial timer control register (STCR) must be set to 1.
Figure 25.1 Block Diagram of Flash Memory
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Section 25 Flash Memory
25.1.1
Operating Mode
When each mode pin and the FWE pin are set in the reset state and reset start is performed, this LSI enters each operating mode as shown in figure 25.2. * Flash memory can be read in user mode, but cannot be programmed or erased. * Flash memory can be read, programmed, or erased on the board only in boot mode, user program mode, and user boot mode. * Flash memory can be read, programmed, or erased by means of the PROM programmer in programmer mode.
RES = 0
Reset state
Programmer mode setting
Programmer mode
RES =0
R
ES
=0
d mo es
in ett
g
Bo ot
RE
mo de
S=
ing
0
ot g bo tin er set Us de mo
RE S
er Us
se tt
=0
FLSHE = 0 FWE = 0
User mode
FWE = 1 FLSHE = 1
User program mode
User boot mode On-board programming mode
Boot mode SCI_1/USB
Figure 25.2 Mode Transition of Flash Memory
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Section 25 Flash Memory
25.1.2
Mode Comparison
The comparison table of programming and erasing related items about boot mode, user program mode, user boot mode, and programmer mode is shown in table 25.1. Table 25.1 Comparison of Programming Modes
Boot Mode Programming/ erasing environment Programming/ erasing enable MAT All erasure Block division erasure Program data transfer Reset initiation MAT Transition to user mode On-board User Program Mode On-board User Boot Mode On-board Programmer Mode PROM programmer User MAT User boot MAT (Automatic)
User MAT User boot MAT (Automatic) *
1
User MAT
User MAT
x
From host via SCI Via optional device Via optional device Via programmer or USB Embedded program storage MAT Changing mode setting and reset User MAT User boot MAT*
2
Changing FLSHE bit and FWE pin
Changing mode setting and reset
Notes: 1. All-erasure is performed. After that, the specified block can be erased. 2. Firstly, the reset vector is fetched from the embedded program storage MAT. After the flash memory related registers are checked, the reset vector is fetched from the user boot MAT.
* The user boot MAT can be programmed or erased only in boot mode and programmer mode. * The user MAT and user boot MAT are erased in boot mode. Then, the user MAT and user boot MAT can be programmed by means of the command method. However, the contents of the MAT cannot be read until this state. Only user boot MAT is programmed and the user MAT is programmed in user boot mode or only user MAT is programmed because user boot mode is not used. * The boot operation of the optional interface can be performed by the mode pin setting different from user program mode in user boot mode.
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Section 25 Flash Memory
25.1.3
Flash Memory MAT Configuration
This LSI's flash memory is configured by the 16-Kbyte user boot MAT and 512-Kbyte user MAT. The start address is allocated to the same address in the user MAT and user boot MAT. Therefore, when the program execution or data access is performed between two MATs, the MAT must be switched by using FMATS. The user MAT or user boot MAT can be read in all modes. However, the user boot MAT can be programmed only in boot mode and programmer mode.
Address H'000000 Address H'003FFF
Address H'000000
16 Kbytes
512 Kbytes
Address H'07FFFF
Figure 25.3 Flash Memory Configuration The size of the user MAT is different from that of the user boot MAT. An address which exceeds the size of the 16-Kbyte user boot MAT should not be accessed. If the attempt is made, data is read as undefined value. 25.1.4 Block Division
The user MAT is divided into seven 64-Kbyte blocks, one 32-Kbyte block, and eight 4-Kbyte blocks as shown in figure 25.4. The user MAT can be erased in this divided-block units, and the erase-block number of EB0 to EB15 is specified when erasing. Programming is performed in 128byte units starting at the addresses whose lowest-order byte is H'00 or H'80.
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Section 25 Flash Memory
EB0 Erase unit: 4 kbytes
H'000000 H'000F80
H'000001 H'000F81 H'001001
H'000002 H'000F82 H'001002
Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes --------------
H'00007F H'000FFF H'00107F H'001FFF H'00207F
EB1 Erase unit: 4 kbytes
H'001000
H'001F80 EB2 Erase unit: 4 kbytes H'002000
H'001F81 H'002001
H'001F82 H'002002
H'002F80 EB3 Erase unit: 4 kbytes H'003F80 EB4 Erase unit: 4 kbytes H'004F80 EB5 Erase unit: 4 kbytes H'005F80 EB6 Erase unit: 4 kbytes H'006F80 EB7 Erase unit: 4 kbytes H'007F80 EB8 Erase unit: 32 kbytes H'00FF80 EB9 Erase unit: 64 kbytes H'01FF80 EB10 Erase unit: 64 kbytes H'02FF80 EB11 Erase unit: 64 kbytes H'03FF80 EB12 Erase unit: 64 kbytes H'04FF80 EB13 Erase unit: 64 kbytes H'05FF80 EB14 Erase unit: 64 kbytes H'06FF80 EB15 Erase unit: 64 kbytes H'07FF80 H'070000 H'060000 H'050000 H'040000 H'030000 H'020000 H'010000 H'008000 H'007000 H'006000 H'005000 H'004000 H'003000
H'002F81 H'003001
H'002F82 H'003002
H'002FFF H'00307F H'003FFF H'00407F H'004FFF H'00507F H'005FFF H'00607F H'006FFF H'00707F
H'003F81 H'004001 H'004F81 H'005001 H'005F81 H'006001 H'006F81 H'007001 H'007F81 H'008001
H'003F82 H'004002 H'004F82 H'005002 H'005F82 H'006002 H'006F82 H'007002 H'007F82 H'008002
H'007FFF H'00807F H'00FFFF H'01007F
H'00FF81 H'010001 H'01FF81 H'020001
H'00FF82 H'010002 H'01FF82 H'020002
H'01FFFF H'02007F H'02FFFF H'03007F
H'02FF81 H'030001 H'03FF81 H'04F001
H'02FF82 H'030002 H'03FF82 H'04F002
H'03FFFF H'04F07F H'04FFFF H'05007F
H'04FF81 H'050001 H'05FF81 H'060001
H'04FF82 H'050002 H'05FF82 H'060002
H'05FFFF H'06007F H'06FFFF H'07007F
H'06FF81 H'070001 H'07FF81
H'06FF82 H'070002 H'07FF82
H'07FFFF
Figure 25.4 Block Division of User MAT
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Section 25 Flash Memory
25.1.5
Programming/Erasing Interface
Programming/erasing is executed by downloading the on-chip program to the on-chip RAM and specifying the program address/data and erase block by using the interface register/parameter. The procedure program is made by the user in user program mode and user boot mode. An overview of the procedure is given as follows. For details, see section 25.4.3, User Program Mode.
Start user procedure program for programming/erasing. Select on-chip program to be downloaded and specify the destination. Download on-chip program by setting FKEY and SCO bits.
Initialization execution (downloaded program execution)
Programming (in 128-byte units) or erasing (in one-block units) (downloaded program execution)
No
Programming/erasing completed? Yes
End user procedure program
Figure 25.5 Overview of User Procedure Program 1. Selection of on-chip program to be downloaded For programming/erasing execution, the FLSHE bit in STCR must be set to 1 to transition to user program mode. This LSI has programming/erasing programs which can be downloaded to the on-chip RAM. The on-chip program to be downloaded is selected by setting the corresponding bits in the programming/erasing interface register. The address of the programming destination is specified by the flash transfer destination address register (FTDAR).
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Section 25 Flash Memory
2. Download of on-chip program The on-chip program is automatically downloaded by setting the flash key code register (FKEY) and the SCO bit in the flash code control status register (FCCS), which are programming/erasing interface registers. The flash memory is replaced to the embedded program storage area when downloading. Since the flash memory cannot be read when programming/erasing, the procedure program, which is working from download to completion of programming/erasing, must be executed in the space other than the flash memory to be programmed/erased (for example, on-chip RAM). Since the result of download is returned to the programming/erasing interface parameter, whether the normal download is executed or not can be confirmed. 3. Initialization of programming/erasing The operating frequency is set before execution of programming/erasing. This setting is performed by using the programming/erasing interface parameter. 4. Programming/erasing execution For programming/erasing execution, the FLSHE bit in STCR and the FWE pin must be set to 1 to transition to user program mode. The program data/programming destination address is specified in 128-byte units when programming. The block to be erased is specified in erase-block units when erasing. These specifications are set by using the programming/erasing interface parameter and the onchip program is initiated. The on-chip program is executed by using the JSR or BSR instruction and performing the subroutine call of the specified address in the on-chip RAM. The execution result is returned to the programming/erasing interface parameter. The area to be programmed must be erased in advance when programming flash memory. All interrupts are prohibited during programming and erasing. Interrupts must be masked within the user system. 5. When programming/erasing is executed consecutively When the processing is not ended by the 128-byte programming or one-block erasure, the program address/data and erase-block number must be updated and consecutive programming/erasing is required. Since the downloaded on-chip program is left in the on-chip RAM after the processing, download and initialization are not required when the same processing is executed consecutively.
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Section 25 Flash Memory
25.2
Input/Output Pins
Table 25.2 shows the flash memory pin configuration. Table 25.2 Pin Configuration
Pin Name RES FWE MD2 MD1 TxD1 RxD1 USD+, USD- VBUS PUPDPLS PF5 Input/Output Input Input Input Input Output Input Input/output Input Input Input Function Reset Flash memory programming/erasing enable pin Sets operating mode of this LSI Sets operating mode of this LSI Serial transmit data output (used in SCI boot mode) Serial receive data input (used in SCI boot mode) USB data input/output (used in USB boot mode) Detects USB cable connection/disconnection (used in USB boot mode) USD+ pull-up control Sets SCI boot mode or USB boot mode (used in boot mode setting)
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Section 25 Flash Memory
25.3
Register Descriptions
The registers/parameters which control flash memory are shown in the following. To read from or write to these registers/parameters, the FLSHE bit in the serial timer control register (STCR) must be set to 1. For details on STCR, see section 3.2.3, Serial Timer Control Register (STCR). * Flash code control status register (FCCS) * Flash program code select register (FPCS) * Flash erase code select register (FECS) * Flash key code register (FKEY) * Flash MAT select register (FMATS) * Flash transfer destination address register (FTDAR) * Download pass/fail result (DPFR) * Flash pass/fail result (FPFR) * Flash multipurpose address area (FMPAR) * Flash multipurpose data destination area (FMPDR) * Flash erase Block select (FEBS) * Flash programming/erasing frequency control (FPEFEQ) There are several operating modes for accessing flash memory, for example, read mode/program mode. There are two memory MATs: user MAT and user boot MAT. The dedicated registers/parameters are allocated for each operating mode and MAT selection. The correspondence of operating modes and registers/parameters for use is shown in table 25.3.
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Section 25 Flash Memory
Table 25.3 Register/Parameter and Target Mode
Download FCCS Programming/ Erasing Interface FPCS Register FECS FKEY FMATS FTDAR Programming/ DPFR Erasing Interface FPFR Parameter FPEFEQ FMPAR FMPDR FEBS Initialization *
1
Programming
Erasure
1
Read
2
*
*
Notes: 1. The setting is required when programming or erasing user MAT in user boot mode. 2. The setting may be required according to the combination of initiation mode and read target MAT.
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Section 25 Flash Memory
25.3.1
Programming/Erasing Interface Register
The programming/erasing interface registers are as described below. They are all 8-bit registers that can be accessed in byte. These registers are initialized at a reset or in hardware standby mode. * Flash Code Control Status Register (FCCS) FCCS is configured by bits which request the monitor of the FWE pin state and error occurrence during programming or erasing flash memory and the download of on-chip program.
Bit 7 Initial Bit Name Value FWE 1/0 R/W R Description Flash Program Enable Monitors the signal level input to the FWE pin and enables or disables programming/erasing flash memory. 0: Programming/erasing disabled 1: Programming/erasing enabled 6, 5 All 0 R/W Reserved The initial value should not be changed.
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Section 25 Flash Memory
Bit 4
Initial Bit Name Value FLER 0
R/W R
Description Flash Memory Error Indicates an error occurs during programming and erasing flash memory. When FLER is set to 1, flash memory enters the error protection state. When FLER is set to 1, high voltage is applied to the internal flash memory. To reduce the damage to flash memory, the reset must be released after the reset period of 100 s which is longer than normal. 0: Flash memory operates normally. Programming/erasing protection for flash memory (error protection) is invalid. [Clearing condition] * At a reset or in hardware standby mode 1: An error occurs during programming/erasing flash memory. Programming/erasing protection for flash memory (error protection) is valid. [Setting conditions] * * When an interrupt, such as NMI, occurs during programming/erasing flash memory. When the flash memory is read during programming/erasing flash memory (including a vector read or an instruction fetch). When the SLEEP instruction is executed during programming/erasing flash memory (including software-standby mode) When a bus master other than the CPU, such as the DTC, gets bus mastership during programming/erasing flash memory.
*
*
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Section 25 Flash Memory
Bit 3
Initial Bit Name Value WEINTE 0
R/W R/W
Description Program/Erase Enable Modifies the space for the interrupt vector table, when interrupt vector data is not read successfully during programming/erasing flash memory or switching between a user MAT and a user boot MAT. When this bit is set to 1, interrupt vector data is read from address spaces H'FFE080 to H'FFE0FF (on-chip RAM space), instead of from address spaces H'000000 to H'00007F (up to vector number 31). Therefore, make sure to set the vector table in the on-chip RAM space before setting this bit to 1. The interrupt exception handling on and after vector number 32 should not be used because the correct vector is not read, resulting in the CPU runaway. 0: The space for the interrupt vector table is not modified. When interrupt vector data is not read successfully, the operation for the interrupt exception handling cannot be guaranteed. An occurrence of any interrupts should be masked. 1: The space for the interrupt vector table is modified. Even when interrupt vector data is not read successfully, the interrupt exception handling up to vector number 31 is enabled.
2, 1
All 0
R/W
Reserved The initial value should not be changed.
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Section 25 Flash Memory
Bit 0
Initial Bit Name Value SCO 0
R/W (R)/W*
Description Source Program Copy Operation Requests the on-chip programming/erasing program to be downloaded to the on-chip RAM. When this bit is set to 1, the on-chip program which is selected by FPCS/FECS is automatically downloaded in the on-chip RAM specified by FTDAR. In order to set this bit to 1, HA5 must be written to FKEY and this operation must be executed in the on-chip RAM. Four NOP instructions must be executed immediately after setting this bit to 1. Since this bit is cleared to 0 when download is completed, this bit cannot be read as 1. All interrupts must be disabled. This should be made in the user system. 0: Download of the on-chip programming/erasing program to the on-chip RAM is not executed. [Clearing condition] When download is completed 1: Request that the on-chip programming/erasing program is downloaded to the on-chip RAM is occurred. [Setting conditions] When all of the following conditions are satisfied and 1 is set to this bit * H'A5 is written to FKEY * During execution in the on-chip RAM
Note:
*
This bit is a write only bit. This bit is always read as 0.
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Section 25 Flash Memory
* Flash Program Code Select Register (FPCS) FPCS selects the on-chip programming program to be downloaded.
Bit 7 to 1 0 Initial Bit Name Value PPVS All 0 0 R/W R/W R/W Description Reserved The initial value should not be changed. Program Pulse Verify Selects the programming program. 0: On-chip programming program is not selected. [Clearing condition] When transfer is completed 1: On-chip programming program is selected.
* Flash Erase Code Select Register (FECS) FECS selects download of the on-chip erasing program.
Bit 7 to 1 0 Initial Bit Name Value EPVB All 0 0 R/W R/W R/W Description Reserved The initial value should not be changed. Erase Pulse Verify Block Selects the erasing program. 0: On-chip erasing program is not selected. [Clearing condition] When transfer is completed 1: On-chip erasing program is selected.
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Section 25 Flash Memory
* Flash Key Code Register (FKEY) FKEY is a register for software protection that enables download of on-chip program and programming/erasing of flash memory. Before setting the SCO bit to 1 in order to download onchip program or executing the downloaded programming/erasing program, these processing cannot be executed if the key code is not written.
Bit 7 6 5 4 3 2 1 0 Initial Bit Name Value K7 K6 K5 K4 K3 K2 K1 K0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Key Code Only when H'A5 is written, writing to the SCO bit is valid. When the value other than H'A5 is written to FKEY, 1 cannot be set to the SCO bit. Therefore downloading to the on-chip RAM cannot be executed. Only when H'5A is written, programming/erasing can be executed. Even if the on-chip programming/erasing program is executed, the flash memory cannot be programmed or erased when the value other than H'5A is written to FKEY. H'A5: Writing to the SCO bit is enabled. (The SCO bit cannot be set by the value other than H'A5.) H'5A: Programming/erasing is enabled. (The value other than H'A5 is in software protection state.) H'00: Initial value
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Section 25 Flash Memory
* Flash MAT Select Register (FMATS) FMATS specifies whether user MAT or user boot MAT is selected.
Bit 7 6 5 4 3 2 1 0 Initial Bit Name Value MS7 MS6 MS5 MS4 MS3 MS2 MS1 MS0 0/1* 0 0/1* 0 0/1* 0 0/1* 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description MAT Select These bits are in user-MAT selection state when the value other than H'AA is written and in user-boot-MAT selection state when H'AA is written. The MAT is switched by writing the value in FMATS. When the MAT is switched, follow section 25.6, Switching between User MAT and User Boot MAT. (The user boot MAT cannot be programmed in user program mode if user boot MAT is selected by FMATS. The user boot MAT must be programmed in boot mode or in programmer mode.) H'AA: The user boot MAT is selected (in user-MAT selection state when the value of these bits are other than H'AA) Initial value when these bits are initiated in user boot mode. H'00: Initial value when these bits are initiated in a mode except for user boot mode (in user-MAT selection state) [Programmable condition] These bits are in the execution state in the on-chip RAM. Note: * Set to 1 when in user boot mode, otherwise set to 0.
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Section 25 Flash Memory
* Flash Transfer Destination Address Register (FTDAR) FTDAR is a register that specifies the address to download an on-chip program. This register must be specified before setting the SCO bit in FCCS to 1.
Bit 7 Initial Bit Name Value TDER 0 R/W R/W Description Transfer Destination Address Setting Error This bit is set to 1 when the address specified by bits TDA6 to TDA0, which is the start address to download an on-chip program, is over the range. Whether or not the range specified by bits TDA6 to TDA0 is within the range of H'00 to H'03 is determined when an on-chip program is downloaded by setting the SCO bit in FCCS to 1. Make sure that this bit is cleared to 0 before setting the SCO bit to 1 and the value specified by TDA6 to TDA0 is within the range of H'00 to H'03. 0: The value specified by bits TDA6 to TDA0 is within the range. 1: The value specified by is TDA6 to TDA0 is over the range (H'04 to H'FF) and the download is stopped. 6 5 4 3 2 1 0 TDA6 TDA5 TDA4 TDA3 TDA2 TDA1 TDA0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W Transfer Destination Address Specifies the start address to download an on-chip program. H'00 to H'03 can be specified as the start address in the on-chip RAM space. H'00: H'FFE080 is specified as a start address to download an on-chip program. H'01: H'FF0800 is specified as a start address to download an on-chip program. H'02: H'FF1800 is specified as a start address to download an on-chip program. H'03: H'FF8800 is specified as a start address to download an on-chip program. H'04 to H'FF: Setting prohibited. Specifying this value sets the TDER bit to 1 and stops the download.
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Section 25 Flash Memory
25.3.2
Programming/Erasing Interface Parameter
The programming/erasing interface parameter specifies the operating frequency, storage place for program data, programming destination address, and erase block and exchanges the processing result for the downloaded on-chip program. This parameter uses the general registers of the CPU (ER0 and ER1) or the on-chip RAM area. The initial value is undefined at a reset or in hardware standby mode. When download, initialization, or on-chip program is executed, registers of the CPU except for R0L are stored. The return value of the processing result is written in R0L. Since the stack area is used for storing the registers except for R0L, the stack area must be saved at the processing start. (A maximum size of a stack area to be used is 128 bytes.) The programming/erasing interface parameter is used in the following four items. 1. Download control 2. Initialization before programming or erasing 3. Programming 4. Erasing These items use different parameters. The correspondence table is shown in table 25.4. The meaning of the bits in FPFR varies in each processing program: initialization, programming, or erasure. For details, see descriptions of FPFR for each process.
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Section 25 Flash Memory
Table 25.4 Parameters and Target Modes
Name of Parameter Abbrevia- Down tion Load Initialization Programming Erasure R/W R/W R/W Initial Value Undefined Undefined Undefined Allocation On-chip RAM* R0L of CPU ER0 of CPU
Download pass/fail DPFR result Flash pass/fail result Flash programming/ erasing frequency control FPFR FPEFEQ

R/W
Flash multipurpose FMPAR address area Flash multipurpose FMPDR data destination area Flash erase block select FEBS

R/W R/W
Undefined Undefined
ER1 of CPU ER0 of CPU R0L of CPU
R/W
Undefined
Note:
*
A single byte of the start address to download an on-chip program, which is specified by FTDAR
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Section 25 Flash Memory
(1)
Download Control
The on-chip program is automatically downloaded by setting the SCO bit to 1. The on-chip RAM area to be downloaded is the 3-Kbyte area starting from the address specified by FTDAR. Download control is set by the program/erase interface registers, and the DPFR parameter indicates the return value. (a) Download pass/fail result parameter (DPFR: single byte of start address specified by FTDAR)
This parameter indicates the return value of the download result. The value of this parameter can be used to determine if downloading is executed or not. Since the confirmation whether the SCO bit is set to 1 is difficult, the certain determination must be performed by writing the single byte of the start address specified by FTDAR to the value other than the return value of download (for example, H'FF) before the download start (before setting the SCO bit to 1).
Bit 7 to 3 2 Initial Bit Name Value SS R/W R/W Description Unused Return 0 Source Select Error Detect Only one type for the on-chip program which can be downloaded can be specified. When more than two types of the program are selected, the program is not selected, or the program is selected without mapping, error is occurred. 0: Download program can be selected normally 1: Download error is occurred (multi-selection or program which is not mapped is selected) 1 FK R/W Flash Key Register Error Detect Returns the check result whether the value of FKEY is set to H'A5. 0: KEY setting is normal (FKEY = H'A5) 1: Setting value of FKEY becomes error (FKEY = value other than H'A5)
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Section 25 Flash Memory
Bit 0
Initial Bit Name Value SF
R/W R/W
Description Success/Fail Returns the result whether download is ended normally or not. The determination result whether program that is downloaded to the on-chip RAM is read back and then transferred to the on-chip RAM is returned. 0: Downloading on-chip program is ended normally (no error) 1: Downloading on-chip program is ended abnormally (error occurs)
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Section 25 Flash Memory
(2)
Programming/Erasing Initialization
The on-chip programming/erasing program to be downloaded includes the initialization program. The specified period pulse must be applied when programming or erasing. The specified pulse width is made by the method in which wait loop is configured by the CPU instruction. The operating frequency of the CPU must be set. The initial program is set as a parameter of the programming/erasing program which has downloaded these settings. (a) Flash programming/erasing frequency parameter (FPEFEQ: general register ER0 of CPU)
This parameter sets the operating frequency of the CPU. The settable range of the operating frequency in this LSI is 20 to 34 MHz.
Bit Initial Bit Name Value R/W R/W Description Unused This bit should be cleared to 0. 15 to 0 F15 to F0 Frequency Set Set the operating frequency of the CPU. With the PLL multiplication function, set the frequency multiplied. The setting value must be calculated as the following methods. 1. The operating frequency which is shown in MHz units must be rounded in a number to three decimal places and be shown in a number of two decimal places. 2. The value multiplied by 100 is converted to the binary digit and is written to the FPEFEQ parameter (general register ER0). For example, when the operating frequency of the CPU is 33.000 MHz, the value is as follows. 1. The number to three decimal places of 34.000 is rounded and the value is thus 34.00. 2. The formula that 34.00 x 100 = 3400 is converted to the binary digit and B'0000,1101,0100,1000 (H'0D48) is set to ER0.
31 to 16
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Section 25 Flash Memory
(b)
Flash pass/fail parameter (FPFR: general register R0L of CPU)
This parameter indicates the return value of the initialization result.
Bit 7 to 2 1 Initial Bit Name Value FQ R/W R/W Description Unused Return 0 Frequency Error Detect Returns the check result whether the specified operating frequency of the CPU is in the range of the supported operating frequency. 0: Setting of operating frequency is normal 1: Setting of operating frequency is abnormal 0 SF R/W Success/Fail Indicates whether initialization is completed normally. 0: Initialization is ended normally (no error) 1: Initialization is ended abnormally (error occurs)
(3)
Programming Execution
When flash memory is programmed, the programming destination address on the user MAT must be passed to the programming program in which the program data is downloaded. 1. The start address of the programming destination on the user MAT must be stored in a general register ER1. This parameter is called as flash multipurpose address area parameter (FMPAR). Since the program data is always in units of 128 bytes, the lower eight bits (A7 to A0) must be H'00 or H'80 as the boundary of the programming start address on the user MAT. 2. The program data for the user MAT must be prepared in the consecutive area. The program data must be in the consecutive space which can be accessed by using the MOV.B instruction of the CPU and in other than the flash memory space. When data to be programmed does not satisfy 128 bytes, the 128-byte program data must be prepared by filling with the dummy code H'FF. The start address of the area in which the prepared program data is stored must be stored in a general register ER0. This parameter is called as flash multipurpose data destination area parameter (FMPDR). For details on the program processing procedure, see section 25.4.3, User Program Mode.
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Section 25 Flash Memory
(a)
Flash multipurpose address area parameter (FMPAR: general register ER1 of CPU)
This parameter stores the start address of the programming destination on the user MAT. When the address in the area other than flash memory space is set, an error occurs. The start address of the programming destination must be at the 128-byte boundary. If this boundary condition is not satisfied, an error occurs. The error occurrence is indicated by the WA bit (bit 1) in FPFR.
Bit 31 to 0 Initial Bit Name Value MOA31 to MOA0 R/W R/W Description Store the start address of the programming destination on the user MAT. The consecutive 128-byte programming is executed starting from the specified start address of the user MAT. Therefore, the specified programming start address becomes a 128-byte boundary and MOA6 to MOA0 are always 0.
(b)
Flash multipurpose data destination parameter (FMPDR: general register ER0 of CPU):
This parameter stores the start address in the area which stores the data to be programmed in the user MAT. When the storage destination of the program data is in flash memory, an error occurs. The error occurrence is indicated by the WD bit in FPFR.
Bit 31 to 0 Initial Bit Name Value MOD31 to MOD0 R/W R/W Description Store the start address of the area which stores the program data for the user MAT. The consecutive 128byte data is programmed to the user MAT starting from the specified start address.
(c)
Flash pass/fail parameter (FPFR: general register R0L of CPU)
This parameter indicates the return value of the program processing result.
Bit 7 Initial Bit Name Value R/W Description Unused Return 0.
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Section 25 Flash Memory
Bit 6
Initial Bit Name Value MD
R/W R/W
Description Programming Mode Related Setting Error Detect Returns the check result that a high level signal is input to the FWE pin and the error protection state is not entered. When the low level signal is input to the FWE pin or the error protection state is entered, 1 is written to this bit. The state can be confirmed with the FWE and FLER bits in FCCS. For conditions to enter the error protection state, see section 25.5.3, Error Protection. 0: FWE and FLER settings are normal (FWE = 1, FLER = 0) 1: Programming cannot be performed (FWE = 0 or FLER = 1)
5
EE
R/W
Programming Execution Error Detect 1 is returned to this bit when the specified data could not be written because the user MAT was not erased. If this bit is set to 1, there is a high possibility that the user MAT is partially rewritten. In this case, after removing the error factor, erase the user MAT. If FMATS is set to H'AA and the user boot MAT is selected, an error occurs when programming is performed. In this case, both the user MAT and user boot MAT are not rewritten. Programming of the user boot MAT should be performed in boot mode or programmer mode. 0: Programming has ended normally 1: Programming has ended abnormally (programming result is not guaranteed)
4
FK
R/W
Flash Key Register Error Detect Returns the check result of the value of FKEY before the start of the programming processing. 0: FKEY setting is normal (FKEY = H'5A) 1: FKEY setting is error (FKEY = value other than H5A)
3
Unused Returns 0.
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Section 25 Flash Memory
Bit 2
Initial Bit Name Value WD
R/W R/W
Description Write Data Address Detect When the address in the flash memory area is specified as the start address of the storage destination of the program data, an error occurs. 0: Setting of write data address is normal 1: Setting of write data address is abnormal
1
WA
R/W
Write Address Error Detect When the following items are specified as the start address of the programming destination, an error occurs. * * When the programming destination address in the area other than flash memory is specified When the specified address is not in a 128-byte boundary. (The lower eight bits of the address are other than H'00 and H'80.)
0: Setting of programming destination address is normal 1: Setting of programming destination address is abnormal 0 SF R/W Success/Fail Indicates whether the program processing is ended normally or not. 0: Programming is ended normally (no error) 1: Programming is ended abnormally (error occurs)
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Section 25 Flash Memory
(4)
Erasure Execution
When flash memory is erased, the erase-block number on the user MAT must be passed to the erasing program which is downloaded. This is set to the FEBS parameter (general register ER0). One block is specified from the block number 0 to 15. For details on the erasing processing procedure, see section 25.4.3, User Program Mode. (a) Flash erase block select parameter (FEBS: general register ER0 of CPU)
This parameter specifies the erase-block number.
Bit Initial Bit Name Value R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Unused These bits should be cleared to H'0. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EB15 EB14 EB13 EB12 EB11 EB10 EB9 EB8 EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0 Erase Block Set the erase-block number in the range from 0 to 15. 0 corresponds to the EB0 block, and 15 corresponds to the EB15 block.
31 to 16
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Section 25 Flash Memory
(b)
Flash pass/fail parameter (FPFR: general register R0L of CPU)
This parameter returns value of the erasing processing result.
Bit 7 6 Initial Bit Name Value MD R/W R/W Description Unused Return 0. Programming Mode Related Setting Error Detect Returns the check result that a high level signal is input to the FWE pin and the error protection state is not entered. When the low level signal is input to the FWE pin or the error protection state is entered, 1 is written to this bit. The state can be confirmed with the FWE and FLER bits in FCCS. For conditions to enter the error protection state, see section 25.5.3, Error Protection. 0: FWE and FLER settings are normal (FWE = 1, FLER = 0) 1: Programming cannot be performed (FWE = 0 or FLER = 1) 5 EE R/W Erasure Execution Error Detect 1 is returned to this bit when the user MAT could not be erased or when flash-memory related register settings are partially changed. If this bit is set to 1, there is a high possibility that the user MAT is partially erased. In this case, after removing the error factor, erase the user MAT. If FMATS is set to H'AA and the user boot MAT is selected, an error occurs when erasure is performed. In this case, both the user MAT and user boot MAT are not erased. Erasing of the user boot MAT should be performed in boot mode or programmer mode. 0: Erasure has ended normally 1: Erasure has ended abnormally (erasure result is not guaranteed) 4 FK R/W Flash Key Register Error Detect Returns the check result of FKEY value before start of the erasing processing. 0: FKEY setting is normal (FKEY = H'5A) 1: FKEY setting is error (FKEY = value other than H'5A)
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Section 25 Flash Memory
Bit 3
Initial Bit Name Value EB
R/W R/W
Description Erase Block Select Error Detect Returns the check result whether the specified eraseblock number is in the block range of the user MAT. 0: Setting of erase-block number is normal 1: Setting of erase-block number is abnormal
2, 1 0
SF

R/W
Unused Return 0. Success/Fail Indicates whether the erasing processing is ended normally or not. 0: Erasure is ended normally (no error) 1: Erasure is ended abnormally (error occurs)
25.4
On-Board Programming Mode
When the pin is set in on-board programming mode and the reset start is executed, the on-board programming state that can program/erase the on-chip flash memory is entered. On-board programming mode has three operating modes: boot mode, user program mode, and user boot mode. For details of the pin setting for entering each mode, see table 25.5. For details of the state transition of each mode for flash memory, see figure 25.2. Table 25.5 Setting On-Board Programming Mode
Mode Setting Boot mode SCI_1 USB User program mode User boot mode Note: * FWE 1 1 1* 1 MD2 0 0 1 0 MD1 0 0 1 0 NMI 1 1 0/1 0 PF5 0 1
Before downloading the programming/erasing programs, the FLSHE bit must be set to 1 to transition to user program mode.
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Section 25 Flash Memory
25.4.1
Boot Mode
Boot mode executes programming/erasing user MAT and user boot MAT by means of the control command and program data transmitted from the host using the on-chip SCI. The tool for transmitting the control command and program data must be prepared in the host. The SCI communication mode is set to asynchronous mode. When reset start is executed after this LSI's pin is set in boot mode, the boot program in the microcomputer is initiated. After the SCI bit rate is automatically adjusted, the communication with the host is executed by means of the control command method. The system configuration diagram in boot mode is shown in figure 25.6. For details on the pin setting in boot mode, see table 25.5. The NMI and other interrupts are ignored in boot mode. However, the NMI and other interrupts should be disabled in the user system.
This LSI Control command, analysis execution software (on-chip) Flash memory
Host Boot Control command, program data programming tool and program data Reply response
RxD1 On-chip SCI_1 TxD1
On-chip RAM
Figure 25.6 System Configuration in Boot Mode
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Section 25 Flash Memory
(1)
SCI Interface Setting by Host
When boot mode is initiated, this LSI measures the low period of asynchronous SCI-communication data (H'00), which is transmitted consecutively by the host. The SCI transmit/receive format is set to 8-bit data, 1 stop bit, and no parity. This LSI calculates the bit rate of transmission by the host by means of the measured low period and transmits the bit adjustment end sign (1 byte of H'00) to the host. The host must confirm that this bit adjustment end sign (H'00) has been received normally and transmits 1 byte of H'55 to this LSI. When reception is not executed normally, boot mode is initiated again (reset) and the operation described above must be executed. The bit rate between the host and this LSI is not matched by the bit rate of transmission by the host and system clock frequency of this LSI. To operate the SCI normally, the transfer bit rate of the host must be set to 9,600 bps or 19,200 bps. The system clock frequency, which can automatically adjust the transfer bit rate of the host and the bit rate of this LSI, is shown in table 25.6. Boot mode must be initiated in the range of this system clock.
Start bit
D0
D1
D2
D3
D4
D5
D6
D7
Stop bit
Measure low period (9 bits) (data is H'00)
High period of at least 1 bit
Figure 25.7 Automatic-Bit-Rate Adjustment Operation of SCI Table 25.6 System Clock Frequency for Automatic-Bit-Rate Adjustment by This LSI
Bit Rate of Host 9,600 bps 19,200 bps System Clock Frequency 20 to 34 MHz
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Section 25 Flash Memory
(2)
State Transition Diagram
The overview of the state transition diagram after boot mode is initiated is shown in figure 25.8. 1. Bit rate adjustment After boot mode is initiated, the bit rate of the SCI interface is adjusted with that of the host. 2. Waiting for inquiry set command For inquiries about user-MAT size and configuration, MAT start address, and support state, the required information is transmitted to the host. 3. Automatic erasure of all user MAT and user boot MAT After inquiries have finished, all user MAT and user boot MAT are automatically erased. 4. Waiting for programming/erasing command When the program preparation notice is received, the state for waiting program data is entered. The programming start address and program data must be transmitted following the programming command. When programming is finished, the programming start address must be set to H'FFFFFFFF and transmitted. Then the state for waiting program data is returned to the state of programming/erasing command wait. When the erasure preparation notice is received, the state for waiting erase-block data is entered. The erase-block number must be transmitted following the erasing command. When the erasure is finished, the erase-block number must be set to H'FF and transmitted. Then the state for waiting erase-block data is returned to the state for waiting programming/erasing command. The erasure must be used when the specified block is programmed without a reset start after programming is executed in boot mode. When programming can be executed by only one operation, all blocks are erased before the state for waiting programming/erasing/other command is entered. The erasing operation is not required. There are many commands other than programming/erasing. Examples are sum check, blank check (erasure check), and memory read of the user MAT/user boot MAT and acquisition of current status information. Note that memory read of the user MAT/user boot MAT can only read the programmed data after all user MAT/user boot MAT has automatically been erased.
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Section 25 Flash Memory
(Bit rate adjustment)
H'00.......H'00 reception H'00 transmission Boot mode initiation (reset by boot mode)
(adjustment completed)
Bit rate adjustment
H'55 rece ption
1.
2.
Wait for inquiry setting command
Inquiry command reception
Inquiry command response
Processing of inquiry setting command
3.
All user MAT and user boot MAT erasure
Read/check command reception Command response
4.
Wait for programming/erasing command
Processing of read/check command
(Erasure selection command reception) (Erasure end notice) (Program end notice) (Program command reception) (Program data transmission) (Erase-block specification)
Wait for erase-block data
Wait for program data
Figure 25.8 Overview of Boot Mode State Transition Diagram
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Section 25 Flash Memory
25.4.2
USB Boot Mode
The H8S/2472 Group supports the USB boot mode. USB boot mode executes programming/erasing of the user MAT by means of the control command and program data transmitted from the externally connected host via the USB. In USB boot mode, the tool for transmitting the control command and program data, and the program data must be prepared in the host. The system configuration in USB boot mode is shown in figure 25.9. Interrupts are ignored in USB boot mode. Configure the user system so that interrupts do not occur.
Host or self-power HUB PUPDPLS
Software for analyzing control commands (on-chip)
This LSI
PF5 MD2 MD1
1 0 0
Flash memory
1.5 k Rs Programming tool and program data Rs Data transmission/ reception VBUS USB+ USBUSB On-chip RAM
Figure 25.9 System Configuration in USB Boot Mode
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Section 25 Flash Memory
(1)
Features
* For enumeration information, refer to table 25.7. Table 25.7 Enumeration Information
USB standard Transfer mode Maximum power consumption Endpoint configuration Ver.2.0 (Full speed) Transfer mode Control (in, out), Bulk (in, out) 100 mA EP0 Control (in out) 8 bytes Configuration 1 InterfaceNumber0 AlternateSetting0 EP1 Bulk (out) 64 bytes EP2 Bulk (in) 64 bytes
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Section 25 Flash Memory
(2)
State Transition Diagram
The state transition after USB boot mode is initiated is shown in figure 25.10.
Boot mode initiation (reset by boot mode)
H'55 rece ption
Enumeration
1.
Inquiry command reception
2.
Wait for inquiry setting command Inquiry command response
Processing of inquiry setting command
3.
All user MAT erasure
4.
Wait for inquiry programming/erasing command
(Era
Read/check command reception Processing of read/check command Command response (Er com asure sur s ma e co nd electio mp rec letio ept n n) ion )
(Erase-block specification) Wait for inquiry programming/erasing command
(Programming completion)
(Program selection command reception) (Program data transmission)
Wait for inquiry programming/erasing command
Figure 25.10 USB Boot Mode State Transition Diagram 1. After a transition to the USB boot mode is made, the boot program embedded in this LSI is initialized. This LSI performs enumeration to the host after the USB boot program is initialized. 2. Inquiry information about the size, configuration, start address, and support status of the user MAT is transmitted to the host. 3. After inquiries have finished, all user MAT are automatically erased.
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Section 25 Flash Memory
4. After all user MAT are automatically erased, the state of waiting for programming/erasing command is entered. When the programming command is received, the state shifts to the state of waiting for programming data. The same applies to erasing. In addition to the commands for programming/erasing, there are commands for performing sum check, blank check (erasure check), and memory read of the user MAT, and acquiring the current status information. (3) Notes on USB Boot Mode Execution
* The clock of 48 MHz needs to be supplied to the USB module. Set the external clock frequency and clock pulse generator so as to supply 48 MHz as the clock for the USB (cku). For details, refer to section 22, USB Function Module (USB). * If the bus powered HUB is disconnected during the flash memory programming and erasing, permanent damage to the LSI may result.
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Section 25 Flash Memory
25.4.3
User Program Mode
The user MAT can be programmed/erased in user program mode. (The user boot MAT cannot be programmed/erased.) Programming/erasing is executed by downloading the program in the microcomputer. The overview flow is shown in figure 25.11. High voltage is applied to internal flash memory during the programming/erasing processing. Therefore, transition to reset or hardware standby must not be executed. Doing so may damage or destroy flash memory. If reset is executed accidentally, reset must be released after the reset input period of 100 s which is longer than normal.
Programming/erasing start
1. Make sure that the program data will not overlap the download destination specified by FTDAR.
When programming, program data is prepared
2. The FWE bit is set to 1 by inputting a high level signal to the FWE pin. 3. Programming/erasing is executed only in the on-chip RAM. However, if program data is in a consecutive area and can be accessed by the MOV.B instruction of the CPU like RAM or ROM, the program data can be in an external space. 4. After programming/erasing is finished, input a low level signal to the FWE pin and transfer to the hardware protection state.
Programming/erasing procedure program is transferred to the on-chip RAM and executed
Programming/erasing end
Figure 25.11 Programming/Erasing Overview Flow
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Section 25 Flash Memory
(1)
On-chip RAM Address Map when Programming/Erasing is Executed
Parts of the procedure program that are made by the user, like download request, programming/erasing procedure, and determination of the result, must be executed in the on-chip RAM. The on-chip program that is to be downloaded is all in the on-chip RAM. Note that area in the on-chip RAM must be controlled so that these parts do not overlap. Figure 25.12 shows the program area to be downloaded.

Area that can be used by user* DPFR (Return value: 1 byte) System use area (15 bytes) Programming/erasing program entry Initialization program entry Initialization + programming program or Initialization + erasing program Area that can be used by user* FTDAR setting + 3 Kbytes RAMEND FTDAR setting + 16 FTDAR setting + 32 FTDAR setting
Address
RAMTOP
Area to be downloaded (Size : 3 Kbytes) Unusable area in programming/erasing processing period
Note: * The on-chip RAM area in this LSI is split into H'FF0800 to H'FF97FF, H'FFE080 to H'FFEFFF, and H'FFFF00 to H'FFFF7F. The area that can be used by the user is specified by FTDAR.
Figure 25.12 RAM Map When Programming/Erasing is Executed
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Section 25 Flash Memory
(2)
Programming Procedure in User Program Mode
The procedures for download, initialization, and programming are shown in figure 25.13.
Start programming procedure program Select on-chip program to be downloaded and specify download destination by FTDAR Set FKEY to H'A5
1 1. 2. 3. 4. 5.
No
Disable interrupts and bus master operation other than CPU Set FKEY to H'5A
9. 10.
Download
Set SCO to 1 and execute download Clear FKEY to 0
Programming
Set parameters to ER1 and ER0 (FMPAR and FMPDR) Programming JSR FTDAR setting + 16
11. 12. 13.
No
Clear FKEY and programming error processing
DPFR = 0? Yes
Set the FPEFEQ parameter
FPFR = 0? Yes No
Required data programming is completed?
Download error processing
6. 7. 8.
No
Initialization
Initialization JSR FTDAR setting + 32
14. 15.
Yes
Clear FKEY to 0 End programming procedure program
FPFR = 0? Yes
Initialization error processing
1
Figure 25.13 Programming Procedure The procedure program must be executed in an area other than the flash memory to be programmed. Especially the part where the SCO bit in FCCS is set to 1 for downloading must be executed in the on-chip RAM. The area that can be executed in the steps of the user procedure program (on-chip RAM, user MAT, and external space) is shown in section 25.4.5, Procedure Program and Storable Area for Programming Data. The following description assumes the area to be programmed on the user MAT is erased and program data is prepared in the consecutive area. When erasing is not executed, erasing is executed before writing.
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Section 25 Flash Memory
128-byte programming is performed in one program processing. When more than 128-byte programming is performed, programming destination address/program data parameter is updated in 128-byte units and programming is repeated. When less than 128-byte programming is performed, data must total 128 bytes by adding the invalid data. If the dummy data to be added is H'FF, the program processing period can be shortened. 1. Select the on-chip program to be downloaded and specify a download destination When the PPVS bit of FPCS is set to 1, the programming program is selected. Several programming/erasing programs cannot be selected at one time. If several programs are set, download is not performed and a download error is returned to the SS bit in DPFR. The start address of a download destination is specified by FTDAR. 2. Program H'A5 in FKEY If H'A5 is not written to FKEY for protection, 1 cannot be set to the SCO bit for download request. 3. 1 is set to the SCO bit of FCCS and then download is executed. To set 1 to the SCO bit, the following conditions must be satisfied. H'A5 is written to FKEY. The SCO bit writing is executed in the on-chip RAM. When the SCO bit is set to 1, download is started automatically. When the SCO bit is returned to the user procedure program, the SCO is cleared to 0. Therefore, the SCO bit cannot be confirmed to be 1 in the user procedure program. The download result can be confirmed only by the return value of DPFR. Before the SCO bit is set to 1, incorrect determination must be prevented by setting the one byte of the start address (to be used as DPFR) specified by FTDAR to a value other than the return value (e.g. H'FF). When download is executed, particular interrupt processing, which is accompanied by the bank switch as described below, is performed as an internal microcomputer processing. Four NOP instructions are executed immediately after the instructions that set the SCO bit to 1. The user-MAT space is switched to the on-chip program storage area. After the selection condition of the download program and the FTDAR setting are checked, the transfer processing to the on-chip RAM specified by FTDAR is executed. The SCO bit in FCCS is cleared to 0. The return value is set to the DPFR parameter.
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Section 25 Flash Memory
After the on-chip program storage area is returned to the user-MAT space, the user procedure program is returned. In the download processing, the values of general registers of the CPU are held. In the download processing, any interrupts are not accepted. However, interrupt requests are held. Therefore, when the user procedure program is returned, the interrupts occur. When the level-detection interrupt requests are to be held, interrupts must be input until the download is ended. When hardware standby mode is entered during download processing, the normal download cannot be guaranteed in the on-chip RAM. Therefore, download must be executed again. Since a stack area of 128 bytes at the maximum is used, the area must be allocated before setting the SCO bit to 1. If a flash memory access by the DTC signal is requested during downloading, the operation cannot be guaranteed. Therefore, an access request by the DTC signal must not be generated. 4. FKEY is cleared to H'00 for protection. 5. The value of the DPFR parameter must be checked and the download result must be confirmed. Check the value of the DPFR parameter (one byte of start address of the download destination specified by FTDAR). If the value is H'00, download has been performed normally. If the value is not H'00, the source that caused download to fail can be investigated by the description below. If the value of the DPFR parameter is the same as before downloading (e.g. H'FF), the address setting of the download destination in FTDAR may be abnormal. In this case, confirm the setting of the TDER bit (bit 7) in FTDAR. If the value of the DPFR parameter is different from before downloading, check the SS bit (bit 2) and the FK bit (bit 1) in the DPFR parameter to ensure that the download program selection and FKEY setting were normal, respectively. 6. The operating frequency is set in the FPEFEQ parameter for initialization. The current frequency of the CPU clock is set to the FPEFEQ parameter value (general register ER0). The settable range of the FPEFEQ parameter is 20 to 34 MHz. When the frequency is set to out of this range, an error is returned to the FPFR parameter of the initialization program and initialization is not performed. For details on the frequency setting, see the description in 25.3.2 (2) (a), Flash programming/erasing frequency parameter (FPEFEQ: general register ER0 of CPU).
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Section 25 Flash Memory
7. Initialization When a programming program is downloaded, the initialization program is also downloaded to the on-chip RAM. There is an entry point of the initialization program in the area from the start address specified by FTDAR + 32 bytes of the on-chip RAM. The subroutine is called and initialization is executed by using the following steps. MOV.L JSR NOP The general registers other than R0L are held in the initialization program. R0L is a return value of the FPFR parameter. Since the stack area is used in the initialization program, 128-byte stack area at the maximum must be allocated in RAM. Interrupts can be accepted during the execution of the initialization program. The program storage area and stack area in the on-chip RAM and register values must not be destroyed. 8. The return value in the initialization program, FPFR (general register R0L) is determined. 9. All interrupts and the use of a bus master other than the CPU are prohibited. The specified voltage is applied for the specified time when programming or erasing. If interrupts occur or the bus mastership is moved to other than the CPU during this time, the voltage for more than the specified time will be applied and flash memory may be damaged. Therefore, interrupts and bus mastership to other than the CPU, such as to the DTC, are prohibited. To disable interrupts, bit 7 (I) in the condition code register (CCR) of the CPU should be set to B'1 in interrupt control mode 0 or bits 7 and 6 (I and UI) should be set to B'11 in interrupt control mode 1. Interrupts other than NMI are held and not executed. The NMI interrupts must be masked within the user system. The interrupts that are held must be executed after all program processing. When the bus mastership is moved to other than the CPU, such as to the DTC, the error protection state is entered. Therefore, taking bus mastership by the DTC is prohibited. 10. FKEY must be set to H'5A and the user MAT must be prepared for programming. #DLTOP+32,ER2 @ER2 ; Set entry address to ER2 ; Call initialization routine
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Section 25 Flash Memory
11. The parameter which is required for programming is set. The start address of the programming destination of the user MAT (FMPAR) is set to general register ER1. The start address of the program data area (FMPDR) is set to general register ER0. Example of the FMPAR setting FMPAR specifies the programming destination address. When an address other than one in the user MAT area is specified, even if the programming program is executed, programming is not executed and an error is returned to the return value parameter FPFR. Since the unit is 128 bytes, the lower eight bits of the address must be H'00 or H'80 as the boundary of 128 bytes. Example of the FMPDR setting When the storage destination of the program data is flash memory, even if the program execution routine is executed, programming is not executed and an error is returned to the FPFR parameter. In this case, the program data must be transferred to the on-chip RAM and then programming must be executed. 12. Programming There is an entry point of the programming program in the area from the start address specified by FTDAR + 16 bytes of the on-chip RAM. The subroutine is called and programming is executed by using the following steps. MOV.L JSR NOP The general registers other than R0L are held in the programming program. R0L is a return value of the FPFR parameter. Since the stack area is used in the programming program, a stack area of 128 bytes at the maximum must be allocated in RAM. 13. The return value in the programming program, FPFR (general register R0L) is determined. 14. Determine whether programming of the necessary data has finished. If more than 128 bytes of data are to be programmed, specify FMPAR and FMPDR in 128byte units, and repeat steps 12 to 14. Increment the programming destination address by 128 bytes and update the programming data pointer correctly. If an address which has already been programmed is written to again, not only will a programming error occur, but also flash memory will be damaged. #DLTOP+16,ER2 @ER2 ; Set entry address to ER2 ; Call programming routine
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Section 25 Flash Memory
15. After programming finishes, clear FKEY and specify software protection. If this LSI is restarted by a reset immediately after user MAT programming has finished, secure the reset period (period of RES = 0) of 100 s which is longer than normal. (3) Erasing Procedure in User Program Mode
The procedures for download, initialization, and erasing are shown in figure 25.14.
Start erasing procedure program
1
Select on-chip program to be downloaded and specify download destination by FTDAR Set FKEY to H'A5
1.
Disable interrupts and bus master operation other than CPU Set FKEY to H'5A
Download
Set SCO to 1 and execute download
Set FEBS parameter Erasing JSR FTDAR setting + 16 FPFR = 0 ?
2. 3. 4.
No
DPFR = 0?
No
Download error processing
Yes
Set the FPEFEQ parameter
Erasing
Clear FKEY to 0
Yes No
Required block erasing is completed?
Clear FKEY and erasing error processing
Initialization
5. 6.
Initialization JSR FTDAR setting + 32 FPFR = 0 ?
Yes
Clear FKEY to 0
No Yes Initialization error processing
End erasing procedure program
1
Figure 25.14 Erasing Procedure The procedure program must be executed in an area other than the user MAT to be erased. Especially the part where the SCO bit in FCCS is set to 1 for downloading must be executed in the on-chip RAM. The area that can be executed in the steps of the user procedure program (on-chip RAM, user MAT, and external space) is shown in section 25.4.5, Procedure Program and Storable Area for Programming Data.
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Section 25 Flash Memory
For the downloaded on-chip program area, refer to the RAM map for programming/erasing in figure 25.12. A single divided block is erased by one erasing processing. For block divisions, refer to figure 25.4. To erase two or more blocks, update the erase block number and perform the erasing processing for each block. 1. Select the on-chip program to be downloaded Set the EPVB bit in FECS to 1. Several programming/erasing programs cannot be selected at one time. If several programs are set, download is not performed and a download error is reported to the SS bit in the DPFR parameter. Specify the start address of a download destination by FTDAR. The procedures to be carried out after setting FKEY, e.g. download and initialization, are the same as those in the programming procedure. For details, refer to Programming Procedure in User Program Mode in section 25.4.3 (2), Programming Procedure in User Program Mode. The procedures after setting parameters for erasing programs are as follows: 2. Set the FEBS parameter necessary for erasure Set the erase block number of the user MAT in the flash erase block select parameter FEBS (general register ER0). If a value other than an erase block number of the user MAT is set, no block is erased even though the erasing program is executed, and an error is returned to the return value parameter FPFR. 3. Erasure Similar to as in programming, there is an entry point of the erasing program in the area from the start address of a download destination specified by FTDAR + 16 bytes of on-chip RAM. The subroutine is called and erasing is executed by using the following steps. MOV.L JSR NOP * * * The general registers other than R0L are held in the erasing program. R0L is a return value of the FPFR parameter. Since the stack area is used in the erasing program, a stack area of 128 bytes at the maximum must be allocated in RAM. #DLTOP+16,ER2 @ER2 ; Set entry address to ER2 ; Call erasing routine
4. The return value in the erasing program, FPFR (general register R0L) is determined.
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Section 25 Flash Memory
5. Determine whether erasure of the necessary blocks has completed. If more than one block is to be erased, update the FEBS parameter and repeat steps 2 to 5. Blocks that have already been erased can be erased again. 6. After erasure completes, clear FKEY and specify software protection. If this LSI is restarted by a reset immediately after user MAT erasure has completed, secure the reset period (period of RES = 0) of 100 s which is longer than normal. (4) Erasing and Programming Procedure in User Program Mode
By changing the on-chip RAM address of the download destination in FTDAR, the erasing program and programming program can be downloaded to separate on-chip RAM areas. Figure 25.15 shows a repeating procedure of erasing and programming.
Start procedure program Specify a download destination of erasing program by FTDAR
Erasing program download
1
Erase relevant block (execute erasing program)
Download erasing program
Erasing/ Programming
Initialize erasing program
Specify a download destination of programming program by FTDAR
Set FMPDR to program relevant block (execute programming program)
Programming program download
Confirm operation
Download programming program Initialize programming program
End ?
No Yes
End procedure program
1
Figure 25.15 Repeating Procedure of Erasing and Programming In the above procedure, download and initialization are performed only once at the beginning. In this kind of operation, note the following:
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Section 25 Flash Memory
*
Be careful not to damage on-chip RAM with overlapped settings. In addition to the erasing program area and programming program area, areas for the user procedure programs, work area, and stack area are reserved in on-chip RAM. Do not make settings that will overwrite data in these areas.
*
Be sure to initialize both the erasing program and programming program. Initialization by setting the FPEFEQ parameter must be performed for both the erasing program and the programming program. Initialization must be executed for both entry addresses: (download start address for erasing program) + 32 bytes and (download start address for programming program) + 32 bytes.
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Section 25 Flash Memory
25.4.4
User Boot Mode
This LSI has user boot mode which is initiated with different mode pin settings than those in boot mode or user program mode. User boot mode is a user-arbitrary boot mode, unlike boot mode that uses the on-chip SCI. Only the user MAT can be programmed/erased in user boot mode. Programming/erasing of the user boot MAT is only enabled in boot mode or programmer mode. (1) User Boot Mode Initiation
For the mode pin settings to start up user boot mode, see table 25.5. When the reset start is executed in user boot mode, the built-in check routine runs. The user MAT and user boot MAT states are checked by this check routine. While the check routine is running, NMI and all other interrupts cannot be accepted. Next, processing starts from the execution start address of the reset vector in the user boot MAT. At this point, HAA is set to FMATS because the execution MAT is the user boot MAT. (2) User MAT Programming in User Boot Mode
For programming the user MAT in user boot mode, additional processing made by setting FMATS are required: switching from user-boot-MAT selection state to user-MAT selection state, and switching back to user-boot-MAT selection state after programming completes. Figure 25.16 shows the procedure for programming the user MAT in user boot mode.
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Section 25 Flash Memory
Start programming procedure program
Select on-chip program to be downloaded and specify download destination by FTDAR Set FKEY to H'A5
1
MAT switchover
Set FMATS to value other than H'AA to select user MAT
User-boot-MAT selection state
Download
Set SCO to 1 and execute download
Set FKEY to H'A5
User-MAT selection state
Clear FKEY to 0
DPFR = 0 ? Yes
Set parameter to ER0 and ER1 (FMPAR and FMPDR)
No
Programming
Programming JSR FTDAR setting + 16
FPFR = 0 ?
Download error processing
Initialization
Set the FPEFEQ parameters Initialization JSR FTDAR setting + 32
FPFR = 0 ?
No Yes Clear FKEY and programming error processing
No
Required data programming is completed?
Yes
No
Clear FKEY to 0
Yes Initialization error processing
Disable interrupts and bus master operation other than CPU
Set FMATS to H'AA to select user boot MAT
End programming procedure program
MAT switchover
1
User-boot-MAT selection state
Note: The MAT must be switched by FMATS to perform the programming error processing in the user boot MAT.
Figure 25.16 Procedure for Programming User MAT in User Boot Mode The difference between the programming procedures in user program mode and user boot mode is whether the MAT is switched or not as shown in figure 25.16. In user boot mode, the user boot MAT can be seen in the flash memory space with the user MAT hidden in the background. The user MAT and user boot MAT are switched only while the user MAT is being programmed. Because the user boot MAT is hidden while the user MAT is being programmed, the procedure program must be located in an area other than flash memory. After programming completes, switch the MATs again to return to the first state. MAT switching is enabled by writing a specific value to FMATS. However note that while the MATs are being switched, the LSI is in an unstable state, e.g. access to a MAT is not allowed until MAT switching is completed, and if an interrupt occurs, from which MAT the interrupt vector is
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Section 25 Flash Memory
read is undetermined. Perform MAT switching in accordance with the description in section 25.6, Switching between User MAT and User Boot MAT. Except for MAT switching, the programming procedure is the same as that in user program mode. The area that can be executed in the steps of the user procedure program (on-chip RAM, user MAT, and external space) is shown in section 25.4.5, Procedure Program and Storable Area for Programming Data.
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Section 25 Flash Memory
(3)
User MAT Erasing in User Boot Mode
For erasing the user MAT in user boot mode, additional processing made by setting FMATS are required: switching from user-boot-MAT selection state to user-MAT selection state, and switching back to user-boot-MAT selection state after erasing completes. Figure 25.17 shows the procedure for erasing the user MAT in user boot mode.
Start erasing procedure program
Select on-chip program to be downloaded and specify download destination by FTDAR Set FKEY to H'A5
1
MAT switchover
Set FMATS to value other than H'AA to select user MAT
User-boot-MAT selection state
Download
Set SCO to 1 and execute download
Set FKEY to H'A5
User-MAT selection state
Clear FKEY to 0
DPFR = 0 ?
Set FEBS parameter
Programming JSR FTDAR setting + 16
FPFR = 0 ?
No
Yes
Download error processing
Erasing
Initialization
Set the FPEFEQ parameters Initialization JSR FTDAR setting + 32
FPFR = 0 ?
No
Yes No
No Clear FKEY and erasing error processing
Required block erasing is completed?
Yes
Clear FKEY to 0
Yes Initialization error processing
Disable interrupts and bus master operation other than CPU
Set FMATS to H'AA to select user boot MAT
End erasing procedure program
MAT switchover
1
User-boot-MAT selection state
Note: The MAT must be switched by FMATS to perform the erasing error processing in the user boot MAT.
Figure 25.17 Procedure for Erasing User MAT in User Boot Mode The difference between the erasing procedures in user program mode and user boot mode depends on whether the MAT is switched or not as shown in figure 25.17.
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Section 25 Flash Memory
MAT switching is enabled by writing a specific value to FMATS. However note that while the MATs are being switched, the LSI is in an unstable state, e.g. access to a MAT is not allowed until MAT switching is completed, and if an interrupt occurs, from which MAT the interrupt vector is read is undetermined. Perform MAT switching in accordance with the description in section 25.6, Switching between User MAT and User Boot MAT. Except for MAT switching, the erasing procedure is the same as that in user program mode. The area that can be executed in the steps of the user procedure program (on-chip RAM, user MAT, and external space) is shown in section 25.4.5, Procedure Program and Storable Area for Programming Data.
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Section 25 Flash Memory
25.4.5
Procedure Program and Storable Area for Programming Data
In the descriptions in the previous section, the programming/erasing procedure programs and storable areas for program data are assumed to be in the on-chip RAM. However, the program and the data can be stored in and executed from other areas, such as part of flash memory which is not to be programmed or erased, or somewhere in the external address space. (1) Conditions that Apply to Programming/Erasing
1. The on-chip programming/erasing program is downloaded from the address in the on-chip RAM specified by FTDAR, therefore, this area is not available for use. 2. The on-chip programming/erasing program will use 128 bytes at the maximum as a stack. So, make sure that this area is secured. 3. Download by setting the SCO bit to 1 will lead to switching of the MAT. If, therefore, this operation is used, it should be executed from the on-chip RAM. 4. The flash memory is accessible until the start of programming or erasing, that is, until the result of downloading has been determined. When in a mode in which the external address space is not accessible, such as single-chip mode, the required procedure programs, NMI handling vector and NMI handler should be transferred to the on-chip RAM before programming/erasing of the flash memory starts. 5. The flash memory is not accessible during programming/erasing operations, therefore, the operation program is downloaded to the on-chip RAM to be executed. The NMI-handling vector and programs such as that which activate the operation program, and NMI handler should thus be stored in on-chip memory other than flash memory or the external address space. 6. After programming/erasing, the flash memory should be inhibited until FKEY is cleared. The reset state (RES = 0) must be in place for more than 100 s when the LSI mode is changed to reset on completion of a programming/erasing operation. Transitions to the reset state, and hardware standby mode are inhibited during programming/erasing. When the reset signal is accidentally input to the chip, a longer period in the reset state than usual (100 s) is needed before the reset signal is released. 7. Switching of the MATs by FMATS should be needed when programming/erasing of the user boot MAT is operated in user-boot mode. The program which switches the MATs should be executed from the on-chip RAM. See section 25.6, Switching between User MAT and User Boot MAT. Please make sure you know which MAT is selected when switching between them. 8. When the data storable area indicated by programming parameter FMPDR is within the flash memory area, an error will occur even when the data stored is normal. Therefore, the data
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Section 25 Flash Memory
should be transferred to the on-chip RAM to place the address that FMPDR indicates in an area other than the flash memory. In consideration of these conditions, there are three factors; operating mode, the bank structure of the user MAT, and operations. The areas in which the programming data can be stored for execution are shown in tables. Table 25.8 Executable MAT
Initiated Mode Operation Programming Erasing Note: * User Program Mode Table 25.9 (1) Table 25.9 (2) Programming/Erasing is possible to user MATs. User Boot Mode* Table 25.9 (3) Table 25.9 (4)
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Section 25 Flash Memory
Table 25.9 (1)
Useable Area for Programming in User Program Mode
Storable /Executable Area On-chip RAM User MAT x* Selected MAT
Item Storage Area for Program Data Operation for Selection of On-chip Program to be Downloaded Operation for Writing H'A5 to FKEY Execution of Writing SCO = 1 to FCCS (Download) Operation for FKEY Clear Determination of Download Result Operation for Download Error Operation for Settings of Initial Parameter Execution of Initialization Determination of Initialization Result Operation for Initialization Error NMI Handling Routine Operation for Inhibit of Interrupt Operation for Writing H'5A to FKEY Operation for Settings of Program Parameter
Embedded Program External Space (Expanded Mode) User MAT Storage Area
x
x
x
x
x
x
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Section 25 Flash Memory
Storable /Executable Area On-chip RAM User MAT x x x x
Selected MAT
Item Execution of Programming Determination of Program Result Operation for Program Error Operation for FKEY Clear Note: *
Embedded Program External Space (Expanded Mode) User MAT Storage Area x
Transferring the data to the on-chip RAM enables this area to be used.
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Section 25 Flash Memory
Table 25.9 (2)
Useable Area for Erasure in User Program Mode
Storable /Executable Area On-chip RAM User MAT Selected MAT
Item Operation for Selection of On-chip Program to be Downloaded Operation for Writing H'A5 to FKEY Execution of Writing SCO = 1 to FCCS (Download) Operation for FKEY Clear Determination of Download Result Operation for Download Error Operation for Settings of Initial Parameter Execution of Initialization Determination of Initialization Result Operation for Initialization Error NMI Handling Routine Operation for Inhibit of Interrupt Operation for Writing H'5A to FKEY Operation for Settings of Erasure Parameter Execution of Erasure Determination of Erasure Result
Embedded Program External Space (Expanded Mode) User MAT Storage Area
x
x
x
x
x
x x x x
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Section 25 Flash Memory
Storable /Executable Area On-chip RAM User MAT x x
Selected MAT
Item Operation for Erasure Error Operation for FKEY Clear
Embedded Program External Space (Expanded Mode) User MAT Storage Area
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Section 25 Flash Memory
Table 25.9 (3)
Useable Area for Programming in User Boot Mode
Storable/Executable Area On-chip RAM User Boot External Space User MAT (Expanded Mode) MAT x*
1
Selected MAT User Boot MAT Embedded Program Storage Area
Item Storage Area for Program Data Operation for Selection of On-chip Program to be Downloaded Operation for Writing H'A5 to FKEY Execution of Writing SCO = 1 to FCCS (Download) Operation for FKEY Clear Determination of Download Result Operation for Download Error Operation for Settings of Initial Parameter Execution of Initialization Determination of Initialization Result Operation for Initialization Error NMI Handling Routine Operation for Interrupt Inhibit Switching MATs by FMATS Operation for Writing H'5A to FKEY
x
x
x
x
x
x x
x
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Section 25 Flash Memory
Storable/Executable Area On-chip RAM User Boot External Space User MAT (Expanded Mode) MAT x
Selected MAT User Boot MAT Embedded Program Storage Area
Item Operation for Settings of Program Parameter Execution of Programming Determination of Program Result Operation for Program Error Operation for FKEY Clear Switching MATs by FMATS
x x x* x x
2
x
x
Notes: 1. Transferring the data to the on-chip RAM enables this area to be used. 2. Switching FMATS by a program in the on-chip RAM enables this area to be used.
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Section 25 Flash Memory
Table 25.9 (4)
Useable Area for Erasure in User Boot Mode
Storable/Executable Area On-chip RAM User Boot External Space User MAT (Expanded Mode) MAT Selected MAT User Boot MAT Embedded Program Storage Area
Item Operation for Selection of On-chip Program to be Downloaded Operation for Writing H'A5 to FKEY Execution of Writing SCO = 1 to FCCS (Download) Operation for FKEY Clear Determination of Download Result Operation for Download Error Operation for Settings of Initial Parameter Execution of Initialization Determination of Initialization Result Operation for Initialization Error NMI Handling Routine Operation for Interrupt Inhibit Switching MATs by FMATS Operation for Writing H'5A to FKEY
x
x
x
x
x
x x
x
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Section 25 Flash Memory
Storable/Executable Area On-chip RAM User Boot External Space User MAT (Expanded Mode) MAT x
Selected MAT User Boot MAT Embedded Program Storage Area
Item Operation for Settings of Erasure Parameter Execution of Erasure Determination of Erasure Result Operation for Erasure Error Operation for FKEY Clear Switching MATs by FMATS Note: *
x x x* x x
x
x
Switching FMATS by a program in the on-chip RAM enables this area to be used.
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Section 25 Flash Memory
25.5
Protection
There are three kinds of flash memory program/erase protection: hardware, software, and error protection. 25.5.1 Hardware Protection
Programming and erasing of flash memory is forcibly disabled or suspended by hardware protection. In this state, the downloading of an on-chip program and initialization are possible. However, an activated program for programming or erasure cannot program or erase locations in a user MAT, and the error in programming/erasing is reported in the parameter FPFR.
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Section 25 Flash Memory
Table 25.10 Hardware Protection
Function to be Protected Item FWE pin protection Description * Download Program/Erase When a low level signal is input to the FWE pin, the FWE bit in FCCS is cleared and the program/eraseprotected state is entered. The program/erase interface registers are initialized in the reset state (including a reset by the WDT) and standby mode and the program/eraseprotected state is entered. The reset state will not be entered by a reset using the RES pin unless the RES pin is held low until oscillation has stabilized after power is initially supplied. In the case of a reset during operation, hold the RES pin low for the RES pulse width that is specified in the section on AC characteristics section. If a reset is input during programming or erasure, data values in the flash memory are not guaranteed. In this case, execute erasure and then execute program again.
Reset/standby protection
*
*
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Section 25 Flash Memory
25.5.2
Software Protection
Software protection is set up in any of two ways: by disabling the downloading of on-chip programs for programming and erasing and by means of a key code. Table 25.11 Software Protection
Function to be Protected Item Protection by the SCO bit Description * The program/erase-protected state is entered by clearing the SCO bit in FCCS which disables the downloading of the programming/erasing programs. Downloading and programming/erasing are disabled unless the required key code is written in FKEY. Different key codes are used for downloading and for programming/erasing. Download Program/Erase
Protection by the FKEY register
*
25.5.3
Error Protection
Error protection is a mechanism for aborting programming or erasure when an error occurs, in the form of the microcomputer entering runaway during programming/erasing of the flash memory or operations that are not according to the established procedures for programming/erasing. Aborting programming or erasure in such cases prevents damage to the flash memory due to excessive programming or erasing. If the microcomputer malfunctions during programming/erasing of the flash memory, the FLER bit in the FCCS register is set to 1 and the error-protection state is entered, and this aborts the programming or erasure. The FLER bit is set in the following conditions: 1. When an interrupt such as NMI occurs during programming/erasing. 2. When the flash memory is read during programming/erasing (including a vector read or an instruction fetch). 3. When a SLEEP instruction (including software-standby mode) is executed during programming/erasing.
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Section 25 Flash Memory
4. When a bus master other than the CPU, such as the DTC, gets bus mastership during programming/erasing. Error protection is cancelled only by a reset or by hardware-standby mode. Note that the reset should be released after the reset period of 100 s which is longer than normal. Since high voltages are applied during programming/erasing of the flash memory, some voltage may remain after the error-protection state has been entered. For this reason, it is necessary to reduce the risk of damage to the flash memory by extending the reset period so that the charge is released. The state-transition diagram in figure 25.18 shows transitions to and from the error-protection state.
Program mode Erase mode
Read disabled Programming/erasing enabled FLER = 0
RES = 0 or STBY = 0
Reset or hardware standby (Hardware protection) Read disabled Programming/erasing disabled FLER = 0
Program/erase interface register is in its initial state.
Er
Error occurrence
r 0o 0 cu S= (S E Y= oft rred R TB wa S RES = 0 or re sta STBY = 0 nd by )
ror
oc
Error protection mode
Read enabled Programming/erasing disabled FLER = 1
Software-standby mode
Error-protection mode (Software standby)
Read disabled Cancel programming/erasing disabled software-standby mode FLER = 1
Program/erase interface register is in its initial state.
Figure 25.18 Transitions to Error-Protection State
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Section 25 Flash Memory
25.6
Switching between User MAT and User Boot MAT
It is possible to alternate between the user MAT and user boot MAT. However, the following procedure is required because these MATs are allocated to address 0. (Switching to the user boot MAT disables programming and erasing. Programming of the user boot MAT should take place in boot mode or programmer mode.) 1. MAT switching by FMATS should always be executed from the on-chip RAM. 2. To ensure that the MAT that has been switched to is accessible, execute four NOP instructions in the on-chip RAM immediately after writing to FMATS of the on-chip RAM (this prevents access to the flash memory during MAT switching). 3. If an interrupt has occurred during switching, there is no guarantee of which memory MAT is being accessed. Always mask the maskable interrupts before switching between MATs. In addition, configure the system so that NMI interrupts do not occur during MAT switching. 4. After the MATs have been switched, take care because the interrupt vector table will also have been switched. If interrupt processing is to be the same before and after MAT switching, transfer the interrupt-processing routines to the on-chip RAM and set the WEINTE bit in FCCS to place the interrupt-vector table in the on-chip RAM. 5. Memory sizes of the user MAT and user boot MAT are different. When accessing the user boot MAT, do not access addresses above the top of its 16-Kbyte memory space. If access goes beyond the 16-Kbyte space, the values read are undefined.

Procedure for switching to the user boot MAT Procedure for switching to the user MAT Procedure for switching to the user boot MAT (1) Mask interrupts (2) Write H'AA to FMATS. (3) Execute four NOP instructions before accessing the user boot MAT. Procedure for switching to the user MAT (1) Mask interrupts (2) Write a value other than H'AA to FMATS. (3) Execute four NOP instructions before accessing the user MAT.

Figure 25.19 Switching between the User MAT and User Boot MAT
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Section 25 Flash Memory
25.7
Programmer Mode
Along with its on-board programming mode, this LSI also has a programmer mode as a further mode for the programming and erasing of programs and data. In the programmer mode, a generalpurpose PROM programmer, which supports microcomputers with 512-Kbyte flash memory as a 1 device type* , can freely be used to write programs to the on-chip ROM. Program/erase is possible 2 on the user MAT and user boot MAT* . A status-polling system is adopted for operation in automatic program, automatic erase, and status-read modes. In the status-read mode, details of the system's internal signals are output after execution of automatic programming or automatic erasure. In programmer mode, provide a 6MHz input-clock signal. Notes: 1. For the PROM programmer and the version of its program, see the instruction manuals for socket adapter. 2. In this LSI, set the programming voltage of the PROM programmer to 3.3 V.
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Section 25 Flash Memory
25.8
Serial Communication Interface Specification for Boot Mode
Initiating boot mode enables the boot program to communicate with the host by using the internal SCI. The serial communication interface specification is shown below. (1) Status
The boot program has three states. 1. Bit-Rate-Adjustment State In this state, the boot program adjusts the bit rate to communicate with the host. Initiating boot mode enables starting of the boot program and entry to the bit-rate-adjustment state. The program receives the command from the host to adjust the bit rate. After adjusting the bit rate, the program enters the inquiry/selection state. 2. Inquiry/Selection State In this state, the boot program responds to inquiry commands from the host. The device name, clock mode, and bit rate are selected. After selection of these settings, the program is made to enter the programming/erasing state by the command for a transition to the programming/erasing state. The program transfers the libraries required for erasure to the onchip RAM and erases the user MATs and user boot MATs before the transition. 3. Programming/erasing state Programming and erasure by the boot program take place in this state. The boot program is made to transfer the programming/erasing programs to the RAM by commands from the host. Sum checks and blank checks are executed by sending these commands from the host. These boot program states are shown in figure 25.20.
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Section 25 Flash Memory
Reset
Bit-rate-adjustment state
Inquiry/response wait Transition to programming/erasing
Response Inquiry Operations for inquiry and selection Operations for response
Operations for erasing user MATs and user boot MATs
Programming/erasing wait Programming Operations for programming Erasing Operations for erasing Checking
Operations for checking
Figure 25.20 Boot Program States
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Section 25 Flash Memory
(2)
Bit-Rate-Adjustment State
The bit rate is calculated by measuring the period of transfer of a low-level byte (H'00) from the host. The bit rate can be changed by the command for a new bit rate selection. After the bit rate has been adjusted, the boot program enters the inquiry and selection state. The bit-rate-adjustment sequence is shown in figure 25.21.
Host H'00 (30 times maximum)
Boot Program
Measuring the 1-bit length
H'00 (Completion of adjustment) H'55 H'E6 (Boot response) (H'FF (error))
Figure 25.21 Bit-Rate-Adjustment Sequence (3) Communications Protocol
After adjustment of the bit rate, the protocol for communications between the host and the boot program is as shown below. 1. 1-byte commands and 1-byte responses These commands and responses are comprised of a single byte. These are consists of the inquiries and the ACK for successful completion. 2. n-byte commands or n-byte responses These commands and responses are comprised of n bytes of data. These are selections and responses to inquiries. The amount of programming data is not included under this heading because it is determined in another command. 3. Error response The error response is a response to inquiries. It consists of an error response and an error code and comes two bytes.
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Section 25 Flash Memory
4. Programming of 128 bytes The size is not specified in commands. The size of n is indicated in response to the programming unit inquiry. 5. Memory read response This response consists of 4 bytes of data.
1-byte command or 1-byte response n-byte Command or n-byte response
Command or response
Data Size Command or response Checksum
Error response Error code Error response
128-byte programming
Address Command
Data (n bytes) Checksum
Memory read response
Size Response
Data Checksum
Figure 25.22 Communication Protocol Format * Command (1 byte): Commands including inquiries, selection, programming, erasing, and checking * Response (1 byte): Response to an inquiry * Size (1 byte): The amount of data for transmission excluding the command, amount of data, and checksum * Checksum (1 byte): The checksum is calculated so that the total of all values from the command byte to the SUM byte becomes H00. * Data (n bytes): Detailed data of a command or response * Error response (1 byte): Error response to a command * Error code (1 byte): Type of the error * Address (4 bytes): Address for programming * Data (n bytes): Data to be programmed (the size is indicated in the response to the programming unit inquiry.)
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Section 25 Flash Memory
* Size (4 bytes): 4-byte response to a memory read (4) Inquiry and Selection States
The boot program returns information from the flash memory in response to the host's inquiry commands and sets the device code, clock mode, and bit rate in response to the host's selection command. Inquiry and selection commands are listed below. Table 25.12 Inquiry and Selection Commands
Command H'20 H'10 H'21 H'11 H'22 Command Name Supported Device Inquiry Device Selection Clock Mode Inquiry Clock Mode Selection Multiplication Ratio Inquiry Description Inquiry regarding device codes Selection of device code Inquiry regarding numbers of clock modes and values of each mode Indication of the selected clock mode Inquiry regarding the number of frequencymultiplied clock types, the number of multiplication ratios, and the values of each multiple
H'23 H'24
Operating Clock Frequency Inquiry Inquiry regarding the maximum and minimum values of the main clock and peripheral clocks User Boot MAT Information Inquiry Inquiry regarding the number of user boot MATs and the start and last addresses of each MAT User MAT Information Inquiry Block for Erasing Information Inquiry Programming Unit Inquiry New Bit Rate Selection Inquiry regarding the a number of user MATs and the start and last addresses of each MAT Inquiry regarding the number of blocks and the start and last addresses of each block Inquiry regarding the unit of programming data Selection of new bit rate
H'25 H'26 H'27 H'3F H'40 H'4F
Transition to Programming/Erasing Erasing of user MAT and user boot MAT, and State entry to programming/erasing state Boot Program Status Inquiry Inquiry into the operated status of the boot program
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Section 25 Flash Memory
The selection commands, which are device selection (H'10), clock mode selection (H'11), and new bit rate selection (H'3F), should be sent from the host in that order. These commands will certainly be needed. When two or more selection commands are sent at once, the last command will be valid. All of these commands, except for the boot program status inquiry command (H'4F), will be valid until the boot program receives the programming/erasing transition (H'40). The host can choose the needed commands out of the commands and inquiries listed above. The boot program status inquiry command (H'4F) is valid after the boot program has received the programming/erasing transition command (H'40). (a) Supported Device Inquiry
The boot program will return the device codes of supported devices and the product code in response to the supported device inquiry.
Command H'20
* Command, H'20, (1 byte): Inquiry regarding supported devices
Response H'30 Number of characters *** SUM Size Number of devices Product name
Device code
* Response, H'30, (1 byte): Response to the supported device inquiry * Size (1 byte): Number of bytes to be transmitted, excluding the command, size, and checksum, that is, the amount of data contributes by the number of devices, characters, device codes and product names * Number of devices (1 byte): The number of device types supported by the boot program * Number of characters (1 byte): The number of characters in the device codes and boot program's name * Device code (4 bytes): ASCII code of the supporting product * Product name (n bytes): Type name of the boot program in ASCII-coded characters * SUM (1 byte): Checksum The checksum is calculated so that the total number of all values from the command byte to the SUM byte becomes H'00.
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Section 25 Flash Memory
(b)
Device Selection
The boot program will set the supported device to the specified device code. The program will return the selected device code in response to the inquiry after this setting has been made.
Command H'10 Size Device code SUM
* Command, H'10, (1 byte): Device selection * Size (1 byte): Amount of device-code data This is fixed at 4 * Device code (4 bytes): Device code (ASCII code) returned in response to the supported device inquiry * SUM (1 byte): Checksum
Response H'06
* Response, H'06, (1 byte): Response to the device selection command ACK will be returned when the device code matches.
Error response H'90 ERROR
* Error response, H'90, (1 byte): Error response to the device selection command ERROR : (1 byte): Error code H'11: Sum check error H'21: Device code error, that is, the device code does not match (c) Clock Mode Inquiry
The boot program will return the supported clock modes in response to the clock mode inquiry.
Command H'21
* Command, H'21, (1 byte): Inquiry regarding clock mode
Response H'31 Size Number of modes Mode *** SUM
* Response, H'31, (1 byte): Response to the clock-mode inquiry * Size (1 byte): Amount of data that represents the number of modes and modes * Number of clock modes (1 byte): The number of supported clock modes H'00 indicates no clock mode or the device allows to read the clock mode. * Mode (1 byte): Values of the supported clock modes (i.e. H'01 means clock mode 1.) * SUM (1 byte): Checksum
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Section 25 Flash Memory
(d)
Clock Mode Selection
The boot program will set the specified clock mode. The program will return the selected clockmode information after this setting has been made. The clock-mode selection command should be sent after the device-selection commands.
Command H'11 Size Mode SUM
* Command, H'11, (1 byte): Selection of clock mode * Size (1 byte): Amount of data that represents the modes * Mode (1 byte): A clock mode returned in reply to the supported clock mode inquiry. * SUM (1 byte): Checksum
Response H'06
* Response, H'06, (1 byte): Response to the clock mode selection command ACK will be returned when the clock mode matches.
Error Response H'91 ERROR
* Error response, H'91, (1 byte) * ERROR
: Error response to the clock mode selection command
: (1 byte): Error code H'11: Checksum error H'22: Clock mode error, that is, the clock mode does not match.
Even if the clock mode numbers are H'00 and H'01 by a clock mode inquiry, the clock mode must be selected using these respective values.
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Section 25 Flash Memory
(e)
Multiplication Ratio Inquiry
The boot program will return the supported multiplication and division ratios.
Command H'22
* Command, H'22, (1 byte): Inquiry regarding multiplication ratio
Response H'32 Number of multiplication ratios *** SUM Size Multiplication ratio Number of types ***
* Response, H'32, (1 byte): Response to the multiplication ratio inquiry * Size (1 byte): The amount of data that represents the number of clock sources and multiplication ratios and the multiplication ratios * Number of types (1 byte): The number of supported multiplied clock types (e.g. when there are two multiplied clock types, which are the main and peripheral clocks, the number of types will be H'02.) * Number of multiplication ratios (1 byte): The number of multiplication ratios for each type (e.g. the number of multiplication ratios to which the main clock can be set and the peripheral clock can be set.) * Multiplication ratio (1 byte) Multiplication ratio: The value of the multiplication ratio (e.g. when the clock-frequency multiplier is four, the value of multiplication ratio will be H'04.) Division ratio: The inverse of the division ratio, i.e. a negative number (e.g. when the clock is divided by two, the value of division ratio will be H'FE. H'FE = D'-2) The number of multiplication ratios returned is the same as the number of multiplication ratios and as many groups of data are returned as there are types. * SUM (1 byte): Checksum
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Section 25 Flash Memory
(f)
Operating Clock Frequency Inquiry
The boot program will return the number of operating clock frequencies, and the maximum and minimum values.
Command H'23
* Command, H'23, (1 byte): Inquiry regarding operating clock frequencies
Response H'33 Size Number of operating clock frequencies
Minimum value of operating Maximum value of operating clock clock frequency frequency *** SUM
* Response, H'33, (1 byte): Response to operating clock frequency inquiry * Size (1 byte): The number of bytes that represents the minimum values, maximum values, and the number of frequencies. * Number of operating clock frequencies (1 byte): The number of supported operating clock frequency types (e.g. when there are two operating clock frequency types, which are the main and peripheral clocks, the number of types will be H'02.) * Minimum value of operating clock frequency (2 bytes): The minimum value of the multiplied or divided clock frequency. The minimum and maximum values represent the values in MHz, valid to the hundredths place of MHz, and multiplied by 100. (e.g. when the value is 20.00 MHz, it will be 2000, which is H'07D0.) * Maximum value (2 bytes): Maximum value among the multiplied or divided clock frequencies. There are as many pairs of minimum and maximum values as there are operating clock frequencies. * SUM (1 byte): Checksum
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Section 25 Flash Memory
(g)
User Boot MAT Information Inquiry
The boot program will return the number of user boot MATs and their addresses.
Command H'24
*
Command, H'24, (1 byte): Inquiry regarding user boot MAT information
H'34 Size Number of areas Area-last address
Response
Area-start address *** SUM
* Response, H'34, (1 byte): Response to user boot MAT information inquiry * Size (1 byte): The number of bytes that represents the number of areas, area-start addresses, and area-last address * Number of Areas (1 byte): The number of consecutive user boot MAT areas When user boot MAT areas are consecutive, the number of areas returned is H'01. * Area-start address (4 byte): Start address of the area * Area-last address (4 byte): Last address of the area There are as many groups of data representing the start and last addresses as there are areas. * SUM (1 byte): Checksum (h) User MAT Information Inquiry
The boot program will return the number of user MATs and their addresses.
Command H'25
*
Command, H'25, (1 byte): Inquiry regarding user MAT information
H'35 Size Number of areas Last address area
Response
Start address area *** SUM
* Response, H'35, (1 byte): Response to the user MAT information inquiry * Size (1 byte): The number of bytes that represents the number of areas, area-start address and area-last address * Number of areas (1 byte): The number of consecutive user MAT areas When the user MAT areas are consecutive, the number of areas is H'01. * Area-start address (4 bytes): Start address of the area
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* Area-last address (4 bytes): Last address of the area There are as many groups of data representing the start and last addresses as there are areas. * SUM (1 byte): Checksum (i) Erased Block Information Inquiry
The boot program will return the number of erased blocks and their addresses.
Command H'26
* Command, H'26, (1 byte): Inquiry regarding erased block information
Response H'36 Size Number of blocks Block last address
Block start address *** SUM
* Response, H'36, (1 byte): Response to the number of erased blocks and addresses * Size (three bytes): The number of bytes that represents the number of blocks, block-start addresses, and block-last addresses. * Number of blocks (1 byte): The number of erased blocks * Block start address (4 bytes): Start address of a block * Block last Address (4 bytes): Last address of a block There are as many groups of data representing the start and last addresses as there are areas. * SUM (1 byte): Checksum (j) Programming Unit Inquiry
The boot program will return the programming unit used to program data.
Command H'27
*
Command, H'27, (1 byte): Inquiry regarding programming unit
H'37 Size Programming unit SUM
Response
* Response, H'37, (1 byte): Response to programming unit inquiry * Size (1 byte): The number of bytes that indicate the programming unit, which is fixed to 2 * Programming unit (2 bytes): A unit for programming This is the unit for reception of programming. * SUM (1 byte): Checksum
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Section 25 Flash Memory
(k)
New Bit-Rate Selection
The boot program will set a new bit rate and return the new bit rate. This selection should be sent after sending the clock mode selection command.
Command H'3F Number of multiplication ratios SUM Size Multiplication ratio 1 Bit rate Multiplication ratio 2 Input frequency
* Command, H'3F, (1 byte): Selection of new bit rate * Size (1 byte): The number of bytes that represents the bit rate, input frequency, number of multiplication ratios, and multiplication ratio * Bit rate (2 bytes): New bit rate One hundredth of the value (e.g. when the value is 19200 bps, it will be 192, which is H00C0.) * Input frequency (2 bytes): Frequency of the clock input to the boot program This is valid to the hundredths place and represents the value in MHz multiplied by 100. (E.g. when the value is 20.00 MHz, it will be 2000, which is H'07D0.) * Number of multiplication ratios (1 byte): The number of multiplication ratios to which the device can be set. * Multiplication ratio 1 (1 byte) : The value of multiplication or division ratios for the main operating frequency Multiplication ratio (1 byte): The value of the multiplication ratio (e.g. when the clock frequency is multiplied by four, the multiplication ratio will be H'04.) Division ratio: The inverse of the division ratio, as a negative number (e.g. when the clock frequency is divided by two, the value of division ratio will be H'FE. H'FE = D'-2) * Multiplication ratio 2 (1 byte): The value of multiplication or division ratios for the peripheral frequency Multiplication ratio (1 byte): The value of the multiplication ratio (e.g. when the clock frequency is multiplied by four, the multiplication ratio will be H'04.) (Division ratio: The inverse of the division ratio, as a negative number (E.g. when the clock is divided by two, the value of division ratio will be H'FE. H'FE = D'-2) * SUM (1 byte): Checksum
Response H'06
* Response, H'06, (1 byte): Response to selection of a new bit rate When it is possible to set the bit rate, the response will be ACK.
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Section 25 Flash Memory
Error Response
H'BF
ERROR
* Error response, H'BF, (1 byte): Error response to selection of new bit rate * ERROR: (1 byte): Error code H'11: H'24: H'25: H'26: H'27: Sum checking error Bit-rate selection error The rate is not available. Error in input frequency This input frequency is not within the specified range. Multiplication-ratio error The ratio does not match an available ratio. Operating frequency error The frequency is not within the specified range.
(5)
Received Data Check
The methods for checking of received data are listed below. 1. Input frequency The received value of the input frequency is checked to ensure that it is within the range of minimum to maximum frequencies which matches the clock modes of the specified device. When the value is out of this range, an input-frequency error is generated. 2. Multiplication ratio The received value of the multiplication ratio or division ratio is checked to ensure that it matches the clock modes of the specified device. When the value is out of this range, an multiplicationratio error is generated. 3. Operating frequency Operating frequency is calculated from the received value of the input frequency and the multiplication or division ratio. The input frequency is input to the LSI and the LSI is operated at the operating frequency. The expression is given below. Operating frequency = Input frequency x Multiplication ratio, or Operating frequency = Input frequency / Division ratio The calculated operating frequency should be checked to ensure that it is within the range of minimum to maximum frequencies which are available with the clock modes of the specified device. When it is out of this range, an operating frequency error is generated.
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Section 25 Flash Memory
4. Bit rate To facilitate error checking, the value (n) of clock select (CKS) in the serial mode register (SMR), and the value (N) in the bit rate register (BRR), which are found from the peripheral operating clock frequency () and bit rate (B), are used to calculate the error rate to ensure that it is less than 4%. If the error is more than 4%, a bit rate error is generated. The error is calculated using the following expression:
Error (%) = {[ x 106 (N + 1) x B x 64 x 2(2xn - 1) ] - 1} x 100
When the new bit rate is selectable, the rate will be set in the register after sending ACK in response. The host will send an ACK with the new bit rate for confirmation and the boot program will response with that rate.
Confirmation H'06
* Confirmation, H'06, (1 byte): Confirmation of a new bit rate
Response H'06
* Response, H'06, (1 byte): Response to confirmation of a new bit rate The sequence of new bit-rate selection is shown in figure 25.23.
Host Setting a new bit rate Waiting for one-bit period at the specified bit rate Setting a new bit rate H'06 (ACK) with the new bit rate H'06 (ACK) with the new bit rate H'06 (ACK)
Boot program
Setting a new bit rate
Figure 25.23 New Bit-Rate Selection Sequence
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Section 25 Flash Memory
(6)
Transition to Programming/Erasing State
The boot program will transfer the erasing program, and erase the user MATs and user boot MATs in that order. On completion of this erasure, ACK will be returned and will enter the programming/erasing state. The host should select the device code, clock mode, and new bit rate with device selection, clockmode selection, and new bit-rate selection commands, and then send the command for the transition to programming/erasing state. These procedures should be carried out before sending of the programming selection command or program data.
Command H'40
* Command, H'40, (1 byte): Transition to programming/erasing state
Response H'06
* Response, H'06, (1 byte): Response to transition to programming/erasing state The boot program will send ACK when the user MAT and user boot MAT have been erased by the transferred erasing program.
Error Response H'C0 H'51
* Error response, H'C0, (1 byte): Error response for user boot MAT blank check * Error code, H'51, (1 byte): Erasing error An error occurred and erasure was not completed. Command Error
(7)
A command error will occur when a command is undefined, the order of commands is incorrect, or a command is unacceptable. Issuing a clock-mode selection command before a device selection or an inquiry command after the transition to programming/erasing state command, are examples.
Error Response H'80 H'xx
* Error response, H'80, (1 byte): Command error * Command, H'xx, (1 byte): Received command
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Section 25 Flash Memory
(8)
Command Order
The order for commands in the inquiry selection state is shown below. 1. A supported device inquiry (H'20) should be made to inquire about the supported devices. 2. The device should be selected from among those described by the returned information and set with a device-selection (H'10) command. 3. A clock-mode inquiry (H'21) should be made to inquire about the supported clock modes. 4. The clock mode should be selected from among those described by the returned information and set. 5. After selection of the device and clock mode, inquiries for other required information should be made, such as the multiplication-ratio inquiry (H'22) or operating frequency inquiry (H'23), which are needed for a new bit-rate selection. 6. A new bit rate should be selected with the new bit-rate selection (H'3F) command, according to the returned information on multiplication ratios and operating frequencies. 7. After selection of the device and clock mode, the information of the user boot MAT and user MAT should be made to inquire about the user boot MATs information inquiry (H'24), user MATs information inquiry (H'25), erased block information inquiry (H'26), and programming unit inquiry (H'27). 8. After making inquiries and selecting a new bit rate, issue the transition to programming/erasing state command (H'40). The boot program will then enter the programming/erasing state.
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Section 25 Flash Memory
(9)
Programming/Erasing State
A programming selection command makes the boot program select the programming method, a 128-byte programming command makes it program the memory with data, and an erasing selection command and block erasing command make it erase the block. The programming/erasing commands are listed below. Table 25.13 Programming/Erasing Command
Command H'42 H'43 H'50 H'48 H'58 H'52 H'4A H'4B H'4C H'4D H'4F Command Name Description
User boot MAT programming selection Transfers the user boot MAT programming program User MAT programming selection 128-byte programming Erasing selection Block erasing Memory read User boot MAT sum check User MAT sum check User boot MAT blank check User MAT blank check Boot program status inquiry Transfers the user MAT programming program Programs 128 bytes of data Transfers the erasing program Erases a block of data Reads the contents of memory Checks the checksum of the user boot MAT Checks the checksum of the user MAT Checks whether the contents of the user boot MAT are blank Checks whether the contents of the user MAT are blank Inquires into the boot program's status
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Section 25 Flash Memory
*
Programming Programming is executed by a programming-selection command and a 128-byte programming command. Firstly, the host should send the programming-selection command and select the programming method and programming MATs. There are two programming selection commands, and selection is according to the area and method for programming. 1. User boot MAT programming selection 2. User MAT programming selection After issuing the programming selection command, the host should send the 128-byte programming command. The 128-byte programming command that follows the selection command represents the data programmed according to the method specified by the selection command. When more than 128-byte data is programmed, 128-byte commands should repeatedly be executed. Sending a 128-byte programming command with H'FFFFFFFF as the address will stop the programming. On completion of programming, the boot program will wait for selection of programming or erasing. Where the sequence of programming operations that is executed includes programming with another method or of another MAT, the procedure must be repeated from the programming selection command. The sequence for programming-selection and 128-byte programming commands is shown in figure 25.24.
Host Programming selection (H'42, H'43) Boot program
Transfer of the programming program
ACK 128-byte programming (address, data) Repeat ACK 128-byte programming (H'FFFFFFFF) ACK Programming
Figure 25.24 Programming Sequence
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Section 25 Flash Memory
(a)
User boot MAT programming selection
The boot program will transfer a programming program. The data is programmed to the user boot MATs by the transferred programming program.
Command H'42
* Command, H'42, (1 byte): User boot MAT programming selection
Response H'06
* Response, H'06, (1 byte): Response to user boot MAT programming selection When the programming program has been transferred, the boot program will return ACK.
Error Response H'C2 ERROR
* Error response : H'C2 (1 byte): Error response to user boot MAT programming selection * ERROR : (1 byte): Error code H'54: Selection processing error (transfer error occurs and processing is not completed) * User MAT programming selection The boot program will transfer a program for programming. The data is programmed to the user MATs by the transferred program for programming.
Command H'43
* Command, H'43, (1 byte): User MAT programming selection
Response H'06
* Response, H'06, (1 byte): Response to user MAT programming selection When the programming program has been transferred, the boot program will return ACK.
Error Response H'C3 ERROR
* Error response : H'C3 (1 byte): Error response to user MAT programming selection * ERROR : (1 byte): Error code H'54: Selection processing error (transfer error occurs and processing is not completed) (b) 128-byte programming
The boot program will use the programming program transferred by the programming selection to program the user boot MATs or user MATs in response to 128-byte programming.
Command H'50 Data *** SUM
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Address ***
Section 25 Flash Memory
* Command, H'50, (1 byte): 128-byte programming * Programming Address (4 bytes): Start address for programming Multiple of the size specified in response to the programming unit inquiry (i.e. H'00, H'01, H'00, H'00 : H'00010000) * Programming Data (128 bytes): Data to be programmed The size is specified in the response to the programming unit inquiry. * SUM (1 byte): Checksum
Response H'06
* Response, H'06, (1 byte): Response to 128-byte programming On completion of programming, the boot program will return ACK.
Error Response H'D0 ERROR
* Error response, H'D0, (1 byte): Error response for 128-byte programming * ERROR: (1 byte): Error code H'11: H'2A: Checksum Error Address Error
H'53: Programming error A programming error has occurred and programming cannot be continued. The specified address should match the unit for programming of data. For example, when the programming is in 128-byte units, the lower 8 bits of the address should be H'00 or H'80. When there are less than 128 bytes of data to be programmed, the host should fill the rest with H'FF. Sending the 128-byte programming command with the address of H'FFFFFFFF will stop the programming operation. The boot program will interpret this as the end of the programming and wait for selection of programming or erasing.
Command H'50 Address SUM
* Command, H'50, (1 byte): 128-byte programming * Programming Address (4 bytes): End code is H'FF, H'FF, H'FF, H'FF. * SUM (1 byte): Checksum
Response H'06
* Response, H'06, (1 byte): Response to 128-byte programming On completion of programming, the boot program will return ACK.
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Section 25 Flash Memory
Error Response
H'D0
ERROR
* Error Response, H'D0, (1 byte): Error response for 128-byte programming * ERROR: (1 byte): Error code H'11: Checksum error H'2A: Address error H'53: Programming error An error has occurred in programming and programming cannot be continued. (10) Erasure Erasure is performed with the erasure selection and block erasure command. Firstly, erasure is selected by the erasure selection command and the boot program then erases the specified block. The command should be repeatedly executed if two or more blocks are to be erased. Sending a block-erasure command from the host with the block number H'FF will stop the erasure operating. On completion of erasing, the boot program will wait for selection of programming or erasing. The sequences of issuing the erasure selection command and block-erasure command are shown in figure 25.25.
Host Preparation for erasure (H'48) Transfer of erasure program ACK Erasure (Erasure block number) ACK Erasure (H'FF) ACK Boot program
Repeat
Erasure
Figure 25.25 Erasure Sequence
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Section 25 Flash Memory
(a)
Erasure Selection
The boot program will transfer the erasure program. User MAT data is erased by the transferred erasure program.
Command H'48
*
Command, H'48, (1 byte): Erasure selection
H'06
Response
*
Response, H'06, (1 byte): Response for erasure selection After the erasure program has been transferred, the boot program will return ACK.
H'C8 ERROR
Error Response
* *
Error Response, H'C8, (1 byte): Error response to erasure selection ERROR: (1 byte): Error code H'54: Selection processing error (transfer error occurs and processing is not completed)
(b)
Block Erasure
The boot program will erase the contents of the specified block.
Command H'58 Size Block number SUM
* * * *
Command, H'58, (1 byte): Erasure Size (1 byte): The number of bytes that represents the erasure block number This is fixed to 1. Block number (1 byte): Number of the block to be erased SUM (1 byte): Checksum
H'06
Response
*
Response, H'06, (1 byte): Response to Erasure After erasure has been completed, the boot program will return ACK.
H'D8 ERROR
Error Response
* *
Error Response, H'D8, (1 byte): Response to Erasure ERROR (1 byte): Error code H'11: H'29: H'51: Sum check error Block number error Block number is incorrect. Erasure error An error has occurred during erasure.
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Section 25 Flash Memory
On receiving block number H'FF, the boot program will stop erasure and wait for a selection command.
Command H'58 Size Block number SUM
* Command, H'58, (1 byte): Erasure * Size, (1 byte): The number of bytes that represents the block number This is fixed to 1. * Block number (1 byte): H'FF Stop code for erasure * SUM (1 byte): Checksum
Response H'06
* Response, H'06, (1 byte): Response to end of erasure (ACK) When erasure is to be performed after the block number H'FF has been sent, the procedure should be executed from the erasure selection command. (11) Memory read The boot program will return the data in the specified address.
Command H'52 Size Area Read address SUM
Read size
* Command: H'52 (1 byte): Memory read * Size (1 byte): Amount of data that represents the area, read address, and read size (fixed at 9) * Area (1 byte) H'00: User boot MAT H'01: User MAT An address error occurs when the area setting is incorrect. * Read address (4 bytes): Start address to be read from * Read size (4 bytes): Size of data to be read * SUM (1 byte): Checksum
Response H'52 Data SUM Read size ***
* Response: H'52 (1 byte): Response to memory read * Read size (4 bytes): Size of data to be read * Data (n bytes): Data for the read size from the read address * SUM (1 byte): Checksum
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Section 25 Flash Memory
Error Response
H'D2
ERROR
* Error response: H'D2 (1 byte): Error response to memory read * ERROR: (1 byte): Error code H'11: Sum check error H'2A: Address error The read address is not in the MAT. H'2B: Size error The read size exceeds the MAT. (12) User Boot MAT Sum Check The boot program will return the byte-by-byte total of the contents of the bytes of the user boot MAT, as a 4-byte value.
Command H'4A
* Command, H'4A, (1 byte): Sum check for user-boot MAT
Response H'5A Size Checksum of user boot program SUM
* Response, H'5A, (1 byte): Response to the sum check of user-boot MAT * Size (1 byte): The number of bytes that represents the checksum This is fixed to 4. * Checksum of user boot program (4 bytes): Checksum of user boot MATs The total of the data is obtained in byte units. * SUM (1 byte): Sum check for data being transmitted (13) User MAT Sum Check The boot program will return the byte-by-byte total of the contents of the bytes of the user MAT.
Command H'4B
* Command, H'4B, (1 byte): Sum check for user MAT
Response H'5B Size Checksum of user program SUM
* Response, H'5B, (1 byte): Response to the sum check of the user MAT * Size (1 byte): The number of bytes that represents the checksum This is fixed to 4. * Checksum of user boot program (4 bytes): Checksum of user MATs The total of the data is obtained in byte units. * SUM (1 byte): Sum check for data being transmitted
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Section 25 Flash Memory
(14) User Boot MAT Blank Check The boot program will check whether or not all user boot MATs are blank and return the result.
Command H'4C
* Command, H'4C, (1 byte): Blank check for user boot MAT
Response H'06
* Response, H'06, (1 byte): Response to the blank check of user boot MAT If all user MATs are blank (H'FF), the boot program will return ACK.
Error Response H'CC H'52
* Error Response, H'CC, (1 byte): Response to blank check for user boot MAT * Error Code, H'52, (1 byte): Erasure has not been completed. (15) User MAT Blank Check The boot program will check whether or not all user MATs are blank and return the result.
Command H'4D
* Command, H'4D, (1 byte): Blank check for user MATs
Response H'06
* Response, H'06, (1 byte): Response to the blank check for user boot MATs If the contents of all user MATs are blank (H'FF), the boot program will return ACK.
Error Response H'CD H'52
* Error Response, H'CD, (1 byte): Error response to the blank check of user MATs. * Error code, H'52, (1 byte): Erasure has not been completed.
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Section 25 Flash Memory
(16) Boot Program State Inquiry The boot program will return indications of its present state and error condition. This inquiry can be made in the inquiry/selection state or the programming/erasing state.
Command H'4F
* Command, H'4F, (1 byte):
Response H'5F Size
Inquiry regarding boot program's state
ERROR SUM
Status
* Response, H'5F, (1 byte): Response to boot program state inquiry * Size (1 byte): The number of bytes. This is fixed to 2. * Status (1 byte): State of the boot program * ERROR (1 byte): Error status ERROR = 0 indicates normal operation. ERROR = 1 indicates error has occurred. * SUM (1 byte): Sum check Table 25.14 Status Code
Code H'11 H'12 H'13 H'1F H'31 H'3F H'4F H'5F Description Device Selection Wait Clock Mode Selection Wait Bit Rate Selection Wait Programming/Erasing State Transition Wait (Bit rate selection is completed) Programming State for Erasure Programming/Erasing Selection Wait (Erasure is completed) Programming Data Receive Wait (Programming is completed) Erasure Block Specification Wait (Erasure is completed)
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Section 25 Flash Memory
Table 25.15 Error Code
Code H'00 H'11 H'12 H'21 H'22 H'24 H'25 H'26 H'27 H'29 H'2A H'2B H'51 H'52 H'53 H'54 H'80 H'FF Description No Error Sum Check Error Program Size Error Device Code Mismatch Error Clock Mode Mismatch Error Bit Rate Selection Error Input Frequency Error Multiplication Ratio Error Operating Frequency Error Block Number Error Address Error Data Length Error Erasure Error Erasure Incomplete Error Programming Error Selection Processing Error Command Error Bit-Rate-Adjustment Confirmation Error
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Section 25 Flash Memory
25.9
Usage Notes
1. The initial state of the product at its shipment is in the erased state. For the product whose revision of erasing is undefined, we recommend to execute automatic erasure for checking the initial state (erased state) and compensating. 2. For the PROM programmer suitable for programmer mode in this LSI and its program version, refer to the instruction manual of the socket adapter. 3. If the socket, socket adapter, or product index does not match the specifications, too much current flows and the product may be damaged. 4. If a voltage higher than the rated voltage is applied, the product may be fatally damaged. Use a PROM programmer that supports the 512-Kbyte flash memory on-chip MCU device at 3.3 V. Do not set the programmer to HN28F101 or the programming voltage to 5.0 V. Use only the specified socket adapter. If other adapters are used, the product may be damaged. 5. Do not remove the chip from the PROM programmer nor input a reset signal during programming/erasing. As a high voltage is applied to the flash memory during programming/erasing, doing so may damage or destroy flash memory permanently. If reset is executed accidentally, reset must be released after the reset input period of 100 s which is longer than normal. 6. The flash memory is not accessible until FKEY is cleared after programming/erasing completes. If this LSI is restarted by a reset immediately after programming/erasing has finished, secure the reset period (period of RES = 0) of more than 100 s. Though transition to the reset state or hardware standby state during programming/erasing is prohibited, if reset is executed accidentally, reset must be released after the reset input period of 100 s which is longer than normal. 7. At powering on or off the Vcc power supply, fix the RES pin to low and set the flash memory to hardware protection state. This power on/off timing must also be satisfied at a power-off and power-on caused by a power failure and other factors. 8. Program the area with 128-byte programming-unit blocks in on-board programming or programmer mode only once. Perform programming in the state where the programming-unit block is fully erased. 9. When the chip is to be reprogrammed with the programmer after execution of programming or erasure in on-board programming mode, it is recommend that automatic programming is performed after execution of automatic erasure. 10. To write data or programs to the flash memory, data or programs must be allocated to addresses higher than that of the external interrupt vector table (H'000040) and H'FF must be written to the areas that are reserved for the system in the exception handling vector table.
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Section 25 Flash Memory
11. If data other than H'FFFFFFFF is written to the key code area (H'00003C to H'00003F) of flash memory, only H'00 can be read in programmer mode. (In this case, data is read as H'00. Rewrite is possible after erasing the data.) For reading in programmer mode, make sure to write H'FFFFFFFF to the entire key code area. If data other than H'FF is to be written to the key code area in programmer mode, a verification error will occur unless a software countermeasure is taken for the PROM programmer and the version of its program. 12. The programming program that includes the initialization routine and the erasing program that includes the initialization routine are each 3 Kbytes or less. Accordingly, when the CPU clock frequency is 34 MHz, the download for each program takes approximately 180 s at the maximum. 13. While an instruction in on-chip RAM is being executed, the DTC can write to the SCO bit in FCCS that is used for a download request or FMATS that is used for MAT switching. Make sure that these registers are not accidentally written to, otherwise an on-chip program may be downloaded and damage RAM or a MAT switchover may occur and the CPU get out of control. Do not use DTC to program flash related registers. 14. A programming/erasing program for flash memory used in the conventional H8S F-ZTAT microcomputer which does not support download of the on-chip program by a SCO transfer request cannot run in this LSI. Be sure to download the on-chip program to execute programming/erasing of flash memory in this LSI. 15. Unlike the conventional H8S F-ZTAT microcomputer, no countermeasures are available for a runaway by WDT during programming/erasing. Prepare countermeasures (e.g. use of the periodic timer interrupts) for WDT with taking the programming/erasing time into consideration as required.
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Section 25 Flash Memory
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Section 26 Boundary Scan (JTAG)
Section 26 Boundary Scan (JTAG)
The JTAG (Joint Test Action Group) is standardized as an international standard, IEEE Standard 1149.1, and is open to the public as IEEE Standard Test Access Port and Boundary-Scan Architecture. Although the name of the function is boundary scan and the name of the group who worked on standardization is the JTAG, the JTAG is commonly used as the name of a boundary scan architecture and a serial interface to access the devices having the architecture. This LSI has a boundary scan function (JTAG). Using this function along with other LSIs facilitates testing a printed-circuit board.
26.1
Features
* Five test pins (ETCK, ETDI, ETDO, ETMS, and ETRST) * TAP controller * Six instructions BYPASS mode EXTEST mode SAMPLE/PRELOAD mode CLAMP mode HIGHZ mode IDCODE mode (These instructions are test modes corresponding to IEEE 1149.1.)
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Section 26 Boundary Scan (JTAG)
ETCK
ETMS TAP controller ETRST Decoder
ETDI
SDIR
Shift register SDBPR SDBSR
SDIDR
ETDO Mux
[Legend] SDIR: SDBPR: SDBSR: SDIDR:
Instruction register Bypass register Boundary scan register ID code register
Figure 26.1 JTAG Block Diagram
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Section 26 Boundary Scan (JTAG)
26.2
Input/Output Pins
Table 26.1 shows the JTAG pin configuration. Table 26.1 Pin Configuration
Pin Name Test clock Abbreviation ETCK I/O Input Function Test clock input Provides an independent clock supply to the JTAG. As the clock input to the ETCK pin is supplied directly to the JTAG, a clock waveform with a duty cycle close to 50% should be input. For details, see section 31, Electrical Characteristics. Test mode select ETMS Input Test mode select input Sampled on the rise of the ETCK pin. The ETMS pin controls the internal state of the TAP controller. Test data input ETDI Input Serial data input Performs serial input of instructions and data for JTAG registers. ETDI is sampled on the rise of the ETCK pin. Test data output ETDO Output Serial data output Performs serial output of instructions and data from JTAG registers. Transfer is performed in synchronization with the ETCK pin. If there is no output, the ETDO pin goes to the highimpedance state. Test reset ETRST Input Test reset input signal Initializes the JTAG asynchronously.
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Section 26 Boundary Scan (JTAG)
26.3
Register Descriptions
The JTAG has the following registers. * Instruction register (SDIR) * Bypass register (SDBPR) * Boundary scan register (SDBSR) * ID code register (SDIDR) Instructions can be input to the instruction register (SDIR) by serial transfer from the test data input pin (ETDI). Data from SDIR can be output via the test data output pin (ETDO). The bypass register (SDBPR) is a 1-bit register to which the ETDI and ETDO pins are connected in BYPASS, CLAMP, or HIGHZ mode. The boundary scan register (SDBSR) is a 346-bit register in H8S/2472 group, 333-bit register in H8S/2462 group to which the ETDI and ETDO pins are connected in SAMPLE/PRELOAD or EXTEST mode. The ID code register (SDIDR) is a 32-bit register; a fixed code can be output via the ETDO pin in IDCODE mode. All registers cannot be accessed directly by the CPU. Table 26.2 shows the kinds of serial transfer possible with each JTAG register. Table 26.2 JTAG Register Serial Transfer
Register SDIR SDBPR SDBSR SDIDR Serial Input Possible Possible Possible Impossible Serial Output Possible Possible Possible Possible
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Section 26 Boundary Scan (JTAG)
26.3.1
Instruction Register (SDIR)
SDIR is a 32-bit register. JTAG instructions can be transferred to SDIR by serial input from the ETDI pin. SDIR can be initialized when the ETRST pin is low or the TAP controller is in the Test-Logic-Reset state, but is not initialized by a reset or in standby mode. Only 4-bit instructions can be transferred to SDIR. If an instruction exceeding 4 bits is input, the last 4 bits of the serial data will be stored in SDIR.
Bit 31 30 29 28 Bit Name TS3 TS2 TS1 TS0 Initial Value 1 1 1 0 R/W R/W R/W R/W R/W Description Test Set Bits 0000: EXTEST mode 0001: Setting prohibited 0010: CLAMP mode 0011: HIGHZ mode 0100: SAMPLE/PRELOAD mode 0101: Setting prohibited : : 1101: Setting prohibited 1110: IDCODE mode (Initial value) 1111: BYPASS mode 27 to 14 13 12 11 All 0 1 0 1 All 0 1 R R R R R R Reserved These bits are always read as 0 and cannot be modified. Reserved This bit is always read as 1 and cannot be modified. Reserved This bit is always read as 0 and cannot be modified. Reserved This bit is always read as 1 and cannot be modified. 10 to 1 0 Reserved These bits are always read as 0 and cannot be modified. Reserved This bit is always read as 1 and cannot be modified.
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Section 26 Boundary Scan (JTAG)
26.3.2
Bypass Register (SDBPR)
SDBPR is a 1-bit shift register. In BYPASS, CLAMP, or HIGHZ mode, SDBPR is connected between the ETDI and ETDO pins. 26.3.3 Boundary Scan Register (SDBSR)
SDBSR is a shift register provided on the PAD for controlling the I/O pins of this LSI. Using EXTEST mode or SAMPLE/PRELOAD mode, a boundary scan test conforming to the IEEE1149.1 standard can be performed. Table 26.3 shows the relationship between the pins of this LSI and the boundary scan register.
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Section 26 Boundary Scan (JTAG)
Table 26.3 Correspondence between Pins and Boundary Scan Register (H8S/2472 Group)
Pin No. Pin Name Input/Output Bit No. from ETDI Pin No. Pin Name Input/Output Bit No. E3 PF6 Input Enable Output A1 VCC C3 P45 Input Enable Output B1 P46 Input Enable Output C2 P47 Input Enable Output D3 P56 Input Enable Output C1 P57 Input Enable Output D2 VSS E4 RES D1 MD1 Input 345 344 343 342 341 340 339 338 337 336 335 334 333 332 331 330 G1 P96 G3 P97 G4 P50 F2 P51 F1 MD2 F3 VCL F4 NC E1 STBY E2 NMI Input Input Input Enable Output Input Enable Output Input Enable Output Input Enable Output 329 328 327 326 325 324 323 322 321 320 319 318 317 316 315 314 313
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Section 26 Boundary Scan (JTAG)
Pin No. Pin Name Input/Output Bit No. G2 P95 Input Enable Output H4 P94 Input Enable Output H3 P93 Input Enable Output H1 NC H2 P92 Input Enable Output J4 P91 Input Enable Output J3 P90 Input Enable Output J1 NC J2 PC7 Input Enable Output K4 PC6 Input Enable Output 312 311 310 309 308 307 306 305 304 303 302 301 300 299 298 297 296 295 294 293 292 291 290 289
Pin No. Pin Name Input/Output Bit No. K3 PC5 Input Enable Output K1 PC4 Input Enable Output K2 PC3 Input Enable Output L3 NC L1 PC2 Input Enable Output L2 NC L4 PC1 Input Enable Output M1 NC M2 PC0 Input Enable Output M3 PA7 Input Enable Output 288 287 286 285 284 283 282 281 280 279 278 277 276 275 274 273 272 271 270 269 268
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Section 26 Boundary Scan (JTAG)
Pin No. Pin Name Input/Output Bit No. N1 PA6 Input Enable Output M4 PA5 Input Enable Output N2 VCC P1 PA4 Input Enable Output P2 PA3 Input Enable Output R1 NC N3 PA2 Input Enable Output R2 NC P3 PA1 Input Enable Output N4 NC 267 266 265 264 263 262 261 260 259 258 257 256 255 254 253 252 251 250
Pin No. Pin Name Input/Output Bit No. R3 PA0 Input Enable Output P4 NC M5 VSS R4 NC N5 P87 Input Enable Output P5 P86 Input Enable Output R5 P85 Input Enable Output M6 P84 Input Enable Output N6 P83 Input Enable Output R6 P82 Input Enable Output 249 248 247 246 245 244 243 242 241 240 239 238 237 236 235 234 233 232 231 230 229
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Section 26 Boundary Scan (JTAG)
Pin No. Pin Name Input/Output Bit No. P6 P81 Input Enable Output M7 P80 Input Enable Output N7 NC R7 PE7 Input Enable Output P7 NC M8 PE6 Input Enable Output N8 PE5 Input Enable Output R8 PE4 Input Enable Output P8 PE3 Input Enable Output M9 PE2 Input Enable Output 228 227 226 225 224 223 222 221 220 219 218 217 216 215 214 213 212 211 210 209 208 207 206 205
Pin No. Pin Name Input/Output Bit No. N9 PE1 Input Enable Output R9 PE0 Input Enable Output P9 VCC M10 PD7 Input Enable Output N10 PD6 Input Enable Output R10 PD5 Input Enable Output P10 PD4 Input Enable Output N11 PD3 Input Enable Output R11 PD2 Input Enable Output P11 PD1 Input Enable Output 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178
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Section 26 Boundary Scan (JTAG)
Pin No. Pin Name Input/Output Bit No. M11 PD0 Input Enable Output R12 NC P12 AVSS N12 P70 Input R13 P71 Input M12 P72 Input P13 P73 Input R14 P74 Input P14 P75 Input R15 P76 Input 177 176 175 174 173 172 171 170 169 168
Pin No. Pin Name Input/Output Bit No. N13 P77 Input P15 AVCC N14 AVref M13 P60 Input Enable Output N15 P61 Input Enable Output M14 P62 Input Enable Output L12 P63 Input Enable Output M15 P64 Input Enable Output L13 P65 Input Enable Output L14 P66 Input Enable Output 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146
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Section 26 Boundary Scan (JTAG)
Pin No. Pin Name Input/Output Bit No. L15 P67 Input Enable Output K12 VCC K13 DrVCC K15 USD K14 USD+ J12 NC J13 DrVSS J15 PUPDPLS Output J14 VBUS H12 ETMS 145 144 143 142
Pin No. Pin Name Input/Output Bit No. H13 ETDO H15 ETDI H14 ETCK G12 ETRST G13 PF2 Input Enable Output G15 PF1 Input Enable Output G14 PF0 Input Enable Output F12 NC F13 VSS F15 P27 Input Enable Output 141 140 139 138 137 136 135 134 133 132 131 130
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Section 26 Boundary Scan (JTAG)
Pin No. Pin Name Input/Output Bit No. F14 P26 Input Enable Output E13 P25 Input Enable Output E15 P24 Input Enable Output E14 P23 Input Enable Output E12 P22 Input Enable Output D15 P21 Input Enable Output D14 P20 Input Enable Output D13 P17 Input Enable Output C15 P16 Input Enable Output D12 P15 Input Enable Output 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100
Pin No. Pin Name Input/Output Bit No. C14 P14 Input Enable Output B15 P13 Input Enable Output B14 P12 Input Enable Output A15 P11 Input Enable Output C13 VSS A14 P10 Input Enable Output B13 PB7 Input Enable Output C12 PB6 Input Enable Output A13 PB5 Input Enable Output B12 PB4 Input Enable Output 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
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Section 26 Boundary Scan (JTAG)
Pin No. Pin Name Input/Output Bit No. D11 PB3 Input Enable Output A12 PB2 Input Enable Output C11 PB1 Input Enable Output B11 PB0 Input Enable Output A11 VCC D10 P30 Input Enable Output C10 P31 Input Enable Output A10 P32 Input Enable Output B10 P33 Input Enable Output D9 P34 Input Enable Output 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46
Pin No. Pin Name Input/Output Bit No. C9 P35 Input Enable Output A9 P36 Input Enable Output B9 P37 Input Enable Output D8 P40 Input Enable Output C8 P41 Input Enable Output A8 P42 Input Enable Output B8 P43 Input Enable Output D7 PEVref C7 PECI A7 P52 Input Enable Output 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
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Section 26 Boundary Scan (JTAG)
Pin No. Pin Name Input/Output Bit No. B7 P53 Input Enable Output D6 FWE Input C6 P54 Input Enable Output A6 P55 Input Enable Output B6 P44 Input Enable Output C5 VCC A5 UXTAL B5 UEXTAL D5 UXSEL 21 20 19 18 17 16 15 14 13 12 11 10 9
Pin No. Pin Name Input/Output Bit No. A4 PF5 Input Enable Output B4 PF4 Input Enable Output C4 NC A3 VSS D4 PF3 Input Enable Output B3 RESO A2 XTAL B2 EXTAL to ETDO 8 7 6 5 4 3 2 1 0
Though the pin no. for the H8S/2462 Group and the H8S/2463 Group differs, the bit no. for these products is the same. The following table is listed with the pin no. of the H8S/2462 Group.
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Section 26 Boundary Scan (JTAG)
Table 26.4 Correspondence between Pins and Boundary Scan Register (H8S/2462 Group and H8S/2463 Group)
Pin No. Pin Name Input/Output Bit No. from ETDI Pin No. Pin Name Input/Output Bit No. 10 PF6 Input Enable Output 1 VCC 2 P45 Input Enable Output 3 P46 Input Enable Output 4 P47 Input Enable Output 5 P56 Input Enable Output 6 P57 Input Enable Output 7 VSS 8 RES 9 MD1 Input 332 331 330 329 328 327 326 325 324 323 322 321 320 319 318 317 19 P95 18 P96 17 P97 16 P50 15 P51 14 MD2 13 VCL 12 STBY 11 NMI Input Input Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output 316 315 314 313 312 311 310 309 308 307 306 305 304 303 302 301 300 299 298 297
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Section 26 Boundary Scan (JTAG)
Pin No. Pin Name Input/Output Bit No. 20 P94 Input Enable Output 21 P93 Input Enable Output 22 P92 Input Enable Output 23 P91 Input Enable Output 24 P90 Input Enable Output 25 PC7 Input Enable Output 26 PC6 Input Enable Output 27 PC5 Input Enable Output 28 PC4 Input Enable Output 29 PC3 Input Enable Output 296 295 294 293 292 291 290 289 288 287 286 285 284 283 282 281 280 279 278 277 276 275 274 273 272 271 270 269 268 267
Pin No. Pin Name Input/Output Bit No. 30 PC2 Input Enable Output 31 PC1 Input Enable Output 32 PC0 Input Enable Output 33 PA7 Input Enable Output 34 PA6 Input Enable Output 35 PA5 Input Enable Output 36 VCC 37 PA4 Input Enable Output 38 PA3 Input Enable Output 39 PA2 Input Enable Output 266 265 264 263 262 261 260 259 258 257 256 255 254 253 252 251 252 249 248 247 246 245 244 243 242 241 240
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Section 26 Boundary Scan (JTAG)
Pin No. Pin Name Input/Output Bit No. 40 PA1 Input Enable Output 41 PA0 Input Enable Output 42 VSS 43 P87 Input Enable Output 44 P86 Input Enable Output 45 P85 Input Enable Output 46 P84 Input Enable Output 47 P83 Input Enable Output 48 P82 Input Enable Output 49 P81 Input Enable Output 239 238 237 236 235 234 233 232 231 230 229 228 227 226 225 224 223 222 221 220 219 218 217 216 215 214 213
Pin No. Pin Name Input/Output Bit No. 50 P80 Input Enable Output 51 PE7 Input Enable Output 52 PE6 Input Enable Output 53 PE5 Input Enable Output 54 PE4 Input Enable Output 55 PE3 Input Enable Output 56 PE2 Input Enable Output 57 PE1 Input Enable Output 58 PE0 Input Enable Output 59 PD7 Input Enable Output 212 211 210 209 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183
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Section 26 Boundary Scan (JTAG)
Pin No. Pin Name Input/Output Bit No. 60 PD6 Input Enable Output 61 PD5 Input Enable Output 62 PD4 Input Enable Output 63 PD3 Input Enable Output 64 PD2 Input Enable Output 65 PD1 Input Enable Output 66 PD0 Input Enable Output 67 AVSS 68 P70 Input 69 P71 Input 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160
Pin No. Pin Name Input/Output Bit No. 70 P72 Input 71 P73 Input 72 P74 Input 73 P75 Input 74 P76 Input 75 P77 Input 76 AVCC 77 AVref 78 P60 Input Enable Output 79 P61 Input Enable Output 159 158 157 156 155 154 153 152 151 150 149 148
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Section 26 Boundary Scan (JTAG)
Pin No. Pin Name Input/Output Bit No. 80 P62 Input Enable Output 81 P63 Input Enable Output 82 P64 Input Enable Output 83 P65 Input Enable Output 84 P66 Input Enable Output 85 P67 Input Enable Output 86 VCC 87 ETMS 88 ETDO 89 ETDI 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130
Pin No. Pin Name Input/Output Bit No. 90 ETCK 91 ETRST 92 PF1 Input Enable Output 93 PF0 Input Enable Output 94 VSS 95 P27 Input Enable Output 96 P26 Input Enable Output 97 P25 Input Enable Output 98 P24 Input Enable Output 99 P23 Input Enable Output 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109
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Section 26 Boundary Scan (JTAG)
Pin No. Pin Name Input/Output Bit No. 100 P22 Input Enable Output 101 P21 Input Enable Output 102 P20 Input Enable Output 103 P17 Input Enable Output 104 P16 Input Enable Output 105 P15 Input Enable Output 106 P14 Input Enable Output 107 P13 Input Enable Output 108 P12 Input Enable Output 109 P11 Input Enable Output 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79
Pin No. Pin Name Input/Output Bit No. 110 VSS 111 P10 Input Enable Output 112 PB7 Input Enable Output 113 PB6 Input Enable Output 114 PB5 Input Enable Output 115 PB4 Input Enable Output 116 PB3 Input Enable Output 117 PB2 Input Enable Output 118 PB1 Input Enable Output 119 PB0 Input Enable Output 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
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Section 26 Boundary Scan (JTAG)
Pin No. Pin Name Input/Output Bit No. 120 VCC 121 P30 Input Enable Output 122 P31 Input Enable Output 123 P32 Input Enable Output 124 P33 Input Enable Output 125 P34 Input Enable Output 126 P35 Input Enable Output 127 P36 Input Enable Output 128 P37 Input Enable Output 129 P40 Input Enable Output 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
Pin No. Pin Name Input/Output Bit No. 130 P41 Input Enable Output 131 P42 Input Enable Output 132 P43 Input Enable Output 133 PEVref 134 PECI 135 P52 Input Enable Output 136 P53 Input Enable Output 137 FWE Input Enable Output 138 P54 Input Enable Output 139 P55 Input Enable Output 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3
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Section 26 Boundary Scan (JTAG)
Pin No. Pin Name Input/Output Bit No. 140 P44 Input Enable Output 141 VSS 142 RESO 143 XTAL 144 EXTAL to ETDO 2 1 0
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Section 26 Boundary Scan (JTAG)
26.3.4
ID Code Register (SDIDR)
SDIDR is a 32-bit register. In IDCODE mode, SDIDR can output a fixed code, H'0803D447, from the ETDO pin. However, no serial data can be written to SDIDR via the ETDI pin.
31 28 0000 Version (4 bits) 27 1000 0000 0011 12 1101 11 0100 0100 1 011 0 1 Fixed Code (1 bit)
Part Number (16 bits)
Manufacture Identify (11 bits)
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Section 26 Boundary Scan (JTAG)
26.4
26.4.1
Operation
TAP Controller State Transitions
Figure 26.2 shows the internal states of the TAP controller. State transitions basically conform to the IEEE1149.1 standard.
1
Test-logic-reset 0 1 Select-DR-scan 0 1 Select-IR-scan 0 1 Capture-DR 0 Shift-DR 1 Exit1-DR 0 Pause-DR 1 0 Exit2-DR 1 Update-DR 1 0 0 1 1 Capture-IR 0 Shift-IR 1 Exit1-IR 0 Pause-IR 1 0 Exit2-IR 1 Update-IR 1 0 0 1 1
0
Run-test/idle
0
0
Figure 26.2 TAP Controller State Transitions
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Section 26 Boundary Scan (JTAG)
26.4.2
JTAG Reset
The JTAG can be reset in two ways. * The JTAG is reset when the ETRST pin is held at 0. * When ETRST = 1, the JTAG can be reset by inputting at least five ETCK clock cycles while ETMS = 1.
26.5
Boundary Scan
The JTAG pins can be placed in the boundary scan mode stipulated by the IEEE1149.1 standard by setting a command in SDIR. 26.5.1 Supported Instructions
This LSI supports the three essential instructions defined in the IEEE1149.1 standard (BYPASS, SAMPLE/PRELOAD, and EXTEST) and optional instructions (CLAMP, HIGHZ, and IDCODE). (1) BYPASS (Instruction code: B'1111)
The BYPASS instruction is an instruction that operates the bypass register. This instruction shortens the shift path to speed up serial data transfer involving other chips on the printed circuit board. While this instruction is being executed, the test circuit has no effect on the system circuits. (2) SAMPLE/PRELOAD (Instruction code: B'0100)
The SAMPLE/PRELOAD instruction inputs values from this LSI internal circuitry to the boundary scan register, outputs values from the scan path, and loads data onto the scan path. When this instruction is being executed, this LSI's input pin signals are transmitted directly to the internal circuitry, and internal circuit values are directly output externally from the output pins. This LSI system circuits are not affected by execution of this instruction. In a SAMPLE operation, a snapshot of a value to be transferred from an input pin to the internal circuitry, or a value to be transferred from the internal circuitry to an output pin, is latched into the boundary scan register and read from the scan path. Snapshot latching does not affect normal operation of this LSI.
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Section 26 Boundary Scan (JTAG)
In a PRELOAD operation, an initial value is set in the parallel output latch of the boundary scan register from the scan path prior to the EXTEST instruction. Without a PRELOAD operation, when the EXTEST instruction was executed an undefined value would be output from the output pin until completion of the initial scan sequence (transfer to the output latch) (with the EXTEST instruction, the parallel output latch value is constantly output to the output pin). (3) EXTEST (Instruction code: B'0000)
The EXTEST instruction is provided to test external circuitry when this LSI is mounted on a printed circuit board. When this instruction is executed, output pins are used to output test data (previously set by the SAMPLE/PRELOAD instruction) from the boundary scan register to the printed circuit board, and input pins are used to latch test results into the boundary scan register from the printed circuit board. If testing is carried out by using the EXTEST instruction N times, the Nth test data is scanned in when test data (N-1) is scanned out. Data loaded into the output pin boundary scan register in the Capture-DR state is not used for external circuit testing (it is replaced by a shift operation). (4) CLAMP (Instruction code: B'0010)
When the CLAMP instruction is enabled, the output pin outputs the value of the boundary scan register that has been previously set by the SAMPLE/PRELOAD instruction. While the CLAMP instruction is enabled, the state of the boundary scan register maintains the previous state regardless of the state of the TAP controller. A bypass register is connected between the ETDI and ETDO pins. The related circuit operates in the same way when the BYPASS instruction is enabled. (5) HIGHZ (Instruction code: B'0011)
When the HIGHZ instruction is enabled, all output pins enter a high-impedance state. While the HIGHZ instruction is enabled, the state of the boundary scan register maintains the previous state regardless of the state of the TAP controller. A bypass register is connected between the ETDI and ETDO pins. The related circuit operates in the same way when the BYPASS instruction is enabled.
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Section 26 Boundary Scan (JTAG)
(6)
IDCODE (Instruction code: B'1110)
When the IDCODE instruction is enabled, the value of the ID code register is output from the ETDO pin with LSB first when the TAP controller is in the Shift-DR state. While the IDCODE instruction is being executed, the test circuit does not affect the system circuit. When the TAP controller is in the Test-Logic-Reset state, the instruction register is initialized to the IDCODE instruction. Notes: 1. Boundary scan mode does not cover power-supply-related pins (VCC, VCL, VSS, AVCC, AVSS, Avref, PEVref, DrVCC, DrVSS, and VBUS). 2. Boundary scan mode does not cover clock-related pins (EXTAL, XTAL, UEXTAL, UXTAL). 3. Boundary scan mode does not cover reset- and standby-related pins (RES, STBY, and RESO). 4. Boundary scan mode does not cover JTAG-related pins (ETCK, ETDI, ETDO, ETMS, and ETRST). 5. Fix the MD2 pin high. 6. Use the STBY pin in high state. 7. Boundary scan mode does not cover the PECI pin. 8. Boundary scan mode does not cover the USB pins (USB+, USB-).
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Section 26 Boundary Scan (JTAG)
26.6
Usage Notes
1. A reset must always be executed by driving the ETRST pin to 0, regardless of whether or not the JTAG is to be activated. The ETRST pin must be held low for 20 ETCK clock cycles. For details, see section 31, Electrical Characteristics. To activate the JTAG after a reset, drive the ETRST pin to 1 and specify the ETCK, ETMS, and ETDI pins to any value. If the JTAG is not to be activated, drive the ETRST, ETCK, ETMS, and ETDI pins to 1 or the high-impedance state. 2. The following must be considered when the power-on reset signal is applied to the ETRST pin. The reset signal must be applied at power-on. To prevent the LSI system operation from being affected by the ETRST pin of the board tester, circuits must be separated. Alternatively, to prevent the ETRST pin of the board tester from being affected by the LSI system reset, circuits must be separated. Figure 26.3 shows a design example of the reset signal circuit wherein no reset signal interference occurs.
Board edge pin System reset Power-on reset circuit ETRST ETRST
This LSI RES
Figure 26.3 Reset Signal Circuit Without Reset Signal Interference
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Section 26 Boundary Scan (JTAG)
3. The registers are not initialized in standby mode. If the ETRST pin is set to 0 in standby mode, IDCODE mode will be entered. 4. The frequency of the ETCK pin must be lower than that of the system clock. For details, see section 31, Electrical Characteristics. 5. Data input/output in serial data transfer starts from the LSB. Figure 26.4 and 26.5 shows examples of serial data input/output. 6. When data that exceeds the number of bits of the register connected between the ETDI and ETDO pins is serially transferred, the serial data that exceeds the number of register bits and output from the ETDO pin is the same as that input from the ETDI pin. 7. If the JTAG serial transfer sequence is disrupted, the ETRST pin must be reset. Transfer should then be retried, regardless of the transfer operation. 8. If a pin with a pull-up function is sampled while its pull-up function is enabled, 1 can be detected at the corresponding input scan register. In this case, the corresponding enable scan register should be cleared to 0. 9. If a pin with an open-drain function is sampled while its open-drain function is enabled and its corresponding output scan register is 1, 0 can be detected at the corresponding enable scan register.
SDIR serial data input/output SDIR is captured into the shift register in Capture-IR, and bits 0 to 31 of SDIR are output in that order from the ETDO pin in Shift-IR. Data input from the ETDI pin is written to SDIR in Update-IR. ETDI Bit 31 . . . . . . . . . . .
Shift register
ETDI Bit 31
Shift register
Bit 31 Bit 28
. . .
Bit 31 Bit 28 SDIR
SDIR
Bit 0 ETDO
Bit 0 ETDO
Capture-IR
Update-IR
Figure 26.4 Serial Data Input/Output (1)
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Section 26 Boundary Scan (JTAG)
SDIDR serial data input/output SDIDR is captured into the shift register in Capture-DR in IDCODE mode, and bits 0 to 31 of SDIDR are output in that order from the ETDO pin in Shift-DR. Data input from the ETDI pin is not written to any register in Update-DR. ETDI Bit 31 Bit 31
Shift register
. . . .
SDIDR
Bit 0
Bit 0
ETDO
Capture-DR
Figure 26.5 Serial Data Input/Output (2)
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Section 26 Boundary Scan (JTAG)
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Section 27 Clock Pulse Generator
Section 27 Clock Pulse Generator
This LSI incorporates a clock pulse generator which generates the system clock (), internal clock, bus master clock, and subclock (SUB). The clock pulse generator consists of an oscillator, PLL multiplier circuit, system clock select circuit, medium-speed clock divider, bus master clock select circuit, subclock input circuit, and subclock waveform shaping circuit. Figure 27.1 shows a block diagram of the clock pulse generator.
EXTAL
Oscillator
XTAL
PLL multiplier circuit
System clock select circuit
Mediumspeed clock /2 divider to /32
Bus master clock select circuit
EXCL
Subclock input circuit
Subclock waveform shaping circuit
SUB
WDT_1 count clock
System clock to pin
Internal clock to peripheral modules
Bus master clock to CPU and DTC
Figure 27.1 Block Diagram of Clock Pulse Generator The bus master clock is selected as either high-speed mode or medium-speed mode by software according to the settings of the SCK2 to SCK0 bits in the standby control register. Use of the medium-speed clock (/2 to /32) may be limited during CPU operation and when accessing the internal memory of the CPU. The operation speed of the DTC and the external space access cycle are thus stabilized regardless of the setting of medium-speed mode. For details on the standby control register, see section 28.1.1, Standby Control Register (SBYCR). The subclock input is controlled by software according to the EXCLE bit setting in the low power control register. For details on the low power control register, see section 28.1.2, Low-Power Control Register (LPWRCR).
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Section 27 Clock Pulse Generator
27.1
Oscillator
Clock pulses can be supplied either by connecting a crystal resonator or by providing external clock input. 27.1.1 Connecting Crystal Resonator
Figure 27.2 shows a typical method of connecting a crystal resonator. An appropriate damping resistance Rd, given in table 27.1, should be used. An AT-cut parallel-resonance crystal resonator should be used. Figure 27.3 shows the equivalent circuit of a crystal resonator. A crystal resonator having the characteristics given in table 27.2 should be used.
CL1 EXTAL XTAL Rd CL2 CL1 = CL2 = 10 to 22 pF
Figure 27.2 Typical Connection to Crystal Resonator Table 27.1 Damping Resistance Values
Frequency (MHz) Rd () 5 300 8 200 8.5 0
CL L XTAL Rs EXTAL AT-cut parallel-resonance crystal resonator
C0
Figure 27.3 Equivalent Circuit of Crystal Resonator
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Section 27 Clock Pulse Generator
Table 27.2 Crystal Resonator Parameters
Frequency (MHz) RS (max) () C0 (max) (pF) 5 100 7 8 80 7 8.5 70 7
27.1.2
External Clock Input Method
Figure 27.4 shows a typical method of connecting an external clock signal. To leave the XTAL pin open, incidental capacitance should be 10 pF or less. To input an inverted clock to the XTAL pin, the external clock should be tied to high in standby mode.
EXTAL XTAL Open
External clock input
(a) Example of external clock input when XTAL pin left open
EXTAL XTAL
External clock input
(b) Example of external clock input when an inverted clock is input to XTAL pin
Figure 27.4 Example of External Clock Input When a specified clock signal is input to the EXTAL pin, internal clock signal output is determined after the external clock output stabilization delay time (tDEXT) has passed. As the clock signal output is not determined during the tDEXT cycle, a reset signal should be set to low to hold it in reset state. For the external clock output stabilization delay time, refer to section 31, Electrical Characteristics.
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Section 27 Clock Pulse Generator
27.2
PLL Multiplier Circuit
The PLL multiplier circuit generates a clock of 4 times the frequency of its input clock. The frequency range of the multiplied clock is shown in table 27.3. Table 27.3 Ranges of Multiplied Clock Frequency
Input Clock (MHz) Crystal Resonator, External Clock 5 to 8.5 Multiplier 4 System Clock (MHz) 20 to 34
27.3
Medium-Speed Clock Divider
The medium-speed clock divider divides the system clock (), and generates /2, /4, /8, /16, and /32 clocks.
27.4
Bus Master Clock Select Circuit
The bus master clock select circuit selects a clock to supply the bus master with either the system clock () or medium-speed clock (/2, /4, /8, /16, or /32) by the SCK2 to SCK0 bits in SBYCR.
27.5
Subclock Input Circuit
The subclock input circuit controls subclock input from the EXCL pin. To use the subclock, a 32.768-kHz external clock should be input from the EXCL pin. At this time, the P56DDR bit in P5DDR should be cleared to 0, and the EXCLE bit in LPWRCR should be set to 1. When the subclock is not used, subclock input should not be enabled.
27.6
Subclock Waveform Shaping Circuit
To remove noise from the subclock input at the EXCL pin, the subclock is sampled by a divided clock. The sampling frequency is set by the NESEL bit in LPWRCR.
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Section 27 Clock Pulse Generator
27.7
Clock Select Circuit
The clock select circuit selects the system clock that is used in this LSI. A clock generated by the oscillator, to which the EXTAL and XTAL pins are input, and multiplied by the PLL circuit is selected as a system clock when returning from high-speed mode, mediumspeed mode, sleep mode, the reset state, or standby mode.
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Section 27 Clock Pulse Generator
27.8
27.8.1
Usage Notes
Note on Resonator
Since all kinds of characteristics of the resonator are closely related to the board design by the user, use the example of resonator connection in this document for only reference; be sure to use an resonator that has been sufficiently evaluated by the user. Consult with the resonator manufacturer about the resonator circuit ratings which vary depending on the stray capacitances of the resonator and installation circuit. Make sure the voltage applied to the oscillation pins do not exceed the maximum rating. 27.8.2 Notes on Board Design
When using a crystal resonator, the crystal resonator and its load capacitors should be placed as close as possible to the EXTAL and XTAL pins. Other signal lines should be routed away from the oscillation circuit to prevent inductive interference with the correct oscillation as shown in figure 27.5.
Prohibited CL2 Signal A Signal B This LSI XTAL EXTAL CL1
Figure 27.5 Note on Board Design of Oscillation Circuit Section 27.8.3 Note on Operation Check
This LSI may oscillate at several kHz of frequency even when a crystal resonator is not connected to the EXTAL and XTAL pins or an external clock is not input. Use this LSI after confirming that the LSI operates with appropriate frequency.
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Section 28 Power-Down Modes
Section 28 Power-Down Modes
For operating modes after the reset state is cancelled, this LSI has not only the normal program execution state but also four power-down modes in which power consumption is significantly reduced. In addition, there is also module stop mode in which reduced power consumption can be achieved by individually stopping on-chip peripheral modules. * Medium-speed mode System clock frequency for the CPU operation can be selected as /2, /4, /8, /16,or /32. * Sleep mode The CPU stops but on-chip peripheral modules continue operating. * Software standby mode Clock oscillation stops, and the CPU and on-chip peripheral modules stop operating. * Hardware standby mode Clock oscillation stops, and the CPU and on-chip peripheral modules enter reset state. * Module stop mode Independently of above operating modes, on-chip peripheral modules that are not used can be stopped individually.
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Section 28 Power-Down Modes
28.1
Register Descriptions
Power-down modes are controlled by the following registers. To access SBYCR, LPWRCR, MSTPCRH, and MSTPCRL, the FLSHE bit in the serial timer control register (STCR) must be cleared to 0. For details on STCR, see section 3.2.3, Serial Timer Control Register (STCR). * Standby control register (SBYCR) * Low power control register (LPWRCR) * Module stop control register H (MSTPCRH) * Module stop control register L (MSTPCRL) * Module stop control register A (MSTPCRA) * Sub-chip module stop control register BH, BL (SUBMSTPBH, SUBMSTPBL) 28.1.1 Standby Control Register (SBYCR)
SBYCR controls power-down modes.
Bit 7 Bit Name SSBY Initial Value 0 R/W R/W Description Software Standby Specifies the operating mode to be entered after executing the SLEEP instruction. When the SLEEP instruction is executed in high-speed mode or medium-speed mode: 0: Shifts to sleep mode 1: Shifts to software standby mode Note that the SSBY bit is not changed even if a mode transition occurs by an interrupt.
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Section 28 Power-Down Modes
Bit 6 5 4
Bit Name STS2 STS1 STS0
Initial Value 0 0 0
R/W R/W R/W R/W
Description Standby Timer Select 2 to 0 Select the wait time for clock settling from clock oscillation start when canceling software standby mode. Select a wait time of 8 ms (oscillation settling time) or more, depending on the operating frequency. With an external clock, select a wait time of 500 s (external clock output settling delay time) or more, depending on the operating frequency. Table 28.1 shows the relationship between the STS2 to STS0 values and wait time.
3
DTSPEED
0
R/W
DTC Speed Specifies the operating clock for the bus masters (DTC) other than the CPU in medium-speed mode. 0: All bus masters operate based on the medium-speed clock. 1: The DTC operates based on the system clock. The operating clock is changed when a DTC transfer is requested even if the CPU operates based on the medium-speed clock.
2 1 0
SCK2 SCK1 SCK0
0 0 0
R/W R/W R/W
System Clock Select 2 to 0 Select a clock for the bus master in high-speed mode or medium-speed mode. 000: High-speed mode (Initial value) 001: Medium-speed clock: /2 010: Medium-speed clock: /4 011: Medium-speed clock: /8 100: Medium-speed clock: /16 101: Medium-speed clock: /32 11x: Must not be set.
[Legend] x: Don't care
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Section 28 Power-Down Modes
Table 28.1 Operating Frequency and Wait Time
STS2 0 0 0 0 1 1 1 STS1 0 0 1 1 0 0 1 STS0 0 1 0 1 0 1 x Wait Time 8192 states 16384 states 32768 states 65536 states 131072 states 262144 states Reserved* 20MHz 0.4 0.8 1.6 3.3 6.6 13.1 25MHz 0.3 0.7 1.3 2.6 5.2 10.5 34MHz 0.2 0.5 1.0 1.9 3.9 7.7 Unit ms
Recommended specification Note: * Setting prohibited. [Legend] x: Don't care
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Section 28 Power-Down Modes
28.1.2
Low-Power Control Register (LPWRCR)
LPWRCR controls power-down modes.
Bit 7, 6 5 Bit Name NESEL Initial Value 0 0 R/W R/W R/W Description Reserved The initial value should not be changed. Noise Elimination Sampling Frequency Select Selects the frequency by which the subclock (SUB) input from the EXCL pin is sampled using the clock () generated by the system clock pulse generator. 0: Sampling using /32 clock 1: Sampling using /4 clock 4 EXCLE 0 R/W Subclock Input Enable Enables/disables subclock input from the EXCL pin. 0: Disables subclock input from the EXCL pin 1: Enables subclock input from the EXCL pin 3 2 PNCCS 0 0 R/W R/W Reserved The initial value should not be changed. Address Multiplex Chip Select Controls the output polarity of chip select signals (CS256, IOS) in the address multiplex extended mode. 0: Outputs CS256, and IOS 1: Outputs CS256, and IOS 1 PNCAH 0 R/W Address Multiplex Address Hold Controls the output polarity of the address hold signal (AH) in the address multiplex extended mode. 0: Outputs AH 1: Outputs AH 0 0 R/W Reserved The initial value should not be changed.
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Section 28 Power-Down Modes
28.1.3
Module Stop Control Registers H, L, and A (MSTPCRH, MSTPCRL, MSTPCRA)
MSTPCR specifies on-chip peripheral modules to shift to module stop mode in module units. Each module can enter module stop mode by setting the corresponding bit to 1. * MSTPCRH
Bit 7 6 5 4 3 2 1 0 Bit Name Initial Value R/W MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 0 0 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W Corresponding Module Reserved The initial value should not be changed. Data transfer controller (DTC) 16-bit free-running timer (FRT) 8-bit timers (TMR_0, TMR_1) 14-bit PWM timer (PWMX) Reserved The initial value should not be changed. A/D converter 8-bit timers (TMR_X, TMR_Y)
* MSTPCRL
Bit 7 6 5 4 3 2 1 0 Bit Name Initial Value R/W MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W Corresponding Module Serial communication interface 3 (SCI_3) Serial communication interface 1 (SCI_1) Reserved The initial value should not be changed. I C bus interface channel 0 (IIC_0) I C bus interface channel 1 (IIC_1) I C bus interface channel 2, 3 (IIC_2, IIC_3) CRC operation circuit I C bus interface channel 4, 5 (IIC_4, IIC_5)
2 2 2 2
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Section 28 Power-Down Modes
* MSTPCRA
Bit Bit Name Initial Value All 0 0 0 0 R/W R/W R/W R/W R/W Corresponding Module Reserved The initial values should not be changed. 14-bit PWM timer (PWMX_1) 14-bit PWM timer (PWMX_0) Reserved The initial value should not be changed.
7 to 3 MSTPA7 to MSTPA3 2 1 0 MSTPA2 MSTPA1 MSTPA0
MSTPCR sets operation and stop by the combination of bits as follows:
MSTPCRH (bit 3) MSTPCRA (bit 2) MSTP11 MSTPA2 0 0 1 0 1 x Function 14-bit PWM timer (PWMX_1) operates. 14-bit PWM timer (PWMX_1) stops. Reserved
MSTPCRH (bit 3) MSTPCRA (bit 1) MSTP11 MSTPA1 0 0 1 0 1 x
Function 14-bit PWM timer (PWMX_0) operates. 14-bit PWM timer (PWMX_0) stops. Reserved
Note: Bit 3 of MSTPCRH is the module stop bit for PWMX_0 and PWMX_1. [Legend] x: Don't care
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Section 28 Power-Down Modes
28.1.4
Sub-Chip Module Stop Control Registers BH, BL (SUBMSTPBH, SUBMSTPBL)
SUBMSTPB specifies on-chip peripheral modules to shift to module stop mode in module units. Each module can enter module stop mode by setting the corresponding bit to 1. * SUBMSTPBH
Bit 7 6 5 4 Bit Name SMSTPB15 SMSTPB14 SMSTPB13 SMSTPB12 Initial Value 1 1 1 1 R/W R/W R/W R/W R/W Corresponding Module Reserved The initial values should not be changed. Ethernet controller (EtherC) DMAC for Ethernet (E-DMAC) USB function module (USB) This bit is valid only in the H8S/2472 Group. The initial value should not be changed in the H8S/2462 Group. 3 to 0 SMSTPB11 All 1 to SMSTPB8 R/W Reserved The initial values should not be changed.
* SUBMSTPBL
Bit Bit Name Initial Value R/W R/W R/W Corresponding Module Reserved The initial values should not be changed. PECI This bit is not incorporated in the H8S/2463 Group. The initial values should not be changed. 3 2 1 0 SMSTPB3 SMSTPB2 SMSTPB1 SMSTPB0 1 1 1 1 R/W R/W R/W R/W Serial communication interface with FIFO (SCIF) Synchronous serial communication unit (SSU) LPC interface (LPC) Reserved The initial values should not be changed.
7 to 5 SMSTPB7 All 1 to SMSTPB5 4 SMSTPB4 1
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Section 28 Power-Down Modes
28.2
Mode Transitions and LSI States
Figure 28.1 shows the enabled mode transition diagram. The mode transition from program execution state to program halt state is performed by the SLEEP instruction. The mode transition from program halt state to program execution state is performed by an interrupt. The STBY input causes a mode transition from any state to hardware standby mode. The RES input causes a mode transition from a state other than hardware standby mode to the reset state. Table 28.2 shows the LSI internal states in each operating mode.
Program halt state STBY pin = Low Reset state STBY pin = High RES pin = Low Program execution state RES pin = High SSBY = 0 SLEEP instruction High-speed mode (main clock) Any interrupt * SCK2 to SCK0 are 0 SCK2 to SCK0 are not 0 SLEEP instruction External interrupt * USB suspend/ resume interrupt SSBY = 1, PSS = 0 Software standby mode Sleep mode (main clock) Hardware standby mode
Medium-speed mode (main clock)
: Transition after exception handling
: Power-down mode
Note: * When a transition is made between modes by means of an interrupt, the transition cannot be made on interrupt source generation alone. Ensure that interrupt handling is performed after accepting the interrupt request.
Figure 28.1 Mode Transition Diagram
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Section 28 Power-Down Modes
Table 28.2 LSI Internal States in Each Mode
Function
System clock pulse generator Subclock pulse generator CPU Instruction execution Registers External interrupts NMI IRQ0 to IRQ15 Peripheral DTC modules Functioning Functioning in medium-speed mode/ Functioning Functioning Functioning Functioning /Halted (retained) Halted (retained) Halted (reset) Functioning
HighSpeed
Functioning Functioning Functioning
MediumSpeed
Functioning Functioning Functioning in medium-speed mode Functioning
Sleep
Functioning Functioning Halted
Module Stop
Functioning Functioning Functioning
Software Standby
Halted Halted Halted
Hardware Standby
Halted Halted Halted
Retained Functioning Functioning
Retained Functioning
Undefined Halted
WDT_1 WDT_0 TMR_0,TMR_1 LPC FRT TMR_X, TMR_Y IIC_0 to IIC_5 CRC SCI_1, SCI_3 SCIF, SSU, PECI EtherC, E-DMAC, USB PWMX_0,PWMX_1 A/D converter RAM Functioning
Functioning
Functioning /Halted (retained)
Functioning
Functioning
Functioning Halted Halted (reset) /Halted (retained/ reset) (retained/ reset)
Halted
Functioning/ Halted (reset) Functioning (DTC) Functioning
Halted (reset)
Functioning
Retained
Retained High impedance
I/O
Notes: Halted (retained) means that internal register values are retained. The internal state is operation suspended. Halted (reset) means that internal register values and internal states are initialized. In module stop mode, only modules for which a stop setting has been made are halted (reset or retained).
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Section 28 Power-Down Modes
28.3
Medium-Speed Mode
The CPU makes a transition to medium-speed mode as soon as the current bus cycle ends according to the setting of the SCK2 to SCK0 bits in SBYCR. In medium-speed mode, the CPU operates on the operating clock (/2, /4, /8, /16, or /32) specified by the SCK2 to SCK0 bits. The bus masters other than the CPU (DTC) also operate in medium-speed mode when the DTSPEED bit in SBYCR is cleared to 0. On-chip peripheral modules other than the bus masters always operate on the system clock (). When the DTSPEED bit in SBYCR is set to 1, the clock can be used as the DTC operating clock. In medium-speed mode, a bus access is executed in the specified number of states with respect to the bus master operating clock. For example, if /4 is selected as the operating clock, on-chip memory is accessed in 4 states, and internal I/O registers in 8 states. By clearing all of bits SCK2 to SCK0 to 0, a transition is made to high-speed mode at the end of the current bus cycle. If a SLEEP instruction is executed when the SSBY bit in SBYCR is cleared to 0, a transition is made to sleep mode. When sleep mode is cleared by an interrupt, medium-speed mode is restored. When the SLEEP instruction is executed with the SSBY bit set to 1 and the PSS bit in TCSR (WDT_1) cleared to 0, operation shifts to software standby mode. When software standby mode is cleared by an external interrupt, medium-speed mode is restored. When the RES pin is set low, medium-speed mode is cancelled and operation shifts to the reset state. The same applies in the case of a reset caused by overflow of the watchdog timer. When the STBY pin is driven low, a transition is made to hardware standby mode. Figure 28.2 shows an example of medium-speed mode timing.
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Section 28 Power-Down Modes
Medium-speed mode
, peripheral module clock
Bus master clock
Internal address bus
SBYCR
SBYCR
Internal write signal
Figure 28.2 Medium-Speed Mode Timing
28.4
Sleep Mode
The CPU makes a transition to sleep mode if the SLEEP instruction is executed when the SSBY bit in SBYCR is cleared to 0. In sleep mode, CPU operation stops but the peripheral modules do not stop. The contents of the CPU's internal registers are retained. Sleep mode is exited by any interrupt, the RES pin, or the STBY pin. When an interrupt occurs, sleep mode is exited and interrupt exception handling starts. Sleep mode is not exited if the interrupt is disabled, or interrupts other than NMI are masked by the CPU. Setting the RES pin level low cancels sleep mode and selects the reset state. After the oscillation settling time has passed, driving the RES pin high causes the CPU to start reset exception handling. When the STBY pin level is driven low, a transition is made to hardware standby mode.
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Section 28 Power-Down Modes
28.5
Software Standby Mode
The CPU makes a transition to software standby mode when the SLEEP instruction is executed with the SSBY bit in SBYCR set to 1 and the PSS bit in TCSR (WDT_1) cleared to 0. In software standby mode, the CPU, on-chip peripheral modules, and clock pulse generator all stop. However, the contents of the CPU registers, on-chip RAM data, I/O ports, and the states of on-chip peripheral modules other than the PWMX, A/D converter, and part of the SCI are retained as long as the prescribed voltage is supplied. Software standby mode is cleared by an external interrupt (NMI, IRQ0 to IRQ15), the USB suspend/resume interrupt (RESUME), the RES pin input, or STBY pin input. When an external interrupt request signal is input, system clock oscillation starts, and after the elapse of the time set in bits STS2 to STS0 in SBYCR, software standby mode is cleared, and interrupt exception handling is started. When exiting software standby mode by IRQ0 to IRQ15 interrupt, set the corresponding enable bit to 1 and ensure that any interrupt with a higher priority than IRQ0 to IRQ15 is not generated. Software standby mode is not exited if the corresponding enable bit is cleared to 0 or if the interrupt has been masked by the CPU. When the RES pin is driven low, system clock oscillation is started. At the same time as system clock oscillation starts, the system clock is supplied to the entire LSI. Note that the RES pin must be held low until clock oscillation settles. When the RES pin goes high after clock oscillation settles, the CPU begins reset exception handling. When the STBY pin is driven low, software standby mode is cancelled and a transition is made to hardware standby mode. Figure 28.3 shows an example in which a transition is made to software standby mode at the falling edge of the NMI pin, and software standby mode is cleared at the rising edge of the NMI pin. In this example, an NMI interrupt is accepted with the NMIEG bit in SYSCR cleared to 0 (falling edge specification), then the NMIEG bit is set to 1 (rising edge specification), the SSBY bit is set to 1, and a SLEEP instruction is executed, causing a transition to software standby mode. Software standby mode is then cleared at the rising edge of the NMI pin.
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Section 28 Power-Down Modes
Oscillator
NMI
NMIEG
SSBY
NMI exception Software standby mode handling (power-down mode) NMIEG = 1 SSBY = 1 SLEEP instruction
Oscillation stabilization time tOSC2
NMI exception handling
Figure 28.3 Software Standby Mode Application Example
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Section 28 Power-Down Modes
28.6
Hardware Standby Mode
The CPU makes a transition to hardware standby mode from any mode when the STBY pin is driven low. In hardware standby mode, all functions enter the reset state. As long as the prescribed voltage is supplied, on-chip RAM data is retained. The I/O ports are set to the high-impedance state. In order to retain on-chip RAM data, the RAME bit in SYSCR should be cleared to 0 before driving the STBY pin low. Do not change the state of the mode pins (MD2 and MD1) while this LSI is in hardware standby mode. Hardware standby mode is cleared by the STBY pin input or the RES pin input. When the STBY pin is driven high while the RES pin is low, clock oscillation is started. Ensure that the RES pin is held low until system clock oscillation settles. When the RES pin is subsequently driven high after the clock oscillation settling time has passed, reset exception handling starts. Figure 28.4 shows an example of hardware standby mode timing.
Oscillator
RES
STBY
Oscillation stabilization time
Reset exception handling
Figure 28.4 Hardware Standby Mode Timing
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Section 28 Power-Down Modes
28.7
Module Stop Mode
Module stop mode can be individually set for each on-chip peripheral module. When the corresponding MSTP bit in MSTPCR and SUBMSTP is set to 1, module operation stops at the end of the bus cycle and a transition is made to module stop mode. In turn, when the corresponding MSTP bit is cleared to 0, module stop mode is cancelled and the module operation resumes at the end of the bus cycle. In module stop mode, the internal states of on-chip peripheral modules other than the PWMX, A/D converter, and part of the SCI are retained. After the reset state is cancelled, all modules other than DTC are in module stop mode. While an on-chip peripheral module is in module stop mode, read/write access to its registers is disabled.
28.8
28.8.1
Usage Notes
I/O Port Status
The status of the I/O ports is retained in software standby mode. Therefore, when a high level is output, the current consumption is not reduced by the amount of current to support the high level output. 28.8.2 Current Consumption when Waiting for Oscillation Settling
The current consumption increases during oscillation settling. 28.8.3 DTC Module Stop Mode
If the DTC module stop mode specification and DTC bus request occur simultaneously, the bus is released to the DTC and the MSTP bit cannot be set to 1. After completing the DTC bus cycle, set the MSTP bit to 1 again. 28.8.4 Notes on Subclock Usage
When using the subclock, make a transition to power-down mode after setting the EXCLE bit in LPWRCR to 1 and loading the subclock two or more cycles. When not using the subclock, the EXCLE bit should not be set to 1.
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Section 29 List of Registers
Section 29 List of Registers
The register list gives information on the on-chip I/O register addresses, how the register bits are configured, and the register states in each operating mode. The information is given as shown below. 1. Register Addresses (address order) * Registers are listed from the lower allocation addresses. * The MSB-side address is indicated for 16-bit and 32-bit addresses. * Registers are classified by functional modules. * The access size is indicated. 2. Register Bits * Bit configurations of the registers are described in the same order as the Register Addresses (address order) above. * Reserved bits are indicated by in the bit name column. * The bit number in the bit-name column indicates that the whole register is allocated as a counter or for holding data. * 16-bit registers are indicated from the bit on the MSB side, in 2 lines of eight bits. * 32-bit registers are indicated from the bit on the MSB side, in 4 lines of eight bits. 3. Register States in Each Operating Mode * Register states are described in the same order as the Register Addresses (address order) above. * The register states described here are for the basic operating modes. If there is a specific reset for an on-chip peripheral module, refer to the section on that on-chip peripheral module.
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Section 29 List of Registers
29.1
Register Addresses (Address Order)
The data bus width indicates the numbers of bits by which the register is accessed. The number of access states indicates the number of states based on the specified reference clock. Note: Access to undefined or reserved addresses is prohibited. Since operation or continued operation is not guaranteed when these registers are accessed, do not attempt such access.
Data Bus Width 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 Number of Access States 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
Register Name EtherC mode register EtherC status register EtherC interrupt permission register PHY interface register MAC address high register MAC address low register Receive frame length register PHY status register Transmit retry over counter register Delayed collision detect counter register Lost carrier counter register Carrier not detect counter register CRC error frame counter register Frame receive error counter register Too-short frame receive counter register Too-long frame receive counter register Residual-bit frame counter register Multicast address frame counter register IPG register Automatic PAUSE frame set register Manual PAUSE frame set register
Abbreviation ECMR ECSR ECSIPR PIR MAHR MALR RFLR PSR TROCR CDCR LCCR CNDCR CEFCR FRECR TSFRCR TLFRCR RFCR MAFCR IPGR APR MPR
Number of Bits Address 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 H'F900 H'F904 H'F908 H'F90C H'F910 H'F914 H'F918 H'F91C H'F920 H'F924 H'F928 H'F92C H'F934 H'F938 H'F93C H'F940 H'F944 H'F948 H'F954 H'F958 H'F95C
Module EtherC EtherC EtherC EtherC EtherC EtherC EtherC EtherC EtherC EtherC EtherC EtherC EtherC EtherC EtherC EtherC EtherC EtherC EtherC EtherC EtherC
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Section 29 List of Registers Data Bus Width 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 Number of Access States 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 4 4
Register Name Automatic PAUSE frame retransmission count set register E-DMAC mode register E-DMAC transmit request register E-DMAC receive request register Transmit descriptor list address register Receive descriptor list address register EtherC/E-DMAC status register EtherC/E-DMAC status interrupt permission register Transmit/receive status copy enable register Receive missed-frame counter register Transmit FIFO threshold register FIFO depth register Receiving method control register Flow control FIFO threshold register Transmit Interrupt Register Receiving-Buffer Write Address Register Receiving-Descriptor Fetch Address Register Transmission-Buffer Read Address Register Transmission-Descriptor Fetch Address Register Bit rate setting register Interrupt flag register 0
Abbreviation TPAUSER EDMR EDTRR EDRRR TDLAR RDLAR EESR EESIPR TRSCER RMFCR TFTR FDR RMCR FCFTR TRIMD RBWAR RDFAR TBRAR TDFAR ECBRR IFR0
Number of Bits Address 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 8 8 H'F964 H'F980 H'F984 H'F988 H'F98C H'F990 H'F994 H'F998 H'F99C H'F9A0 H'F9A4 H'F9A8 H'F9AC H'F9B4 H'F9BC H'F9C0 H'F9C4 H'F9CC H'F9D0 H'F9D4 H'FA00
Module EtherC E-DMAC E-DMAC E-DMAC E-DMAC E-DMAC E-DMAC E-DMAC E-DMAC E-DMAC E-DMAC E-DMAC E-DMAC E-DMAC E-DMAC E-DMAC E-DMAC E-DMAC E-DMAC E-DMAC USB
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Section 29 List of Registers Data Bus Width 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 Number of Access States 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 2 2
Register Name Interrupt flag register 1 Interrupt flag register 2 Interrupt enable register 0 Interrupt enable register 1 Interrupt enable register 2 Interrupt select register 0 Interrupt select register 1 Interrupt select register 2 EP0i data register EP0o data register EP0s data register EP1 data register EP2 data register EP3 data register EP0o receive data size register EP1 receive data size register Data status register FIFO clear register Endpoint stall register Trigger register DTC transfer setting register Configuration value register Control register Endpoint information register Transceiver test register 0 Transceiver test register 1 Receive buffer register Transmitter holding register
Abbreviation IFR1 IFR2 IER0 IER1 IER2 ISR0 ISR1 ISR2 EPDR0i EPDR0o EPDR0s EPDR1 EPDR2 EPDR3 EPSZ0o EPSZ1 DASTS FCLR EPSTL TRG DMA CVR CTLR EPIR TRNTREG0 TRNTREG1 FRBR FTHR
Number of Bits Address 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'FA01 H'FA02 H'FA04 H'FA05 H'FA06 H'FA08 H'FA09 H'FA0A H'FA0C H'FA0D H'FA0E H'FA10 H'FA14 H'FA18 H'FA24 H'FA25 H'FA27 H'FA28 H'FA2A H'FA2C H'FA2D H'FA2E H'FA2F H'FA32 H'FA44 H'FA45 H'FC80 H'FC80
Module USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB SCIF SCIF
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Section 29 List of Registers Data Bus Width 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 Number of Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Register Name Divisor latch L Interrupt enable register Divisor latch H Interrupt identification register FIFO control register Line control register Modem control register Line status register Modem status register Scratch pad register SCIF control register SS control register H SS control register L SS mode register SS enable register SS status register SS control register 2 SS transmit data register 0 SS transmit data register 1 SS transmit data register 2 SS transmit data register 3 SS receive data register 0 SS receive data register 1 SS receive data register 2 SS receive data register 3 SS shift register Host interface control register 4 BT status register 0 BT status register 1
Abbreviation FDLL FIER FDLH FIIR FFCR FLCR FMCR FLSR FMSR FSCR SCIFCR SSCRH SSCRL SSMR SSER SSSR SSCR2 SSTDR0 SSTDR1 SSTDR2 SSTDR3 SSRDR0 SSRDR1 SSRDR2 SSRDR3 SSTRSR HICR4 BTSR0 BTSR1
Number of Bits Address 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'FC80 H'FC81 H'FC81 H'FC82 H'FC82 H'FC83 H'FC84 H'FC85 H'FC86 H'FC87 H'FC88 H'FCC0 H'FCC1 H'FCC2 H'FCC3 H'FCC4 H'FCC5 H'FCC6 H'FCC7 H'FCC8 H'FCC9 H'FCCA H'FCCB H'FCCC H'FCCD H'FCCE H'FD00 H'FD02 H'FD03
Module SCIF SCIF SCIF SCIF SCIF SCIF SCIF SCIF SCIF SCIF SCIF SSU SSU SSU SSU SSU SSU SSU SSU SSU SSU SSU SSU SSU SSU SSU LPC LPC LPC
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Section 29 List of Registers Data Bus Width 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 Number of Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Register Name BT control/status register 0 BT control/status register 1 BT control register BT interrupt mask register SMIC flag register Host interface control register 5 SMIC control/status register SMIC data register SMIC interrupt register 0 SMIC interrupt register 1 SERIRQ control register3 Bidirectional data register 0MW Bidirectional data register 0SW Bidirectional data register 1 Bidirectional data register 2 Bidirectional data register 3 Bidirectional data register 4 Bidirectional data register 5 Bidirectional data register 6 Bidirectional data register 7 Bidirectional data register 8 Bidirectional data register 9 Bidirectional data register 10 Bidirectional data register 11 Bidirectional data register 12 Bidirectional data register 13 Bidirectional data register 14 Bidirectional data register 15 Input data register 3
Abbreviation BTCSR0 BTCSR1 BTCR BTIMSR SMICFLG HICR5 SMICCSR SMICDTR SMICIR0 SMICIR1 SIRQCR3 TWR0MW TWR0SW TWR1 TWR2 TWR3 TWR4 TWR5 TWR6 TWR7 TWR8 TWR9 TWR10 TWR11 TWR12 TWR13 TWR14 TWR15 IDR3
Number of Bits Address 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'FD04 H'FD05 H'FD06 H'FD07 H'FD08 H'FD09 H'FD0A H'FD0B H'FD0C H'FD0E H'FD0F H'FD10 H'FD10 H'FD11 H'FD12 H'FD13 H'FD14 H'FD15 H'FD16 H'FD17 H'FD18 H'FD19 H'FD1A H'FD1B H'FD1C H'FD1D H'FD1E H'FD1F H'FD20
Module LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC
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Section 29 List of Registers Data Bus Width 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 8 8 Number of Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Register Name Output data register 3 Status register 3 SERIRQ control register 4 LPC channel 3 address register H LPC channel 3 address register L SERIRQ control register 0 SERIRQ control register 1 Input data register 1 Output data register 1 Status register 1 SERIRQ control register 5 Input data register 2 Output data register 2 Status register 2 Host interface select register Host interface control register 0 Host interface control register 1 Host interface control register 2 Host interface control register 3 SERIRQ control register2 BT data buffer BT FIFO valid size register 0 BT FIFO valid size register 1 LPC channel 1, 2 address register H LPC channel 1, 2 address register L SCIF address register H SCIF address register L Sub-chip module stop control register BH Sub-chip module stop control register BL
Abbreviation ODR3 STR3 SIRQCR4 LADR3H LADR3L SIRQCR0 SIRQCR1 IDR1 ODR1 STR1 SIRQCR5 IDR2 ODR2 STR2 HISEL HICR0 HICR1 HICR2 HICR3 SIRQCR2 BTDTR BTFVSR0 BTFVSR1 LADR12H LADR12L SCIFADRH SCIFADRL SUBMSTPBH SUBMSTPBL
Number of Bits Address 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'FD21 H'FD22 H'FD23 H'FD24 H'FD25 H'FD26 H'FD27 H'FD28 H'FD29 H'FD2A H'FD2B H'FD2C H'FD2D H'FD2E H'FD2F H'FD30 H'FD31 H'FD32 H'FD33 H'FD34 H'FD35 H'FD36 H'FD37 H'FD38 H'FD39 H'FD3A H'FD3B H'FE3E H'FE3F
Module LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC SYSTEM SYSTEM
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Section 29 List of Registers Data Bus Width 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Number of Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Register Name Event count status register Event count control register Module stop control register A Noise canceler enable register Noise canceler mode control register Noise canceler cycle setting register Port E output data register Port F output data register Port E input data register Port E data direction register Port F input data register Port F data direction register Port C output data register Port D output data register Port C input data register Port C data direction register Port D input data register Port D data direction register Flash code control/status register Flash program code select register Flash erase code select register Flash key code register Flash MAT select register Flash transfer destination address register I2C bus control register_4 I C bus status register_4 I C bus data register_4 Second slave address register_4
2 2
Abbreviation ECS ECCR MSTPCRA P3NCE P3NCMC NCCS PEODR PFODR PEPIN PEDDR PFPIN PFDDR PCODR PDODR PCPIN PCDDR PDPIN PDDDR FCCS FPCS FECS FKEY FMATS FTDAR ICCR_4 ICSR_4 ICDR_4 SARX_4
Number of Bits Address 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'FE40 H'FE42 H'FE43 H'FE44 H'FE45 H'FE46 H'FE48 H'FE49 H'FE4A H'FE4A H'FE4B H'FE4B H'FE4C H'FE4D H'FE4E H'FE4E H'FE4F H'FE4F H'FE88 H'FE89 H'FE8A H'FE8C H'FE8D H'FE8E H'FE90 H'FE91 H'FE92 H'FE92
Module EVC EVC SYSTEM PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT FLASH FLASH FLASH FLASH FLASH FLASH IIC_4 IIC_4 IIC_4 IIC_4
Rev. 2.00 Aug. 20, 2008 Page 1078 of 1198 REJ09B0403-0200
Section 29 List of Registers Data Bus Width 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 16 16 16 16 16 16 16 16 16 8 8 8 8 Number of Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Register Name I C bus mode register_4 Slave address register_4 I C bus control register_5 I C bus status register_5 I C bus data register_5 Second slave address register_5 I C bus mode register_5 Slave address register_5 Serial mode register_1 Bit rate register_1 Serial control register_1 Transmit data register_1 Serial status register_1 Receive data register_1 Smart card mode register_1 A/D data register A A/D data register B A/D data register C A/D data register D A/D data register E A/D data register F A/D data register G A/D data register H A/D control/status register A/D control register Serial multiplexed mode register 0 Serial multiplexed mode register 1 Noise canceler enable register Noise canceler mode control register
2 2 2 2 2
Abbreviation ICMR_4 SAR_4 ICCR_5 ICSR_5 ICDR_5 SARX_5 ICMR_5 SAR_5 SMR_1 BRR_1 SCR_1 TDR_1 SSR_1 RDR_1 SCMR_1 ADDRA ADDRB ADDRC ADDRD ADDRE ADDRF ADDRG ADDRH ADCSR ADCR SMR0 SMR1 P4BNCE P4BNCMC
Number of Bits Address 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 16 16 16 16 16 16 16 8 8 8 8 8 8 H'FE93 H'FE93 H'FE94 H'FE95 H'FE96 H'FE96 H'FE97 H'FE97 H'FE98 H'FE99 H'FE9A H'FE9B H'FE9C H'FE9D H'FE9E H'FEA0 H'FEA2 H'FEA4 H'FEA6 H'FEA8 H'FEAA H'FEAC H'FEAE H'FEB0 H'FEB1 H'FEB8 H'FEB9 H'FEBA H'FEBB
Module IIC_4 IIC_4 IIC_5 IIC_5 IIC_5 IIC_5 IIC_5 IIC_5 SCI_1 SCI_1 SCI_1 SCI_1 SCI_1 SCI_1 SCI_1 ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC SMX SMX PORT PORT
Rev. 2.00 Aug. 20, 2008 Page 1079 of 1198 REJ09B0403-0200
Section 29 List of Registers Data Bus Width 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Number of Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 4 2 4 4 2 2 2 2 2 2 2 2 2 2 2
Register Name Port 6 pull-up MOS control register Pin function control register Port 4 pull-up MOS control register I C bus control register_3 I C bus status register_3 I C bus data register_3 Second slave address register_3 I2C bus mode register_3 Slave address register_3 I C bus control register_2 I C bus status register_2 I C bus data register_2 Second slave address register_2 I C bus mode register_2 Slave address register_2 PWMX (D/A) data register A_1 PWMX (D/A) control register_1 PWMX (D/A) data register B_1 PWMX (D/A) counter_1 CRC control register CRC data input register CRC data output register I C bus extended control register_0 I2C bus extended control register_1 I C SMBus control register I C bus extended control register_2 I C bus extended control register_3 I C bus transfer select register I C bus extended control register_4 I C bus extended control register_5
2 2 2 2 2 2 2 2 2 2 2 2 2 2
Abbreviation P6PCR PINFNCR P4PCR ICCR_3 ICSR_3 ICDR_3 SARX_3 ICMR_3 SAR_3 ICCR_2 ICSR_2 ICDR_2 SARX_2 ICMR_2 SAR_2 DADRA_1 DACR_1 DADRB_1 DACNT_1 CRCCR CRCDIR CRCDOR ICXR_0 ICXR_1 ICSMBCR ICXR_2 ICXR_3 IICX3 ICXR_4 ICXR_5
Number of Bits Address 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 8 16 16 8 8 16 8 8 8 8 8 8 8 8 H'FEBC H'FEBE H'FEBF H'FEC0 H'FEC1 H'FEC2 H'FEC2 H'FEC3 H'FEC3 H'FEC8 H'FEC9 H'FECA H'FECA H'FECB H'FECB H'FECC H'FECC H'FECE H'FECE H'FED4 H'FED5 H'FED6 H'FED8 H'FED9 H'FEDB H'FEDC H'FEDD H'FEDF H'FEE0 H'FEE1
Module PORT PORT PORT IIC_3 IIC_3 IIC_3 IIC_3 IIC_3 IIC_3 IIC_2 IIC_2 IIC_2 IIC_2 IIC_2 IIC_2
PWMX_1 8 PWMX_1 8 PWMX_1 8 PWMX_1 8 CRC CRC CRC IIC_0 IIC_1 IIC IIC_2 IIC_3 IIC IIC_4 IIC_5 16 16 16 8 8 8 8 8 8 8 8
Rev. 2.00 Aug. 20, 2008 Page 1080 of 1198 REJ09B0403-0200
Section 29 List of Registers Data Bus Width 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Number of Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Register Name Keyboard comparator control register DTC enable register F Interrupt control register D Interrupt control register A Interrupt control register B Interrupt control register C IRQ status register IRQ sense control register H IRQ sense control register L DTC enable register A DTC enable register B DTC enable register C DTC enable register D DTC enable register E DTC vector register Address break control register Break address register A Break address register B Break address register C IRQ enable register 16 IRQ status register 16 IRQ sense control register 16H IRQ sense control register 16L IRQ sense port select register 16 IRQ sense port select register Port control register 0 Bus control register 2 Wait state control register 2 Peripheral clock select register
Abbreviation KBCOMP DTCERF ICRD ICRA ICRB ICRC ISR ISCRH ISCRL DTCERA DTCERB DTCERC DTCERD DTCERE DTVECR ABRKCR BARA BARB BARC IER16 ISR16 ISCR16H ISCR16L ISSR16 ISSR PTCNT0 BCR2 WSCR2 PCSR
Number of Bits Address 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'FEE4 H'FEE6 H'FEE7 H'FEE8 H'FEE9 H'FEEA H'FEEB H'FEEC H'FEED H'FEEE H'FEEF H'FEF0 H'FEF1 H'FEF2 H'FEF3 H'FEF4 H'FEF5 H'FEF6 H'FEF7 H'FEF8 H'FEF9 H'FEFA H'FEFB H'FEFC H'FEFD H'FEFE H'FF80 H'FF81 H'FF82
Module EVC DTC INT INT INT INT INT INT INT DTC DTC DTC DTC DTC DTC INT INT INT INT INT INT INT INT PORT PORT PORT BSC BSC PWMX
Rev. 2.00 Aug. 20, 2008 Page 1081 of 1198 REJ09B0403-0200
Section 29 List of Registers Data Bus Width 8 8 8 8 8 8 8 8 8 8 8 8 8 16 16 16 16 16 16 16 Number of Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 4 2 4 4 2 2 2 2
Register Name System control register 2 Standby control register Low power control register Module stop control register H Module stop control register L I C bus control register_1 I C bus status register _1 I2C bus data register _1 Second slave address register _1 I C bus mode register_1 Slave address register _1 Timer interrupt enable register Timer control/status register Free-running counter Output compare register A Output compare register B Timer control register
2 2 2
Abbreviation SYSCR2 SBYCR LPWRCR MSTPCRH MSTPCRL ICCR_1 ICSR_1 ICDR_1 SARX_1 ICMR_1 SAR_1 TIER TCSR FRC OCRA OCRB TCR
Number of Bits Address 8 8 8 8 8 8 8 8 8 8 8 8 8 16 16 16 8 8 16 16 16 8 16 16 8 16 8 16 H'FF83 H'FF84 H'FF85 H'FF86 H'FF87 H'FF88 H'FF89 H'FF8E H'FF8E H'FF8F H'FF8F H'FF90 H'FF91 H'FF92 H'FF94 H'FF94 H'FF96 H'FF97 H'FF98 H'FF9A H'FFA0 H'FFA0 H'FFA6 H'FFA6 H'FFA8 H'FFA8 H'FFA9 H'FFA8
Module SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM IIC_1 IIC_1 IIC_1 IIC_1 IIC_1 IIC_1 FRT FRT FRT FRT FRT FRT FRT FRT FRT
Timer output compare control register TOCR Output compare register AR Output compare register AF PWMX (D/A) data register A_0 PWMX (D/A) control register_0 PWMX (D/A) data register B_0 PWMX (D/A) counter_0 OCRAR OCRAF DADRA_0 DACR_0 DADRB_0 DACNT_0
PWMX_0 8 PWMX_0 8 PWMX_0 8 PWMX_0 8 WDT_0 WDT_0 WDT_0 WDT_0 16 16 16 16
Timer control/status register _0 (read) TCSR_0 Timer control/status register _0 (write) TCSR_0 Timer counter_0 (read) Timer counter_0 (write) TCNT_0 TCNT_0
Rev. 2.00 Aug. 20, 2008 Page 1082 of 1198 REJ09B0403-0200
Section 29 List of Registers Data Bus Width 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Number of Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Register Name Port A output data register Port A input data register Port A data direction register Port 1 pull-up MOS control register Port 2 pull-up MOS control register Port 3 pull-up MOS control register Port 1 data direction register Port 2 data direction register Port 1 data register Port 2 data register Port 3 data direction register Port 4 data direction register Port 3 data register Port 4 data register Port 5 data direction register Port 6 data direction register Port 5 data register Port 6 data register Port B output data register Port B input data register Port 8 data direction register Port 7 input data register Port B data direction register Port 8 data register Port 9 data direction register Port 9 data register Interrupt enable register Serial timer control register System control register Mode control register
Abbreviation PAODR PAPIN PADDR P1PCR P2PCR P3PCR P1DDR P2DDR P1DR P2DR P3DDR P4DDR P3DR P4DR P5DDR P6DDR P5DR P6DR PBODR PBPIN P8DDR P7PIN PBDDR P8DR P9DDR P9DR IER STCR SYSCR MDCR
Number of Bits Address 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'FFAA H'FFAB H'FFAB H'FFAC H'FFAD H'FFAE H'FFB0 H'FFB1 H'FFB2 H'FFB3 H'FFB4 H'FFB5 H'FFB6 H'FFB7 H'FFB8 H'FFB9 H'FFBA H'FFBB H'FFBC H'FFBD H'FFBD H'FFBE H'FFBE H'FFBF H'FFC0 H'FFC1 H'FFC2 H'FFC3 H'FFC4 H'FFC5
Module PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT INT SYSTEM SYSTEM SYSTEM
Rev. 2.00 Aug. 20, 2008 Page 1083 of 1198 REJ09B0403-0200
Section 29 List of Registers Data Bus Width 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 16 16 16 Number of Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Register Name Bus control register Wait state control register Timer control register_0 Timer control register_1 Timer control/status register_0 Timer control/status register_1 Time constant register A_0 Time constant register A_1 Time constant register B_0 Time constant register B_1 Timer counter_0 Timer counter_1 I C bus control register_0 I C bus status register_0 I C bus data register_0 Second slave address register_0 I2C bus mode register_0 Slave address register_0 Serial mode register_3 Bit rate register_3 Serial control register_3 Transmit data register_3 Serial status register_3 Receive data register_3 Smart card mode register_3
2 2 2
Abbreviation BCR WSCR TCR_0 TCR_1 TCSR_0 TCSR_1 TCORA_0 TCORA_1 TCORB_0 TCORB_1 TCNT_0 TCNT_1 ICCR_0 ICSR_0 ICDR_0 SARX_0 ICMR_0 SAR_0 SMR_3 BRR_3 SCR_3 TDR_3 SSR_3 RDR_3 SCMR_3
Number of Bits Address 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 8 16 H'FFC6 H'FFC7 H'FFC8 H'FFC9 H'FFCA H'FFCB H'FFCC H'FFCD H'FFCE H'FFCF H'FFD0 H'FFD1 H'FFD8 H'FFD9 H'FFDE H'FFDE H'FFDF H'FFDF H'FFE0 H'FFE1 H'FFE2 H'FFE3 H'FFE4 H'FFE5 H'FFE6 H'FFEA H'FFEA H'FFEB H'FFEA
Module BSC BSC TMR_0 TMR_1 TMR_0 TMR_1 TMR_0 TMR_1 TMR_0 TMR_1 TMR_0 TMR_1 IIC_0 IIC_0 IIC_0 IIC_0 IIC_0 IIC_0 SCI_3 SCI_3 SCI_3 SCI_3 SCI_3 SCI_3 SCI_3 WDT_1 WDT_1 WDT_1 WDT_1
Timer control/ status register_1 (read) TCSR_1 Timer control/ status register_1 (write) TCSR_1 Timer counter_1 (read) Timer counter_1 (write) TCNT_1 TCNT_1
Rev. 2.00 Aug. 20, 2008 Page 1084 of 1198 REJ09B0403-0200
Section 29 List of Registers Data Bus Width 8 8 8 8 8 8 8 8 8 8 8 Number of Access States 2 2 2 2 2 2 2 2 2 2 2
Register Name Timer control register_X Timer control/status register_X Timer counter_X Time constant register A_X Time constant register B_X Timer control register_Y Timer control/status register_Y Time constant register A_Y Time constant register B_Y Timer counter_Y Timer connection register S
Abbreviation TCR_X TCSR_X TCNT_X TCORA_X TCORB_X TCR_Y TCSR_Y TCORA_Y TCORB_Y TCNT_Y TCONRS
Number of Bits Address 8 8 8 8 8 8 8 8 8 8 8 H'FFF0 H'FFF1 H'FFF4 H'FFF6 H'FFF7 H'FFF0 H'FFF1 H'FFF2 H'FFF3 H'FFF4 H'FFFE
Module TMR_X TMR_X TMR_X TMR_X TMR_X TMR_Y TMR_Y TMR_Y TMR_Y TMR_Y TMR
Notes: 1. The registers related to USB are supported only by the H8S/2472 Group. 2. The registers related to PECI are supported only by the H8S/2472 Group and the H8S/2462 Group.
Rev. 2.00 Aug. 20, 2008 Page 1085 of 1198 REJ09B0403-0200
Section 29 List of Registers
29.2
Register Bits
Register addresses and bit names of the on-chip peripheral modules are described below. Each line covers eight bits, so 16-bit and 32-bit registers are shown as 2 lines and 4 lines, respectively.
Register Abbreviation ECMR Bit 7 ECSR ECSIPR PIR MAHR MA47 MA39 MA31 MA23 MALR MA15 MA7 Bit 6 RE MA46 MA38 MA30 MA22 MA14 MA6 Bit 5 TE MA45 MA37 MA29 MA21 MA13 MA5 Bit 4 PRCEF PSRTO PSRTOIP MA44 MA36 MA28 MA20 MA12 MA4 Bit 3 ZPF ILB MDI MA43 MA35 MA27 MA19 MA11 MA3 Bit 2 PFR ELB LCHNG LCHNGIP MDO MA42 MA34 MA26 MA18 MA10 MA2 Bit 1 RXF MPDE DM MPD MPDIP MMD MA41 MA33 MA25 MA17 MA9 MA1 Bit 0 TXF PRM ICD ICDIP MDC MA40 MA32 MA24 MA16 MA8 MA0 Module EtherC
Rev. 2.00 Aug. 20, 2008 Page 1086 of 1198 REJ09B0403-0200
Section 29 List of Registers
Register Abbreviation RFLR Bit 7 RFL7 PSR TROCR TROC31 TROC23 TROC15 TROC7 CDCR COSDC31 COSDC23 COSDC15 COSDC7 LCCR LCC31 LCC23 LCC15 LCC7 CNDCR CNDC31 CNDC23 CNDC15 CNDC7 CEFCR CEFC31 CEFC23 CEFC15 CEFC7 FRECR FREC31 FREC23 FREC15 FREC7 Bit 6 RFL6 TROC30 TROC22 TROC14 TROC6 COSDC30 COSDC22 COSDC14 COSDC6 LCC30 LCC22 LCC14 LCC6 CNDC30 CNDC22 CNDC14 CNDC6 CEFC30 CEFC22 CEFC14 CEFC6 FREC30 FREC22 FREC14 FREC6 Bit 5 RFL5 TROC29 TROC21 TROC13 TROC5 COSDC29 COSDC21 COSDC13 COSDC5 LCC29 LCC21 LCC13 LCC5 CNDC29 CNDC21 CNDC13 CNDC5 CEFC29 CEFC21 CEFC13 CEFC5 FREC29 FREC21 FREC13 FREC5 Bit 4 RFL4 TROC28 TROC20 TROC12 TROC4 COSDC28 COSDC20 COSDC12 COSDC4 LCC28 LCC20 LCC12 LCC4 CNDC28 CNDC20 CNDC12 CNDC4 CEFC28 CEFC20 CEFC12 CEFC4 FREC28 FREC20 FREC12 FREC4 Bit 3 RFL11 RFL3 TROC27 TROC19 TROC11 TROC3 COSDC27 COSDC19 COSDC11 COSDC3 LCC27 LCC19 LCC11 LCC3 CNDC27 CNDC19 CNDC11 CNDC3 CEFC27 CEFC19 CEFC11 CEFC3 FREC27 FREC19 FREC11 FREC3 Bit 2 RFL10 RFL2 TROC26 TROC18 TROC10 TROC2 COSDC26 COSDC18 COSDC10 COSDC2 LCC26 LCC18 LCC10 LCC2 CNDC26 CNDC18 CNDC10 CNDC2 CEFC26 CEFC18 CEFC10 CEFC2 FREC26 FREC18 FREC10 FREC2 Bit 1 RFL9 RFL1 TROC25 TROC17 TROC9 TROC1 COSDC25 COSDC17 COSDC9 COSDC1 LCC25 LCC17 LCC9 LCC1 CNDC25 CNDC17 CNDC9 CNDC1 CEFC25 CEFC17 CEFC9 CEFC1 FREC25 FREC17 FREC9 FREC1 Bit 0 RFL8 RFL0 LMON TROC24 TROC16 TROC8 TROC0 COSDC24 COSDC16 COSDC8 COSDC0 LCC24 LCC16 LCC8 LCC0 CNDC24 CNDC16 CNDC8 CNDC0 CEFC24 CEFC16 CEFC8 CEFC0 FREC24 FREC16 FREC8 FREC0 Module EtherC
Rev. 2.00 Aug. 20, 2008 Page 1087 of 1198 REJ09B0403-0200
Section 29 List of Registers
Register Abbreviation TSFRCR Bit 7 TSFC31 TSFC23 TSFC15 TSFC7 TLFRCR TLFC31 TLFC23 TLFC15 TLFC7 RFCR RFC31 RFC23 RFC15 RFC7 MAFCR MAFC31 MAFC23 MAFC15 MAFC7 IPGR APR AP15 AP7 MPR MP15 MP7 TPAUSER TPAUSE15 TPAUSE7 Bit 6 TSFC30 TSFC22 TSFC14 TSFC6 TLFC30 TLFC22 TLFC14 TLFC6 RFC30 RFC22 RFC14 RFC6 MAFC30 MAFC22 MAFC14 MAFC6 AP14 AP6 MP14 MP6 TPAUSE14 TPAUSE6 Bit 5 TSFC29 TSFC21 TSFC13 TSFC5 TLFC29 TLFC21 TLFC13 TLFC5 RFC29 RFC21 RFC13 RFC5 MAFC29 MAFC21 MAFC13 MAFC5 AP13 AP5 MP13 MP5 TPAUSE13 TPAUSE5 Bit 4 TSFC28 TSFC20 TSFC12 TSFC4 TLFC28 TLFC20 TLFC12 TLFC4 RFC28 RFC20 RFC12 RFC4 MAFC28 MAFC20 MAFC12 MAFC4 IPG4 AP12 AP4 MP12 MP4 TPAUSE12 TPAUSE4 Bit 3 TSFC27 TSFC19 TSFC11 TSFC3 TLFC27 TLFC19 TLFC11 TLFC3 RFC27 RFC19 RFC11 RFC3 MAFC27 MAFC19 MAFC11 MAFC3 IPG3 AP11 AP3 MP11 MP3 TPAUSE11 TPAUSE3 Bit 2 TSFC26 TSFC18 TSFC10 TSFC2 TLFC26 TLFC18 TLFC10 TLFC2 RFC26 RFC18 RFC10 RFC2 MAFC26 MAFC18 MAFC10 MAFC2 IPG2 AP10 AP2 MP10 MP2 TPAUSE10 TPAUSE2 Bit 1 TSFC25 TSFC17 TSFC9 TSFC1 TLFC25 TLFC17 TLFC9 TLFC1 RFC25 RFC17 RFC9 RFC1 MAFC25 MAFC17 MAFC9 MAFC1 IPG1 AP9 AP1 MP9 MP1 TPAUSE9 TPAUSE1 Bit 0 TSFC24 TSFC16 TSFC8 TSFC0 TLFC24 TLFC16 TLFC8 TLFC0 RFC24 RFC16 RFC8 RFC0 MAFC24 MAFC16 MAFC8 MAFC0 IPG0 AP8 AP0 MP8 MP0 TPAUSE8 TPAUSE0 Module EtherC
Rev. 2.00 Aug. 20, 2008 Page 1088 of 1198 REJ09B0403-0200
Section 29 List of Registers
Register Abbreviation EDMR Bit 7 EDTRR EDRRR TDLAR TDLA31 TDLA23 TDLA15 TDLA7 RDLAR RDLA31 RDLA23 RDLA15 RDLA7 EESR ADE RMAF EESIPR ADEIP RMAFIP TRSCER RMAFCE Bit 6 DE TDLA30 TDLA22 TDLA14 TDLA6 RDLA30 RDLA22 RDLA14 RDLA6 TWB ECI TWBIP ECIIP Bit 5 DL1 TDLA29 TDLA21 TDLA13 TDLA5 RDLA29 RDLA21 RDLA13 RDLA5 TC TCIP Bit 4 DL0 TDLA28 TDLA20 TDLA12 TDLA4 RDLA28 RDLA20 RDLA12 RDLA4 TDE RRF TDEIP RRFIP RRFCE Bit 3 TDLA27 TDLA19 TDLA11 TDLA3 RDLA27 RDLA19 RDLA11 RDLA3 TFUF CND RTLF TFUFIP CNDIP RTLFIP Bit 2 TDLA26 TDLA18 TDLA10 TDLA2 RDLA26 RDLA18 RDLA10 RDLA2 TABT FR DLC RTSF TABTIP FRIP DLCIP RTSFIP Bit 1 TDLA25 TDLA17 TDLA9 TDLA1 RDLA25 RDLA17 RDLA9 RDLA1 RABT RDE CD PRE RABTIP RDEIP CDIP PREIP Bit 0 SWR TR RR TDLA24 TDLA16 TDLA8 TDLA0 RDLA24 RDLA16 RDLA8 RDLA0 RFCOF RFOF TRO CERF RFCOFIP RFOFIP TROIP CERFIP Module E-DMAC
Rev. 2.00 Aug. 20, 2008 Page 1089 of 1198 REJ09B0403-0200
Section 29 List of Registers
Register Abbreviation RMFCR Bit 7 MFC15 MFC7 TFTR TFT7 FDR RMCR FCFTR TRIMD RBWAR RBWA31 RBWA23 RBWA15 RBWA7 RDFAR RDFA31 RDFA23 RDFA15 RDFA7 Bit 6 MFC14 MFC6 TFT6 RBWA30 RBWA22 RBWA14 RBWA6 RDFA30 RDFA22 RDFA14 RDFA6 Bit 5 MFC13 MFC5 TFT5 RBWA29 RBWA21 RBWA13 RBWA5 RDFA29 RDFA21 RDFA13 RDFA5 Bit 4 MFC12 MFC4 TFT4 RBWA28 RBWA20 RBWA12 RBWA4 RDFA28 RDFA20 RDFA12 RDFA4 Bit 3 MFC11 MFC3 TFT3 RBWA27 RBWA19 RBWA11 RBWA3 RDFA27 RDFA19 RDFA11 RDFA3 Bit 2 MFC10 MFC2 TFT10 TFT2 TFD2 RFD2 RFF2 RFD2 RBWA26 RBWA18 RBWA10 RBWA2 RDFA26 RDFA18 RDFA10 RDFA2 Bit 1 MFC9 MFC1 TFT9 TFT1 TFD1 RFD1 RFF1 RFD1 RBWA25 RBWA17 RBWA9 RBWA1 RDFA25 RDFA17 RDFA9 RDFA1 Bit 0 MFC8 MFC0 TFT8 TFT0 TFD0 RFD0 RNC RFF0 RFD0 TIS RBWA24 RBWA16 RBWA8 RBWA0 RDFA24 RDFA16 RDFA8 RDFA0 Module E-DMAC
Rev. 2.00 Aug. 20, 2008 Page 1090 of 1198 REJ09B0403-0200
Section 29 List of Registers
Register Abbreviation TBRAR Bit 7 TBRA31 TBRA23 TBRA15 TBRA7 TDFAR TDFA31 TDFA23 TDFA15 TDFA7 ECBRR IFR0 IFR1 IFR2 IER0 IER1 IER2 ISR0 ISR1 ISR2 EPDR0i EPDR0o EPDR0s EPDR1 EPDR2 EPDR3 EPSZ0o EPSZ1 DASTS FCLR EPSTL TRG DMA CVR BRST BRST BRST SSRSME D7 D7 D7 D7 D7 D7 CNFV1 Bit 6 TBRA30 TBRA22 TBRA14 TBRA6 TDFA30 TDFA22 TDFA14 TDFA6 EP1FULL EP1FULL EP1FULL D6 D6 D6 D6 D6 D6 EP3CLR EP3KTE CNFV0 Bit 5 TBRA29 TBRA21 TBRA13 TBRA5 TDFA29 TDFA21 TDFA13 TDFA5 EP2TR SURSS EP2TR EP2TR D5 D5 D5 D5 D5 D5 EP3DE EP1CLR EP1RDFN INTV1 Bit 4 TBRA28 TBRA20 TBRA12 TBRA4 TDFA28 TDFA20 TDFA12 TDFA4 EP2EMPTY SURSF EP2EMPTY SURSE EP2EMPTY SURSE D4 D4 D4 D4 D4 D4 EP2DE EP2CLR EP2PKTE INTV0 Bit 3 TBRA27 TBRA19 TBRA11 TBRA3 TDFA27 TDFA19 TDFA11 TDFA3 SETUPTS VBUSMN CFDN SETUPTS CFDN SETUPTS CFDN D3 D3 D3 D3 D3 D3 EP3STL Bit 2 TBRA26 TBRA18 TBRA10 TBRA2 TDFA26 TDFA18 TDFA10 TDFA2 EP0oTS EP3TR EP0oTS EP3TR EP0oTS EP3TR D2 D2 D2 D2 D2 D2 EP2STL EP0sRDFN PULLUP_E ALTV2 Bit 1 TBRA25 TBRA17 TBRA9 TBRA1 TDFA25 TDFA17 TDFA9 TDFA1 EP0iTR EP3TS SETC EP0iTR EP3TS SETCE EP0iTR EP3TS SETCE D1 D1 D1 D1 D1 D1 EP1STL EP0oRDFN EP2DMAE ALTV1 Bit 0 TBRA24 TBRA16 TBRA8 TBRA0 TDFA24 TDFA16 TDFA8 TDFA0 RTM EP0iTS VBUSF SETI EP0iTS VBUSF SETIE EP0iTS VBUSF SETIE D0 D0 D0 D0 D0 D0 EP0iDE EP0iCLR EP0STL EP0iPKTE EP1DMAE ALTV0 USB Module E-DMAC
Rev. 2.00 Aug. 20, 2008 Page 1091 of 1198 REJ09B0403-0200
Section 29 List of Registers
Register Abbreviation CTLR EPIR TRNTREG0 TRNTREG1 FRBR FTHR FDLL FIER FDLH FIIR FFCR FLCR FMCR FLSR FMSR FSCR SCIFCR SSCRH SSCRL SSMR SSER SSSR SSCR2 SSTDR0 SSTDR1 SSTDR2 SSTDR3 SSRDR0 Bit 7 D7 PTSTE bit 7 bit 7 bit 7 bit 7 FIFOE1 Bit 6 D6 bit 6 bit 6 bit 6 bit 6 FIFOE0 Bit 5 D5 bit 5 bit 5 bit 5 bit 5 Bit 4 RWUPS D4 bit 4 bit 4 bit 4 bit 4 EPS LOOPBACK BI CTS bit 4 OUT2LOOP SOL TENDSTS bit4 bit4 bit4 bit4 bit4 Bit 3 RSME D3 SUSPEND bit 3 bit 3 bit 3 EDSSI bit 3 INTID2 DMAMODE PEN OUT2 FE DDCD bit 3 CKSEL1 SOLP TEIE TEND SCSATS bit3 bit3 bit3 bit3 bit3 Bit 2 D2 txenl xver_data bit 2 bit 2 bit 2 ELSI bit 2 INTID1 XMITFRST STOP OUT1 PE TERI bit 2 CKSEL0 SCKS CKS2 TIE TDRE SSODTS bit2 bit2 bit2 bit2 bit2 Bit 1 ASCE D1 Txse0 dpls bit 1 bit 1 bit 1 ETBEI bit 1 INTID0 RCVRFRST CLS1 RTS OE DDSR bit 1 SCIFRST CSS1 DATS1 CKS1 RIE RDRF bit1 bit1 bit1 bit1 bit1 Bit 0 D0 Txdata dmns bit 0 bit 0 bit 0 ERBFI bit 0 INTPEND FIFOE CLS0 DTR DR DCTS bit 0 REGRST CSS0 DATS0 CKS0 CEIE CE bit0 bit0 bit0 bit0 bit0 SSU SCIF Module USB
RCVRTRIG1 RCVRTRIG0 DLAB BREAK
STICKPARITY
THRE DSR bit 5 SRES CPHS SCSOS bit5 bit5 bit5 bit5 bit5
RXFIFOERR TEMT DCD bit 7 SCIFOE1 MSS MLS TE SDOS bit7 bit7 bit7 bit7 bit7 RI bit 6 SCIFOE0 BIDE SSUMS CPOS RE ORER SSCKOS bit6 bit6 bit6 bit6 bit6
Rev. 2.00 Aug. 20, 2008 Page 1092 of 1198 REJ09B0403-0200
Section 29 List of Registers
Register Abbreviation SSRDR1 SSRDR2 SSRDR3 SSTRSR HICR4 BTSR0 BTSR1 BTCSR0 BTCSR1 BTCR Bit 7 bit7 bit7 bit7 bit7 LADR12SEL RSTRENBL B_BUSY Bit 6 bit6 bit6 bit6 bit6 HRSTI FSEL1 HRSTIE H_BUSY Bit 5 bit5 bit5 bit5 bit5 IRQCRI FSEL0 IRQCRIE OEM0 Bit 4 bit4 bit4 bit4 bit4 FRDI BEVTI FRDIE BEVTIE BEVT_ATN Bit 3 bit3 bit3 bit3 bit3 SWENBL HRDI B2HI HRDIE B2HIE B2H_ATN Bit 2 bit2 bit2 bit2 bit2 KCSENBL HWRI H2BI HWRIE H2BIE H2B_ATN Bit 1 bit1 bit1 bit1 bit1 SMCENBL HBTWI CRRPI HBTWIE CRRPIE CLR_RD_ PTR BTIMSR BMC_ HWRST SMICFLG RX_DATA_ RDY HICR5 SMICCSR SMICDTR SMICIR0 SMICIR1 SIRQCR3 TWR0MW TWR0SW TWR1 TWR2 TWR3 TWR4 TWR5 TWR6 TWR7 bit 7 bit 7 bit 7 bit 7 bit 7 bit 7 bit 7 bit 7 bit 7 bit 7 bit 7 TX_DATA_ RDY bit 6 bit 6 bit 6 bit 6 bit 6 bit 6 bit 6 bit 6 bit 6 bit 6 bit 6 bit 5 bit 5 bit 5 bit 5 bit 5 bit 5 bit 5 bit 5 bit 5 bit 5 bit 5 bit 4 bit 4 HDTWI HDTWIE bit 4 bit 4 bit 4 bit 4 bit 4 bit 4 bit 4 bit 4 bit 4 bit 3 bit 3 HDTRI HDTRIE SCSIRQ3 bit 3 bit 3 bit 3 bit 3 bit 3 bit 3 bit 3 bit 3 bit 3 bit 2 bit 2 STARI STARIE SCSIRQ2 bit 2 bit 2 bit 2 bit 2 bit 2 bit 2 bit 2 bit 2 bit 2 SCIFE bit 1 bit 1 CTLWI CTLWIE SCSIRQ1 bit 1 bit 1 bit 1 bit 1 bit 1 bit 1 bit 1 bit 1 bit 1 bit 0 bit 0 BUSYI BUSYIE SCSIRQ0 bit 0 bit 0 bit 0 bit 0 bit 0 bit 0 bit 0 bit 0 bit 0 SMI SEVT_ATN SMS_ATN OEM3 OEM2 OEM1 B2H_IRQ Bit 0 bit0 bit0 bit0 bit0 BTENBL HBTRI CRWPI HBTRIE CRWPIE CLR_WR_ PTR B2H_IRQ_ EN BUSY LPC Module SSU
Rev. 2.00 Aug. 20, 2008 Page 1093 of 1198 REJ09B0403-0200
Section 29 List of Registers
Register Abbreviation TWR8 TWR9 TWR10 TWR11 TWR12 TWR13 TWR14 TWR15 IDR3 ODR3 STR3*1 STR3*
2
Bit 7 bit 7 bit 7 bit 7 bit 7 bit 7 bit 7 bit 7 bit 7 bit 7 bit 7 IBF3B DBU37 IRQ15E bit 15 bit 7 Q/C IRQ11E3 bit 7 bit 7 DBU17 SELIRQ15 bit 7 bit 7 DBU27 SELSTR3 LPC3E LPCBSY GA20 LFRAME
Bit 6 bit 6 bit 6 bit 6 bit 6 bit 6 bit 6 bit 6 bit 6 bit 6 bit 6 OBF3B DBU36 IRQ14E bit 14 bit 6 SELREQ IRQ10E3 bit 6 bit 6 DBU16 SELIRQ14 bit 6 bit 6 DBU26 SELIRQ11 LPC2E CLKREQ LRST CLKRUN
Bit 5 bit 5 bit 5 bit 5 bit 5 bit 5 bit 5 bit 5 bit 5 bit 5 bit 5 MWMF DBU35 IRQ13E bit 13 bit 5 IEDIR2 IRQ9E3 bit 5 bit 5 DBU15 SELIRQ13 bit 5 bit 5 DBU25 SELIRQ10 LPC1E IRQBSY SDWN SERIRQ
Bit 4 bit 4 bit 4 bit 4 bit 4 bit 4 bit 4 bit 4 bit 4 bit 4 bit 4 SWMF DBU34 IRQ8E bit 12 bit 4 SMIE3B IRQ6E3 bit 4 bit 4 DBU14 SELIRQ8 bit 4 bit 4 DBU24 SELIRQ9 FGA20E LRSTB ABRT LRESET
Bit 3 bit 3 bit 3 bit 3 bit 3 bit 3 bit 3 bit 3 bit 3 bit 3 bit 3 C/D3 C/D3 IRQ7E bit 11 bit 3 SMIE3A IRQ11E2 bit 3 bit 3 C/D1 SELIRQ7 bit 3 bit 3 C/D2 SELIRQ6 SDWNE SDWNB IBFIE3 LPCPD
Bit 2 bit 2 bit 2 bit 2 bit 2 bit 2 bit 2 bit 2 bit 2 bit 2 bit 2 DBU32 DBU32 IRQ5E bit 10 SMIE2 IRQ10E2 bit 2 bit 2 DBU12 SELIRQ5 bit 2 bit 2 DBU22 SELSMI PMEE PMEB IBFIE2 PME
Bit 1 bit 1 bit 1 bit 1 bit 1 bit 1 bit 1 bit 1 bit 1 bit 1 bit 1 IBF3A IBF3A IRQ4E bit 9 bit 1 IRQ12E1 IRQ9E2 bit 1 bit 1 IBF1 SELIRQ4 bit 1 bit 1 IBF2 SELIRQ12 LSMIE LSMIB IBFIE1 LSMI
Bit 0 bit 0 bit 0 bit 0 bit 0 bit 0 bit 0 bit 0 bit 0 bit 0 bit 0 OBF3A OBF3A IRQ3E bit 8 TWRE IRQ1E1 IRQ6E2 bit 0 bit 0 OBF1 SELIRQ3 bit 0 bit 0 OBF2 SELIRQ1 LSCIE LSCIB ERRIE LSCI
Module LPC
SIRQCR4 LADR3H LADR3L SIRQCR0 SIRQCR1 IDR1 ODR1 STR1 SIRQCR5 IDR2 ODR2 STR2 HISEL HICR0 HICR1 HICR2 HICR3
Rev. 2.00 Aug. 20, 2008 Page 1094 of 1198 REJ09B0403-0200
Section 29 List of Registers
Register Abbreviation SIRQCR2 BTDTR BTFVSR0 BTFVSR1 LADR12H LADR12L SCIFADRH SCIFADRL SUBMSTPBH SUBMSTPBL ECS Bit 7 IEDIR3 bit 7 N7 N7 bit 15 bit 7 bit 15 bit 7 SMSTPB15 SMSTPB7 E15 E7 ECCR MSTPCRA P3NCE P3NCMC NCCS PEODR PFODR PEPIN PEDDR PFPIN PFDDR PCODR PDODR PCPIN PCDDR PDPIN PDDDR EDSB MSTPA7 P37NCE P37NCMC PE7ODR PE7PIN PE7DDR PC7ODR PD7ODR PC7PIN PC7DDR PD7PIN PD7DDR Bit 6 bit 6 N6 N6 bit 14 bit 6 bit 14 bit 6 SMSTPB14 SMSTPB6 E14 E6 MSTPA6 P36NCE P36NCMC PE6ODR PF6ODR PE6PIN PE6DDR PF6PIN PF6DDR PC6ODR PD6ODR PC6PIN PC6DDR PD6PIN PD6DDR Bit 5 bit 5 N5 N5 bit 13 bit 5 bit 13 bit 5 SMSTPB13 SMSTPB5 E13 E5 MSTPA5 P35NCE P35NCMC PE5ODR PF5ODR PE5PIN PE5DDR PF5PIN PF5DDR PC5ODR PD5ODR PC5PIN PC5DDR PD5PIN PD5DDR Bit 4 bit 4 N4 N4 bit 12 bit 4 bit 12 bit 4 SMSTPB12 PECI E12 E4 MSTPA4 P34NCE P34NCMC PE4ODR PF4ODR PE4PIN PE4DDR PF4PIN PF4DDR PC4ODR PD4ODR PC4PIN PC4DDR PD4PIN PD4DDR Bit 3 bit 3 N3 N3 bit 11 bit 3 bit 11 bit 3 SMSTPB11 SCIF E11 E3 ECSB3 MSTPA3 P33NCE P33NCMC PE3ODR PF3ODR PE3PIN PE3DDR PF3PIN PF3DDR PC3ODR PD3ODR PC3PIN PC3DDR PD3PIN PD3DDR Bit 2 bit 2 N2 N2 bit 10 bit 10 SMSTPB10 SMSTPB2 E10 E2 ECSB2 MSTPA2 P32NCE P32NCMC NCCK2 PE2ODR PF2ODR PE2PIN PE2DDR PF2PIN PF2DDR PC2ODR PD2ODR PC2PIN PC2DDR PD2PIN PD2DDR Bit 1 bit 1 N1 N1 bit 9 bit 1 bit 9 SMSTPB9 LPC E9 E1 ECSB1 MSTPA1 P31NCE P31NCMC NCCK1 PE1ODR PF1ODR PE1PIN PE1DDR PF1PIN PF1DDR PC1ODR PD1ODR PC1PIN PC1DDR PD1PIN PD1DDR Bit 0 bit 0 N0 N0 bit 8 bit 0 bit 8 SMSTPB8 SMSTPB0 E8 E0 ECSB0 MSTPA0 P30NCE P30NCMC NCCK0 PE0ODR PF0ODR PE0PIN PE0DDR PF0PIN PF0DDR PC0ODR PD0ODR PC0PIN PC0DDR PD0PIN PD0DDR MSTPA0 PORT EVC
SYSTEM
Module LPC
Rev. 2.00 Aug. 20, 2008 Page 1095 of 1198 REJ09B0403-0200
Section 29 List of Registers
Register Abbreviation FCCS FPCS FECS FKEY FMATS FTDAR ICCR_4 ICSR_4 ICDR_4 SARX_4 ICMR_4 SAR_4 ICCR_5 ICSR_5 ICDR_5 SARX_5 ICMR_5 SAR_5 SMR_1*3 Bit 7 FWE K7 MS7 TDER ICE ESTP bit 7 SVAX6 MLS SVA6 ICE ESTP bit 7 SVAX6 MLS SVA6 C/A (GM) bit 7 TIE bit 7
3
Bit 6 K6 MS6 TDA6 IEIC STOP bit 6 SVAX5 WAIT SVA5 IEIC STOP bit 6 SVAX5 WAIT SVA5 CHR (BLK) bit 6 RIE bit 6 RDRF (RDRF) bit 6
Bit 5 K5 MS5 TDA5 MST IRTR bit 5 SVAX4 CKS2 SVA4 MST IRTR bit 5 SVAX4 CKS2 SVA4 PE (PE) bit 5 TE bit 5 ORER (ORER) bit 5
Bit 4 FLER K4 MS4 TDA4 TRS AASX bit 4 SVAX3 CKS1 SVA3 TRS AASX bit 4 SVAX3 CKS1 SVA3 O/E (O/E) bit 4 RE bit 4 FER (ERS) bit 4
Bit 3 WEINTE K3 MS3 TDA3 ACKE AL bit 3 SVAX2 CKS0 SVA2 ACKE AL bit 3 SVAX2 CKS0 SVA2 STOP (BCP1) bit 3 MPIE bit 3 PER (PER) bit 3 SDIR
Bit 2 K2 MS2 TDA2 BBSY AAS bit 2 SVAX1 BC2 SVA1 BBSY AAS bit 2 SVAX1 BC2 SVA1 MP (BCP0) bit 2 TEIE bit 2 TEND (TEND) bit 2 SINV
Bit 1 K1 MS1 TDA1 IRIC ADZ bit 1 SVAX0 BC1 SVA0 IRIC ADZ bit 1 SVAX0 BC1 SVA0 CKS1 (CKS1) bit 1 CKE1 bit 1 MPB (MPB) bit 1
Bit 0 SCO PPVS EPVB K0 MS0 TDA0 SCP ACKB bit 0 FSX BC0 FS SCP ACKB bit 0 FSX BC0 FS CKS0 (CKS0) bit 0 CKE0 bit 0 MPBT (MPBT) bit 0 SMIF
Module FLASH
IIC_4
IIC_5
SCI_1
BRR_1 SCR_1 TDR_1 SSR_1*
TDRE (TDRE)
RDR_1 SCMR_1
bit 7
Rev. 2.00 Aug. 20, 2008 Page 1096 of 1198 REJ09B0403-0200
Section 29 List of Registers
Register Abbreviation ADDRA Bit 7 AD9 AD1 ADDRB AD9 AD1 ADDRC AD9 AD1 ADDRD AD9 AD1 ADDRE AD9 AD1 ADDRF AD9 AD1 ADDRG AD9 AD1 ADDRH AD9 AD1 ADCSR ADCR SMR0 SMR1 P4BNCE P4BNCMC P6PCR PINFNCR ADF TRGS1 DCD1 CTS1 P47NCE P47NCMC P67PCR Bit 6 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 ADIE TRGS0 RI1 DTR1 P46NCE P46NCMC P66PCR Bit 5 AD7 AD7 AD7 AD7 AD7 AD7 AD7 AD7 ADST SCANE DSR1 RTS1 P45NCE P45NCMC P65PCR Bit 4 AD6 AD6 AD6 AD6 AD6 AD6 AD6 AD6 SCANS SME CTS3 P44NCE P44NCMC P64PCR Bit 3 AD5 AD5 AD5 AD5 AD5 AD5 AD5 AD5 CKS1 PB3NCE PB3NCMC P63PCR Bit 2 AD4 AD4 AD4 AD4 AD4 AD4 AD4 AD4 CH2 CKS0 SM2 RTS3 PB2NCE PB2NCMC P62PCR SERIRQ OFF P4PCR ICCR_3 ICSR_3 ICDR_3 SARX_3 P47PCR ICE ESTP bit 7 SVAX6 P46PCR IEIC STOP bit 6 SVAX5 P45PCR MST IRTR bit 5 SVAX4 P44PCR TRS AASX bit 4 SVAX3 P43PCR ACKE AL bit 3 SVAX2 P42PCR BBSY AAS bit 2 SVAX1 Bit 1 AD3 AD3 AD3 AD3 AD3 AD3 AD3 AD3 CH1 ADSTCLR SM1 PB1NCE PB1NCMC P61PCR LPCPD OFF P41PCR IRIC ADZ bit 1 SVAX0 Bit 0 AD2 AD2 AD2 AD2 AD2 AD2 AD2 AD2 CH0 EXTRGS SM0 PB0NCE PB0NCMC P60PCR CLKRUN OFF P40PCR SCP ACKB bit 0 FSX IIC_3 PORT SMX Module ADC
Rev. 2.00 Aug. 20, 2008 Page 1097 of 1198 REJ09B0403-0200
Section 29 List of Registers
Register Abbreviation ICMR_3 SAR_3 ICCR_2 ICSR_2 ICDR_2 SARX_2 ICMR_2 SAR_2 DADRA_1 Bit 7 MLS SVA6 ICE ESTP bit 7 SVAX6 MLS SVA6 DA13 DA5 DACR_1 DADRB_1 DA13 DA5 DACNT_1 UC7 UC8 CRCCR CRCDIR CRCDOR DORCLR bit 7 bit 15 bit 7 ICXR_0 ICXR_1 ICSMBCR ICXR_2 ICXR_3 IICX3 ICXR_4 ICXR_5 KBCOMP DTCERF STOPIM STOPIM SMB5E STOPIM STOPIM STOPIM STOPIM EVENTE DTCEF7 Bit 6 WAIT SVA5 IEIC STOP bit 6 SVAX5 WAIT SVA5 DA12 DA4 PWME DA12 DA4 UC6 UC9 bit 6 bit 14 bit 6 HNDS HNDS SMB4E HNDS HNDS HNDS HNDS DTCEF6 Bit 5 CKS2 SVA4 MST IRTR bit 5 SVAX4 CKS2 SVA4 DA11 DA3 DA11 DA3 UC5 UC10 bit 5 bit 13 bit 5 ICDRF ICDRF SMB3E ICDRF ICDRF ICDRF ICDRF Bit 4 CKS1 SVA3 TRS AASX bit 4 SVAX3 CKS1 SVA3 DA10 DA2 DA10 DA2 UC4 UC11 bit 4 bit 12 bit 4 ICDRE ICDRE SMB2E ICDRE ICDRE ICDRE ICDRE Bit 3 CKS0 SVA2 ACKE AL bit 3 SVAX2 CKS0 SVA2 DA9 DA1 OEB DA9 DA1 UC3 UC12 bit 3 bit 11 bit 3 ALIE ALIE SMB1E ALIE ALIE TCSS ALIE ALIE Bit 2 BC2 SVA1 BBSY AAS bit 2 SVAX1 BC2 SVA1 DA8 DA0 OEA DA8 DA0 UC2 UC13 LMS bit 2 bit 10 bit 2 ALSL ALSL SMB0E ALSL ALSL IICX5 ALSL ALSL Bit 1 BC1 SVA0 IRIC ADZ bit 1 SVAX0 BC1 SVA0 DA7 CFS OS DA7 CFS UC1 G1 bit 1 bit 9 bit 1 FNC1 FNC1 FSEL1 FNC1 FNC1 IICX4 FNC1 FNC1 Bit 0 BC0 FS SCP ACKB bit 0 FSX BC0 FS DA6 CKS DA6 REGS UC0 REGS G0 bit 0 bit 8 bit 0 FNC0 FNC0 FSEL0 FNC0 FNC0 IICX3 FNC0 FNC0 IIC_0 IIC_1 IIC IIC_2 IIC_3 IIC IIC_4 IIC_5 EVC DTC CRC
PWMX_1
Module IIC_3
IIC_2
Rev. 2.00 Aug. 20, 2008 Page 1098 of 1198 REJ09B0403-0200
Section 29 List of Registers
Register Abbreviation ICRD ICRA ICRB ICRC ISR ISCRH ISCRL DTCERA DTCERB DTCERC DTCERD DTCERE DTVECR ABRKCR BARA BARB BARC IER16 ISR16 ISCR16H ISCR16L ISSR16 ISSR PTCNT0 BCR2 WSCR2 PCSR SYSCR2 SBYCR LPWRCR MSTPCRH Bit 7 ICRD7 ICRA7 ICRB7 ICRC7 IRQ7F IRQ7SCB IRQ3SCB DTCEA7 DTCED7 SWDTE CMF A23 A15 A7 IRQ15E IRQ15F IRQ15SCB IRQ11SCB ISS15 ISS7 SCPFSEL1 WM10 PWCKX1B SSBY MSTP15 Bit 6 ICRD6 ICRA6 ICRB6 ICRC6 IRQ6F IRQ7SCA IRQ3SCA DTCEA6 DTCEB6 DTVEC6 A22 A14 A6 IRQ14E IRQ14F IRQ15SCA IRQ11SCA ISS14 ISS6 SCPFSEL3 WC11 PWCKX1A STS2 MSTP14 Bit 5 ICRD5 ICRA5 ICRC5 IRQ5F IRQ6SCB IRQ2SCB DTCEA5 DTCEB5 DTVEC5 A21 A13 A5 IRQ13E IRQ13F IRQ14SCB IRQ10SCB ISS13 ISS5 WC10 PWCKX0B STS1 NESEL MSTP13 Bit 4 ICRA4 ICRB4 ICRC4 IRQ4F IRQ6SCA IRQ2SCA DTCEA4 DTCEC4 DTCED4 DTVEC4 A20 A12 A4 IRQ12E IRQ12F IRQ14SCA IRQ10SCA ISS12 ISS4 PWCKX0A STS0 EXCLE MSTP12 Bit 3 ICRA3 ICRB3 ICRC3 IRQ3F IRQ5SCB IRQ1SCB DTCEA3 DTCED3 DTCEE3 DTVEC3 A19 A11 A3 IRQ11E IRQ11F IRQ13SCB IRQ9SCB ISS11 ISS3 PWMXS ADFULLE PWCKX1C ADMXE DTSPEED MSTP11 Bit 2 ICRD2 ICRA2 ICRB2 ICRC2 IRQ2F IRQ5SCA IRQ1SCA DTCEC2 DTCEE2 DTVEC2 A18 A10 A2 IRQ10E IRQ10F IRQ13SCA IRQ9SCA ISS10 ISS2 EXCKS SCK2 PNCCS MSTP10 Bit 1 ICRD1 ICRA1 ICRB1 ICRC1 IRQ1F IRQ4SCB IRQ0SCB DTCEC1 DTCEE1 DTVEC1 A17 A9 A1 IRQ9E IRQ9F IRQ12SCB IRQ8SCB ISS9 ISS1 OBE SCK1 PNCAH MSTP9 Bit 0 ICRD0 ICRA0 ICRB0 ICRC0 IRQ0F IRQ4SCA IRQ0SCA DTCEC0 DTCEE0 DTVEC0 BIE A16 A8 IRQ8E IRQ8F IRQ12SCA IRQ8SCA ISS8 ISS0 PWCKX0C SCK0 MSTP8 PWMX
SYSTEM
Module INT
DTC
INT
PORT
BSC
Rev. 2.00 Aug. 20, 2008 Page 1099 of 1198 REJ09B0403-0200
Section 29 List of Registers
Register Abbreviation MSTPCRL ICCR_1 ICSR_1 ICDR_1 SARX_1 ICMR_1 SAR_1 TIER TCSR FRC Bit 7 MSTP7 ICE ESTP bit 7 SVAX6 MLS SVA6 bit 15 bit 7 OCRA bit 15 bit 7 OCRB bit 15 bit 7 TCR TOCR OCRAR bit 15 bit 7 OCRAF bit 15 bit 7 DADRA_0 DA13 DA5 DACR_0 DADRB_0 DA13 DA5 DACNT_0 UC7 UC8 TCSR_0 TCNT_0 OVF bit 7 Bit 6 MSTP6 IEIC STOP bit 6 SVAX5 WAIT SVA5 bit 14 bit 6 bit 14 bit 6 bit 14 bit 6 OCRAMS bit 14 bit 6 bit 14 bit 6 DA12 DA4 PWME DA12 DA4 UC6 UC9 WT/IT bit 6 Bit 5 MSTP5 MST IRTR bit 5 SVAX4 CKS2 SVA4 bit 13 bit 5 bit 13 bit 5 bit 13 bit 5 ICRS bit 13 bit 5 bit 13 bit 5 DA11 DA3 DA11 DA3 UC5 UC10 TME bit 5 Bit 4 MSTP4 TRS AASX bit 4 SVAX3 CKS1 SVA3 bit 12 bit 4 bit 12 bit 4 bit 12 bit 4 OCRS bit 12 bit 4 bit 12 bit 4 DA10 DA2 DA10 DA2 UC4 UC11 bit 4 Bit 3 MSTP3 ACKE AL bit 3 SVAX2 CKS0 SVA2 OCIAE OCFA bit 11 bit 3 bit 11 bit 3 bit 11 bit 3 bit 11 bit 3 bit 11 bit 3 DA9 DA1 OEB DA9 DA1 UC3 UC12 RST/NMI bit 3 Bit 2 MSTP2 BBSY AAS bit 2 SVAX1 BC2 SVA1 OCIBE OCFB bit 10 bit 2 bit 10 bit 2 bit 10 bit 2 bit 10 bit 2 bit 10 bit 2 DA8 DA0 OEA DA8 DA0 UC2 UC13 CKS2 bit 2 Bit 1 MSTP1 IRIC ADZ bit 1 SVAX0 BC1 SVA0 OVIE OVF bit 9 bit 1 bit 9 bit 1 bit 9 bit 1 CKS1 bit 9 bit 1 bit 9 bit 1 DA7 CFS OS DA7 CFS UC1 CKS1 bit 1 Bit 0 MSTP0 SCP ACKB bit 0 FSX BC0 FS CCLRA bit 8 bit 0 bit 8 bit 0 bit 8 bit 0 CKS0 bit 8 bit 0 bit 8 bit 0 DA6 CKS DA6 REGS UC0 REGS CKS0 bit 0 WDT_0
PWMX_0
Module
SYSTEM
IIC_1
FRT
Rev. 2.00 Aug. 20, 2008 Page 1100 of 1198 REJ09B0403-0200
Section 29 List of Registers
Register Abbreviation PAODR PAPIN PADDR P1PCR P2PCR P3PCR P1DDR P2DDR P1DR P2DR P3DDR P4DDR P3DR P4DR P5DDR P6DDR P5DR P6DR PBODR PBPIN P8DDR P7PIN PBDDR P8DR P9DDR P9DR IER STCR SYSCR MDCR Bit 7 PA7ODR PA7PIN PA7DDR P17PCR P27PCR P37PCR P17DDR P27DDR P17DR P27DR P37DDR P47DDR P37DR P47DR P57DDR P67DDR P57DR P67DR PB7ODR PB7PIN P87DDR P77PIN PB7DDR P87DR P97DDR P97DR IRQ7E IICX2 CS256E EXPE Bit 6 PA6ODR PA6PIN PA6DDR P16PCR P26PCR P36PCR P16DDR P26DDR P16DR P26DR P36DDR P46DDR P36DR P46DR P56DDR P66DDR P56DR P66DR PB6ODR PB6PIN P86DDR P76PIN PB6DDR P86DR P96DDR P96DR IRQ6E IICX1 IOSE Bit 5 PA5ODR PA5PIN PA5DDR P15PCR P25PCR P35PCR P15DDR P25DDR P15DR P25DR P35DDR P45DDR P35DR P45DR P55DDR P65DDR P55DR P65DR PB5ODR PB5PIN P85DDR P75PIN PB5DDR P85DR P95DDR P95DR IRQ5E IICX0 INTM1 Bit 4 PA4ODR PA4PIN PA4DDR P14PCR P24PCR P34PCR P14DDR P24DDR P14DR P24DR P34DDR P44DDR P34DR P44DR P54DDR P64DDR P54DR P64DR PB4ODR PB4PIN P84DDR P74PIN PB4DDR P84DR P94DDR P94DR IRQ4E INTM0 Bit 3 PA3ODR PA3PIN PA3DDR P13PCR P23PCR P33PCR P13DDR P23DDR P13DR P23DR P33DDR P43DDR P33DR P43DR P53DDR P63DDR P53DR P63DR PB3ODR PB3PIN P83DDR P73PIN PB3DDR P83DR P93DDR P93DR IRQ3E FLSHE XRST Bit 2 PA2ODR PA2PIN PA2DDR P12PCR P22PCR P32PCR P12DDR P22DDR P12DR P22DR P32DDR P42DDR P32DR P42DR P52DDR P62DDR P52DR P62DR PB2ODR PB2PIN P82DDR P72PIN PB2DDR P82DR P92DDR P92DR IRQ2E NMIEG MDS2 Bit 1 PA1ODR PA1PIN PA1DDR P11PCR P21PCR P31PCR P11DDR P21DDR P11DR P21DR P31DDR P41DDR P31DR P41DR P51DDR P61DDR P51DR P61DR PB1ODR PB1PIN P81DDR P71PIN PB1DDR P81DR P91DDR P91DR IRQ1E ICKS1 MDS1 Bit 0 PA0ODR PA0PIN PA0DDR P10PCR P20PCR P30PCR P10DDR P20DDR P10DR P20DR P30DDR P40DDR P30DR P40DR P50DDR P60DDR P50DR P60DR PB0ODR PB0PIN P80DDR P70PIN PB0DDR P80DR P90DDR P90DR IRQ0E ICKS0 RAME INT
SYSTEM
Module PORT
Rev. 2.00 Aug. 20, 2008 Page 1101 of 1198 REJ09B0403-0200
Section 29 List of Registers
Register Abbreviation BCR WSCR TCR_0 TCR_1 TCSR_0 TCSR_1 TCORA_0 TCORA_1 TCORB_0 TCORB_1 TCNT_0 TCNT_1 ICCR_0 ICSR_0 ICDR_0 SARX_0 ICMR_0 SAR_0 SMR_3*
3
Bit 7 ABW256 CMIEB CMIEB CMFB CMFB bit 7 bit 7 bit 7 bit 7 Bit7 bit 7 ICE ESTP bit 7 SVAX6 MLS SVA6 C/A (GM)
Bit 6 ICIS AST256 CMIEA CMIEA CMFA CMFA bit 6 bit 6 bit 6 bit 6 bit 6 bit 6 IEIC STOP bit 6 SVAX5 WAIT SVA5 CHR (BLK) bit 6 RIE bit 6 RDRF (RDRF) bit 6 WT/IT bit 6 CMIEA CMFA
Bit 5 BRSTRM ABW OVIE OVIE OVF OVF bit 5 bit 5 bit 5 bit 5 bit 5 bit 5 MST IRTR bit 5 SVAX4 CKS2 SVA4 PE (PE) bit 5 TE bit 5 ORER (ORER) bit 5 TME bit 5 OVIE OVF
Bit 4 BRSTS1 AST ADTE bit 4 bit 4 bit 4 bit 4 bit 4 bit 4 TRS AASX bit 4 SVAX3 CKS1 SVA3 O/E (O/E) bit 4 RE bit 4 FER (ERS) bit 4 PSS bit 4
Bit 3 BRSTS0 WMS1 bit 3 bit 3 bit 3 bit 3 bit 3 bit 3 ACKE AL bit 3 SVAX2 CKS0 SVA2 STOP (BCP1) bit 3 MPIE bit 3 PER (PER) bit 3 SDIR RST/NMI bit 3
Bit 2 WMS0 CKS2 CKS2 bit 2 bit 2 bit 2 bit 2 bit 2 bit 2 BBSY AAS bit 2 SVAX1 BC2 SVA1 MP (BCP0) bit 2 TIE bit 2 TEND (TEND) bit 2 SINV CKS2 bit 2 CKS2
Bit 1 IOS1 WC1 CKS1 CKS1 bit 1 bit 1 bit 1 bit 1 bit 1 bit 1 IRIC ADZ bit 1 SVAX0 BC1 SVA0 CKS1 (CKS1) bit 1 CKE1 bit 1 MPB (MPB) bit 1 CKS1 bit 1 CKS1
Bit 0 IOS0 WC0 CKS0 CKS0 bit 0 bit 0 bit 0 bit 0 bit 0 bit 0 SCP ACKB bit 0 FSX BC0 FS CKS0 (CKS0) bit 0 CKE0 bit 0 MPBT (MPBT) bit 0 SMIF CKS0 bit 0 CKS0
Module BSC
TMR_0,1
IIC_0
SCI_3
BRR_3 SCR_3 TDR_3 SSR_3*
3
bit 7 TIE bit 7 TDRE (TDRE)
RDR_3 SCMR_3 TCSR_1 TCNT_1 TCR_X TCSR_X
bit 7 OVF bit 7 CMIEB CMFB
WDT_1
TMR_X,Y
Rev. 2.00 Aug. 20, 2008 Page 1102 of 1198 REJ09B0403-0200
Section 29 List of Registers
Register Abbreviation TCNT_X TCORA_X TCORB_X TCR_Y TCSR_Y TCORA_Y TCORB_Y TCNT_Y TCONRS Bit 7 bit 7 bit 7 bit 7 CMIEB CMFB bit 7 bit 7 bit 7 TMRX/Y Bit 6 bit 6 bit 6 bit 6 CMIEA CMFA bit 6 bit 6 bit 6 Bit 5 bit 5 bit 5 bit 5 OVIE OVF bit 5 bit 5 bit 5 Bit 4 bit 4 bit 4 bit 4 bit 4 bit 4 bit 4 Bit 3 bit 3 bit 3 bit 3 bit 3 bit 3 bit 3 Bit 2 bit 2 bit 2 bit 2 CKS2 bit 2 bit 2 bit 2 Bit 1 bit 1 bit 1 bit 1 CKS1 bit 1 bit 1 bit 1 Bit 0 bit 0 bit 0 bit 0 CKS0 bit 0 bit 0 bit 0 Module
TMR_X,Y
Notes: The registers related to USB are supported only by the H8S/2472 Group. The registers related to PECI are supported only by the H8S/2472 Group and the H8S/2462 Group 1. When TWRE = 1 or SELSTR3 = 0 2. When TWRE = 0 and SELSTR3 = 1 3. Some Bits have different names in normal mode and smart card interface mode. The Bit name in smart card interface mode is enclosed in parentheses.
Rev. 2.00 Aug. 20, 2008 Page 1103 of 1198 REJ09B0403-0200
Section 29 List of Registers
29.3
Register Abbreviation ECMR ECSR ECSIPR PIR MAHR MALR RFLR PSR TROCR CDCR LCCR CNDCR CEFCR FRECR TSFRCR TLFRCR RFCR MAFCR IPGR APR MPR TPAUSER EDMR EDTRR EDRRR TDLAR RDLAR
Register States in Each Operating Mode
High-Speed/ Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized WDT Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Medium-Speed Sleep Module Stop Software Standby Hardware Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized E-DMAC Module EtherC
Rev. 2.00 Aug. 20, 2008 Page 1104 of 1198 REJ09B0403-0200
Section 29 List of Registers
Register Abbreviation EESR EESIPR TRSCER RMFCR TFTR FDR RMCR FCFTR TRIMD RBWAR RDFAR TBRAR TDFAR ECBRR IFR0 IFR1 IFR2 IER0 IER1 IER2 ISR0 ISR1 ISR2 EPDR0i EPDR0o EPDR0s EPDR1 EPDR2 EPDR3 Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized WDT Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
High-Speed/ Medium-Speed Sleep Module Stop
Software Standby
Hardware Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized USB Module E-DMAC
Rev. 2.00 Aug. 20, 2008 Page 1105 of 1198 REJ09B0403-0200
Section 29 List of Registers
Register Abbreviation EPSZ0o EPSZ1 DASTS FCLR EPSTL TRG DMA CVR CTLR EPIR TRNTREG0 TRNTREG1 FRBR FTHR FDLL FIER FDLH FIIR FFCR FLCR FMCR FLSR FMSR FSCR SCIFCR SSCRH SSCRL SSMR SSER Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized WDT Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
High-Speed/ Medium-Speed Sleep Module Stop
Software Standby
Hardware Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized SSU SCIF Module USB
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Section 29 List of Registers
Register Abbreviation SSSR SSCR2 SSTDR0 SSTDR1 SSTDR2 SSTDR3 SSRDR0 SSRDR1 SSRDR2 SSRDR3 SSTRSR HICR4 BTSR0 BTSR1 BTCSR0 BTCSR1 BTCR BTIMSR SMICFLG HICR5 SMICCSR SMICDTR SMICIR0 SMICIR1 SIRQCR3 TWR0MW TWR0SW TWR1 TWR2 Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized WDT Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
High-Speed/ Medium-Speed Sleep Module Stop
Software Standby
Hardware Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized LPC Module SSU
Rev. 2.00 Aug. 20, 2008 Page 1107 of 1198 REJ09B0403-0200
Section 29 List of Registers
Register Abbreviation TWR3 TWR4 TWR5 TWR6 TWR7 TWR8 TWR9 TWR10 TWR11 TWR12 TWR13 TWR14 TWR15 IDR3 ODR3 STR3 SIRQCR4 LADR3H LADR3L SIRQCR0 SIRQCR1 IDR1 ODR1 STR1 SIRQCR5 IDR2 ODR2 STR2 HISEL Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized WDT Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
High-Speed/ Medium-Speed Sleep Module Stop
Software Standby
Hardware Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Module LPC
Rev. 2.00 Aug. 20, 2008 Page 1108 of 1198 REJ09B0403-0200
Section 29 List of Registers
Register Abbreviation HICR0 HICR1 HICR2 HICR3 SIRQCR2 BTDTR BTFVSR0 BTFVSR1 LADR12H LADR12L SCIFADRH SCIFADRL SUBMSTPBH SUBMSTPBL ECS ECCR MSTPCRA P3NCE P3NCMC NCCS PEODR PFODR PEPIN PEDDR PFPIN PFDDR PCODR PDODR Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized WDT Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
High-Speed/ Medium-Speed Sleep Module Stop
Software Standby
Hardware Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized SYSTEM PORT EVC SYSTEM Module LPC
Rev. 2.00 Aug. 20, 2008 Page 1109 of 1198 REJ09B0403-0200
Section 29 List of Registers
Register Abbreviation PCPIN PCDDR PDPIN PDDDR FCCS FPCS FECS FKEY FMATS FTDAR ICCR_4 ICSR_4 ICDR_4 SARX_4 ICMR_4 SAR_4 ICCR_5 ICSR_5 ICDR_5 SARX_5 ICMR_5 SAR_5 SMR_1 BRR_1 SCR_1 TDR_1 SSR_1 RDR_1 SCMR_1 Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized WDT Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
High-Speed/ Medium-Speed Sleep Module Stop Initialized Initialized Initialized
Software Standby Initialized Initialized Initialized
Hardware Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized SCI_1 IIC_5 IIC_4 FLASH Module PORT
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Section 29 List of Registers
Register Abbreviation ADDRA ADDRB ADDRC ADDRD ADDRE ADDRF ADDRG ADDRH ADCSR ADCR SMR0 SMR1 P4BNCE P4BNCMC P6PCR PINFNCR P4PCR ICCR_3 ICSR_3 ICDR_3 SARX_3 ICMR_3 SAR_3 ICCR_2 ICSR_2 ICDR_2 SARX_2 ICMR_2 SAR_2 Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized WDT Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
High-Speed/ Medium-Speed Sleep Module Stop Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Software Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Hardware Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized IIC_2 IIC_3 PORT SMX Module ADC
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Section 29 List of Registers
Register Abbreviation DADRA_1 DACR_1 DADRB_1 DACNT_1 CRCCR CRCDIR CRCDOR ICXR_0 ICXR_1 ICSMBCR ICXR_2 ICXR_3 IICX3 ICXR_4 ICXR_5 KBCOMP DTCERF ICRD ICRA ICRB ICRC ISR ISCRH ISCRL DTCERA DTCERB DTCERC DTCERD DTCERE DTVECR Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized WDT Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
High-Speed/ Medium-Speed Sleep Module Stop Initialized Initialized Initialized Initialized
Software Standby Initialized Initialized Initialized Initialized
Hardware Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized DTC IIC_0 IIC_1 IIC IIC_2 IIC_3 IIC IIC_4 IIC_5 EVC DTC INT CRC Module PWMX_1
Rev. 2.00 Aug. 20, 2008 Page 1112 of 1198 REJ09B0403-0200
Section 29 List of Registers
Register Abbreviation ABRKCR BARA BARB BARC IER16 ISR16 ISCR16H ISCR16L ISSR16 ISSR PTCNT0 BCR2 WSCR2 PCSR SYSCR2 SBYCR LPWRCR MSTPCRH MSTPCRL ICCR_1 ICSR_1 ICDR_1 SARX_1 ICMR_1 SAR_1 TIER TCSR FRC OCRA OCRB Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized WDT Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
High-Speed/ Medium-Speed Sleep Module Stop
Software Standby
Hardware Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized FRT IIC_1 PWMX_0,1 SYSTEM BSC PORT Module INT
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Section 29 List of Registers
Register Abbreviation TCR TOCR OCRAR OCRAF DADRA_0 DACR_0 DADRB_0 DACNT_0 TCSR_0 TCNT_0 PAODR PAPIN PADDR P1PCR P2PCR P3PCR P1DDR P2DDR P1DR P2DR P3DDR P4DDR P3DR P4DR P5DDR P6DDR P5DR P6DR PBODR Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized WDT Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
High-Speed/ Medium-Speed Sleep Module Stop Initialized Initialized Initialized Initialized
Software Standby Initialized Initialized Initialized Initialized
Hardware Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized PORT WDT_0 PWMX_0 Module FRT
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Section 29 List of Registers
Register Abbreviation PBPIN P8DDR P7PIN PBDDR P8DR P9DDR P9DR IER STCR SYSCR MDCR BCR WSCR TCR_0 TCR_1 TCSR_0 TCSR_1 TCORA_0 TCORA_1 TCORB_0 TCORB_1 TCNT_0 TCNT_1 ICCR_0 ICSR_0 ICDR_0 SARX_0 ICMR_0 SAR_0 Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized WDT Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
High-Speed/ Medium-Speed Sleep Module Stop
Software Standby
Hardware Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized IIC_0 TMR_0 TMR_1 BSC INT SYSTEM Module PORT
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Section 29 List of Registers
Register Abbreviation SMR_3 BRR_3 SCR_3 TDR_3 SSR_3 RDR_3 SCMR_3 TCSR_1 TCNT_1 TCR_X TCSR_X TCNT_X TCORA_X TCORB_X TCR_Y TCSR_Y TCORA_Y TCORB_Y TCNT_Y TCONRS Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized WDT Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
High-Speed/ Medium-Speed Sleep Module Stop Initialized Initialized Initialized
Software Standby Initialized Initialized Initialized
Hardware Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized TMR_X TMR_Y WDT_1 Module SCI_3
Notes: 1. The registers related to USB are supported only by the H8S/2472 Group. 2. The registers related to PECI are supported only by the H8S/2472 Group and the H8S/2462 Group.
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Section 30 Platform Environment Control Interface (PECI)
Section 30 Platform Environment Control Interface (PECI)
Renesas Technology Corporation is only able to provide information contained in this section to the parties with which we have concluded a nondisclosure agreement. Please contact one of our sales representatives for details. If this module is not used, the PECI-related pins should be handled as follows. PECI is not supported by the H8S/2463 Group. * Connect the PEVref pin to VSS. * Leave the other PECI pins open.
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Section 30 Platform Environment Control Interface (PECI)
Rev. 2.00 Aug. 20, 2008 Page 1118 of 1198 REJ09B0403-0200
Section 31 Electrical Characteristics
Section 31 Electrical Characteristics
31.1 Absolute Maximum Ratings
Table 31.1 lists the absolute maximum ratings. Table 31.1 Absolute Maximum Ratings
Item Power supply voltage* Input voltage (pins multiplexed with analog input) Input voltage (pins multiplexed with IIC functions) (1) (2) Symbol Value Unit V
VCC, DrVCC -0.3 to +4.3 Vin Vin Vin AVref AVCC VAN PEVref Vin Topr -0.3 to AVCC + 0.3 -0.3 to +6.5 -0.3 to VCC + 0.3 -0.3 to AVCC + 0.3 -0.3 to +4.3 -0.3 to AVCC + 0.3 -0.3 to +1.5 -0.15 to PEVref + 0.15
Input voltage (pins other than (1) and (2) above) Reference power supply voltage Analog power supply voltage Analog input voltage PECI reference power supply voltage Input voltage (PECI) Operating temperature
-20 to +75 (regular specifications) C -40 to +85 (wide temperature specifications)
Operating temperature Topr (when flash memory is programmed or erased) Storage temperature Tstg
0 to +75
-55 to +125
Caution: Permanent damage to this LSI may result if absolute maximum ratings are exceeded. Note: * Voltage applied to the VCC pin. Make sure power is not applied to the VCL pin.
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Section 31 Electrical Characteristics
31.2
DC Characteristics
Table 31.2 lists the DC characteristics. Table 31.3 lists the permissible output currents. Table 31.4 lists the bus drive characteristics. Table 31.2 DC Characteristics (1) Conditions: VCC = 3.0 V to 3.6 V, AVCC* = 3.0 V to 3.6 V, DrVCC = 3.0 V to 3.6 V, 1 1 AVref* = 3.0 V to AVCC, VSS = AVSS* = DrVSS = 0 V
Test Unit Conditions V
1
Item Schmitt trigger input voltage EVENT15 to EVENT0, (1) (Ex)DB7 to (Ex)DB0, (Ex)IRQ15 to (Ex)IRQ0, ETRST, XTAL, EXCL, ADTRG, UXTAL, UEXTAL SCL5 to SCL0, SDA5 to SDA0
Symbol Min. VT- VT
+
Typ. Max. VCC x 0.7 VCC x 0.7 VCC + 0.3 VCC + 0.3 AVCC + 0.3 5.5 VCC + 0.3
VCC x 0.2
VT+ - VT- VT- VT
+
VCC x 0.05 VCC x 0.3 VCC x 0.9 VCC x 0.7 2.2 VCC x 0.5
VT+ - VT- Input RES, STBY, NMI, FWE, MD2, high MD1 voltage EXTAL Port 7 SCL5 to SCL0, SDA5 to SDA0 CLKRUN, GA20, PME, LSMI, LSCI, SERIRQ, LAD3 to LAD0, LPCPD, LCLK, LRESET, LFRAME RM_REF-CLK, RM_CRS-DV, RM_RXD0, RM_RXD1, RM_RX-ER Input pins other than (1) and (2) above (2) VIH
VCC x 0.05
2.0
VCC + 0.3
2.2
VCC + 0.3
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Section 31 Electrical Characteristics Test Unit Conditions
Item Input RES, STBY, NMI, FWE, MD2, low MD1 voltage EXTAL (3)
Symbol Min. VIL -0.3 -0.3 -0.3 Port 7 CLKRUN, GA20, PME, LSMI, LSCI, SERIRQ, LAD3 to LAD0, LPCPD, LCLK, LRESET, LFRAME RM_REF-CLK, RM_CRS-DV, RM_RXD0, RM_RXD1, RM_RX-ER Input pins other than (1) and (3) above -0.3 -0.3
Typ. Max. VCC x 0.1 VCC x 0.1 VCC x 0.2 AVCC x 0.2 VCC x 0.3
f > 25 MHz f 25 MHz
-0.3
0.8
-0.3 VOH

VCC x 0.2 V
Output SCL5 to SCL0, SDA5 to SDA0, (4) high CLKRUN, GA20, PME, LSMI, voltage LSCI*2 Ports 80 to 83 , C0 to C5, D6, D7*3 SERIRQ, LAD3 to LAD0 RM_TX-EN, RM_TXD0, RM_TXD1 Output pins other than (4) above
0.5 VCC x 0.9 2.4 VCC -0.5 VCC -1.0

0.5 0.4 VCC x 0.1 0.4 0.4 1.0
IOH = -200 A
IOH = -0.5 mA
IOH = -4.0 mA
IOH = -200 A
IOH = -1 mA IOL = 8 mA IOL = 3 mA IOL = 1.5 mA IOH = 4.0 mA IOL = 1.6 mA IOL = 12 mA
Output SCL5 to SCL0, SDA5 to SDA0 (5) low voltage CLKRUN, GA20, PME, LSMI, LSCI, SERIRQ, LAD3 to LAD0 RM_TX-EN, RM_TXD0, RM_TXD1 Output pins other than (5) above HC7 to HC0
VOL

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Section 31 Electrical Characteristics
Table 31.2 DC Characteristics (2) Conditions: VCC = 3.0 V to 3.6 V, AVCC* = 3.0 V to 3.6 V, DrVCC = 3.0 V to 3.6 V, 1 1 AVref* = 3.0 V to AVCC, VSS = AVSS* = DrVSS = 0 V
Item Input leakage RES, STBY, NMI, FWE, current MD2, MD1 Port 7 Three-state leakage current (off state) Ports 1 to 6 Ports 8 to F ITSI Test Symbol Min. Typ. Max. Unit Conditions Iin 1.0 1.0 1.0 A VIN = 0.5 to VCC - 0.5 V VIN = 0.5 to AVCC - 0.5 V VIN = 0.5 to VCC - 0.5 V
1
Input pull-up Ports 1 to 4, 6, A, D5 to D0 -IP MOS current Supply current*4 Normal operation Sleep mode Standby mode*5 ICC
20
45 35 40 1.0 2.5
300 60 45 100 250 2.0 5.0 mA A A mA
VIN = 0 V f = 34 MHz, high-speed mode, All modules operating f = 34 MHz Ta 50 C 50 C < Ta
Analog power supply current Reference power supply current
During A/D conversion A/D conversion standby
AIcc

During A/D conversion A/D conversion standby
AIref
0.1 0.5
1.0 5.0
mA A
Input All input pin capacitance RAM standby voltage VCC start voltage VCC rising edge Notes:
Cin VRAM
3.0
0
10 0.8 20
pF V V ms/V
Vin = 0 V, f = 1 MHz, Ta = 25 C
VCCSTART SVCC
1. Do not leave the AVCC, AVref, and AVSS pins open even if the A/D converter is not used. Even if the A/D converter is not used, apply a value in the range from 3.0 V to 3.6 V to the AVCC and AVref pins by connecting them to the power supply (VCC). The relationship between these two pins should be AVref AVCC. 2. An external pull-up resistor is necessary to provide high-level output from SCL5 to SCL0, SDA5 to SDA0 (ICE bit in ICCR is 1), CLKRUN, GA20, PME, LSMI, and LSCI. 3. Ports 80 to 83, C0 to C5, D6, and D7 are NMOS push-pull outputs. High levels on ports 80 to 83, C0 to C5, D6, and D7 are driven by NMOS. An external pull-up resistor is necessary to provide high-level output from these pins when they are used as an output.
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Section 31 Electrical Characteristics 4. Supply current values are for VIH min = VCC - 0.2 V and VIL max = 0.2 V with all output pins unloaded and the on-chip pull-up MOSs in the off state. 5. When VCC = 3.0 V, VIH min = VCC - 0.2 V, and VIL max = 0.2 V.
Table 31.3 Permissible Output Currents Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, DrVCC = 3.0 V to 3.6 V, 1 1 AVref* = 3.0 V to AVCC, VSS = AVSS* = DrVSS = 0 V
Item Symbol Min. IOL -IOH -IOH Typ. Max. 10 12 1.6 48 90 2 60 Unit mA
Permissible output low current SCL5 to SCL0, SDA5 to SDA0 IOL (per pin) HC7 to HC0 Other output pins Permissible output low current Total of HC7 to HC0 (total) Total of all output pins, including the above Permissible output high current (per pin) Permissible output high current (total) Notes: All output pins Total of all output pins
1. To protect LSI reliability, do not exceed the output current values in table 31.3. 2. When driving a Darlington transistor or LED, always insert a current-limiting resistor in the output line, as show in figures 31.1 and 31.2.
This LSI
2 k
Port
Darlington transistor
Figure 31.1 Darlington Transistor Drive Circuit (Example)
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Section 31 Electrical Characteristics
This LSI
600 HC0 to HC7 LED
Figure 31.2 LED Drive Circuit (Example)
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Section 31 Electrical Characteristics
31.3
AC Characteristics
Figure 31.3 shows the test conditions for the AC characteristics.
3V C = 30pF : All ports RL = 2.4 k RH = 12 k I/O timing test levels * Low level : 0.8 V * High level : 1.5 V
RL LSI output pin C RH
Figure 31.3 Output Load Circuit 31.3.1 Clock Timing
Table 31.4 shows the clock timing. The clock timing specified here covers clock output () and clock pulse generator (crystal) and external clock input (EXTAL pin) oscillation stabilization times. For details of external clock input (EXTAL pin and EXCL pin) timing, see table 31.5 and 31.6. Table 31.4 Clock Timing Conditions: VCC = 3.0 V to 3.6 V, VSS = 0 V, = 20 MHz to 34 MHz
Item Clock cycle time Clock high level pulse width Symbol tcyc tCH Min. 29.4 9.7 9.7 10 8 Max. 50 5 5 ms Figure 31.5 Figure 31.6 Unit ns Test Conditions Figure 31.4
Clock low level pulse width tCL Clock rise time Clock fall time Reset oscillation stabilization (crystal) tCr tCf tOSC1
tOSC2 Software standby oscillation stabilization time (crystal)
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Section 31 Electrical Characteristics
Table 31.5 External Clock Input Conditions Conditions: VCC = 3.0 V to 3.6 V, VSS = 0 V, = 20 MHz to 34 MHz
Test Conditions Figure 31.7
Item External clock input low level pulse width External clock input high level pulse width
Symbol tEXL tEXH
Min. 58.8 58.8 0.4 0.4 500
Max. 5 5 0.6 0.6
Unit ns ns ns ns tcyc tcyc s
External clock input rising time tEXr External clock input falling time tEXf Clock low level pulse width Clock high level pulse width External clock output stabilization delay time Note: * tCL tCH tDEXT*
Figure 31.4
Figure 31.8
tDEXT includes a RES pulse width (tRESW).
Table 31.6 Subclock Input Conditions Conditions: VCC = 3.0 V to 3.6 V, VSS = 0 V, = 20 MHz to 34 MHz
Test Conditions Figure 31.9
Item
Symbol
Min. 0.4 0.4
Typ. 15.26 15.26
Max. 10 10 0.6 0.6
Unit s s ns ns tcyc tcyc
Subclock input low level pulse tEXCLL width Subclock input high level pulse tEXCLH width Subclock input rising time Subclock input falling time Clock low level pulse width Clock high level pulse width tEXCLr tEXCLf tCL tCH
Figure 31.4
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Section 31 Electrical Characteristics
tcyc tCH tCf
tCL
tCr
Figure 31.4 System Clock Timing
VCC
STBY
tOSC1 RES
tOSC1
Figure 31.5 Oscillation Stabilization Timing
NMI
IRQi ( i = 0 to 15 ) tOSC2
Figure 31.6 Oscillation Stabilization Timing (Exiting Software Standby Mode)
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Section 31 Electrical Characteristics
tEXH
tEXL
EXTAL
VCC x 0.5
tEXr
tEXf
Figure 31.7 External Clock Input Timing
VCC
2.7 V
STBY
VIH
EXTAL
(Internal and external)
RES tDEXT*
Note: The external clock output stabilization delay time (tDEXT) includes a RES pulse width (tRESW).
Figure 31.8 Timing of External Clock Output Stabilization Delay Time
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Section 31 Electrical Characteristics
tEXCLH
tEXCLL
EXCL
VCC x 0.5
tEXCLr
tEXCLf
Figure 31.9 Subclock Input Timing
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Section 31 Electrical Characteristics
31.3.2
Control Signal Timing
Table 31.7 shows the control signal timing. Only external interrupts NMI and IRQ0 to IRQ15 can be driven based on the subclock (SUB = 32.768 kHz). Table 31.7 Control Signal Timing Conditions: VCC = 3.0 V to 3.6 V, VSS = 0 V, = 20 MHz to 34 MHz
Item RES setup time RES pulse width NMI setup time NMI hold time Symbol tRESS tRESW tNMIS tNMIH Min. 200 20 150 10 200 Max. Unit ns tcyc ns Figure 31.11 Test Conditions Figure 31.10
NMI pulse width tNMIW (exiting software standby mode) IRQ setup time (IRQ15 to IRQ0) IRQ hold time (IRQ15 to IRQ0) IRQ pulse width (IRQ15 to IRQ0) (exiting software standby mode) tIRQS tIRQH tIRQW
150 10 200

tRESS RES tRESW
tRESS
Figure 31.10 Reset Input Timing
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Section 31 Electrical Characteristics
tNMIS NMI tNMIW
tNMIH
IRQi (i = 0 to 15) tIRQS IRQ Edge input
tIRQW tIRQH
tIRQS IRQ Level input
Figure 31.11 Interrupt Input Timing
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Section 31 Electrical Characteristics
31.3.3
Bus Timing
Table 31.8 shows the bus timing. In subclock (SUB = 32.768 kHz) operation, external expansion mode operation cannot be guaranteed. Table 31.8 Bus Timing Conditions: VCC = 3.0 V to 3.6 V, VSS = 0 V, = 20 MHz to 34 MHz
Item Address delay time Address setup time Address hold time CS delay time (IOS, CS256) AS delay time HBE delay time LBE delay time RD delay time 1 RD delay time 2 Read data setup time Read data hold time Symbol tAD tAS tAH tCSD tASD tHBD tLBD tRSD1 tRSD2 tRDS tRDH Min. 0.5 x tcyc -14.7 0.5 x tcyc - 9.7 14.7 0 Max. 14.7 14.7 14.7 tAD + 5.0 tAD + 5.0 14.7 14.7 1.0 x tcyc - 29.4 1.5 x tcyc - 24.7 2.0 x tcyc - 29.4 2.5 x tcyc - 24.7 3.0 x tcyc - 29.4 14.7 14.7 Unit ns Test Conditions Figures 31.12 to 31.19
Read data access time 1 tACC1 Read data access time 2 tACC2 Read data access time 3 tACC3 Read data access time 4 tACC4 Read data access time 5 tACC5 WR delay time 1 WR delay time 2 WR pulse width 1 WR pulse width 2 Write data delay time Write data setup time Write data hold time WAIT setup time WAIT hold time tWRD1 tWRD2 tWSW1 tWSW2 tWDD tWDS tWDH tWTS tWTH
1.0 x tcyc - 19.6 1.5 x tcyc - 19.6 0 0.5 x tcyc - 5 24.7 5 24.7
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Section 31 Electrical Characteristics
T1
T2
tAD A23 to A0, IOS* CS256 tCSD tAS tASD AS* tASD tAH
tRSD1 RD (Read) tAS
tACC2
tRSD2
tACC3 D15 to D0 (Read)
tRDS
tRDH
tWRD2 HWR, LWR (Write) tAS tWDD D15 to D0 (Write) tWSW1
tWRD2 tAH tWDH
Note: * AS is multiplexed with IOS. Either the AS or IOS function can be selected by the IOSE bit of SYSCR.
Figure 31.12 Basic Bus Timing/2-State Access
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Section 31 Electrical Characteristics
T1
T2
T3
tAD A23 to A0, IOS* CS256 tCSD tAS tASD AS* tASD tAH
tRSD1 RD (Read) tAS D15 to D0 (Read)
tACC4
tRSD2
tACC5
tRDS
tRDH
tWRD1 HWR, LWR (Write) tWDD D15 to D0 (Write) tWDS tWSW2
tWRD2 tAH tWDH
Note: * AS is multiplexed with IOS. Either the AS or IOS function can be selected by the IOSE bit of SYSCR.
Figure 31.13 Basic Bus Timing/3-State Access
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Section 31 Electrical Characteristics
T1
T2
Tw
T3
A23 to A0, IOS* CS256
AS*
RD (Read)
D15 to D0 (Read)
HWR, LWR (Write) D15 to D0 (Write) tWTS WAIT tWTH tWTS tWTH
Note: * AS is multiplexed with IOS. Either the AS or IOS function can be selected by the IOSE bit of SYSCR.
Figure 31.14 Basic Bus Timing/3-State Access with One Wait State
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Section 31 Electrical Characteristics
T1
T2
tAD Address [A23 to A0] tCSD
Even
IOS (IOSE = 1) CS256 (CS256E = 1)
tAS AS tHBD
HBE LBE
L
tASD
tASD
tAH
tRSD1 RD Read Bus Cycle
WR Read Bus Cycle
tACC2
tRSD2
tAS
L
tACC3
tRDS
tRDH
D15 to D8 D7 to D0
Valid Invalid
RD Write Bus Cycle
L
tWRD1 tAS tWDD tWSW1
tWRD2 tAH tWDH
WR Write Bus Cycle
D15 to D8
Valid Undified
D7 to D0
Figure 31.15 Even Byte Access (ADMXE = 0)
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Section 31 Electrical Characteristics
T1
T2
tAD Address [A23 to A0] tCSD
Odd
IOS (IOSE = 1) CS256 (CS256E = 1)
tAS AS
HBE
L
tASD
tASD
tAH
tLBD
LBE
tRSD1 RD Read Bus Cycle
WR Read Bus Cycle
tACC2
tRSD2
tAS
L
tACC3
tRDS
tRDH
D15 to D8 D7 to D0
Invalid Valid
RD Write Bus Cycle
L
tWRD1 tAS tWDD tWSW1
tWRD2 tAH tWDH
WR Write Bus Cycle
D15 to D8
Undifined Valid
D7 to D0
Figure 31.16 Odd Byte Access (ADMXE = 0)
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Section 31 Electrical Characteristics
T1
T2
tAD Address [A23 to A0] tCSD
IOS (IOSE = 1) CS256 (CS256E = 1)
tAS AS tHBD
HBE
tASD
tASD
tAH
tLBD
LBE
tRSD1 RD Read Bus Cycle
WR Read Bus Cycle
tACC2
tRSD2
tAS
L
tACC3
tRDS
tRDH
D15 to D8 D7 to D0
Valid Valid
RD Write Bus Cycle
L
tWRD1 tAS tWDD tWSW1
tWRD2 tAH tWDH
WR Write Bus Cycle
D15 to D8
Valid Valid
D7 to D0
Figure 31.17 Word Access (ADMXE = 0)
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Section 31 Electrical Characteristics
T1
T2 or T3
T1
T2
tAD A23 to A0, IOS* CS256 tAS tASD AS* tASD tAH
tRSD2 RD (Read) tACC3 D15 to D0 (Read) tRDS tRDH
Note: * AS is multiplexed with IOS. Either the AS or IOS function can be selected by the IOSE bit of SYSCR.
Figure 31.18 Burst ROM Access Timing/2-State Access
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Section 31 Electrical Characteristics
T1
T2 or T3
T1
tAD A23 to A0, IOS* CS256
AS*
tRSD2 RD (Read) tACC1 D15 to D0 (Read) tRDS tRDH
Note: * AS is multiplexed with IOS. Either the AS or IOS function can be selected by the IOSE bit of SYSCR.
Figure 31.19 Burst ROM Access Timing/1-State Access
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Section 31 Electrical Characteristics
31.3.4
Multiplex Bus Timing
Table 31.9 shows the Multiplex bus interface timing. In subclock (SUB = 32.768 kHz) operation, external expansion mode operation cannot be guaranteed. Table 31.9 Multiplex Bus Timing Conditions: VCC = 3.0 V to 3.6 V, VSS = 0 V, = 20 MHz to 34 MHz
Item Address delay time Address setup time 2 Address hold time 2 CS delay time (IOS, CS256) AH delay time RD delay time 1 RD delay time 2 Read data setup time Read data hold time Symbol tAD tAS2 tAH2 tCSD tAHD tRSD1 tRSD2 tRDS tRDH Min.. 0.5 x tcyc - 9.7 14.7 0 Max. 14.7 14.7 14.7 14.7 14.7 1.5 x tcyc - 24.4 2.5 x tcyc - 24.4 3.5 x tcyc - 24.4 4.5 x tcyc - 24.4 14.7 14.7 Unit ns Test Conditions Figures 31.20, 31.21
0.5 x tcyc - 14.7
Read data access time 2 tACC2 Read data access time 4 tACC4 Read data access time 6 tACC6 Read data access time 7 tACC7 WR delay time 1 WR delay time 2 WR pulse width time 1 WR pulse width time 2 Write data delay time Write data setup time Write data hold time tWRD1 tWRD2 tWSW1 tWSW2 tWDD tWDS tWDH
1.0 x tcyc - 19.6 1.5 x tcyc - 19.6 0 0.5 x tcyc - 5 24.4
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Section 31 Electrical Characteristics
T1
T2
T3
T4
tCSD IOS, CS256 tAHD AH tRSD1 RD (Read) tACC6 AD15 to AD0 (Read) tAD tAS2 A15 to A0 tAH2 tWRD2 HWR, LWR (Write) tAD AD15 to AD0 (Write) A15 to A0 tWDD D15 to D0 tWSW1 tWDH tWRD2 tRDS tRDH tACC2 tRSD2
D15 to D0
Figure 31.20 Multiplex Bus Timing/Data 2-State Access
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Section 31 Electrical Characteristics
T1
T2
T3
T4
T5
tCSD IOS, CS256 tAHD AH tRSD1 RD (Read) tACC7 AD15 to AD0 (Read) A15 to A0 tAD
tAS2 tAH2
tACC4
tRSD2
tRDS tRDH
D15 to D0
tWRD1 HWR, LWR (Write) AD15 to AD0 (Write) tWSW2 tAD A15 to A0 tWDD tWDS D15 to D0
tWRD2
tWDH
Figure 31.21 Multiplex Bus Timing/Data 3-State Access
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Section 31 Electrical Characteristics
31.3.5
Timing of On-Chip Peripheral Modules
Tables 31.10 to 31.13 show the on-chip peripheral module timing. The on-chip peripheral modules that can be operated by the subclock (SUB = 32.768 kHz) are I/O ports, external interrupts (NMI, IRQ0 to IRQ15), watchdog timer, and 8-bit timer (channels 0 and 1) only.
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Section 31 Electrical Characteristics
Table 31.10 Timing of On-Chip Peripheral Modules Conditions: VCC = 3.0 V to 3.6 V, VSS = 0 V, SUB = 32.768 kHz*, = 20 MHz to 34 MHz
Item I/O ports Output data delay time Input data setup time Input data hold time PWMX SCI Timer output delay time Input clock cycle Asynchronous Synchronous tSCKW tSCKr tSCKf tTXD tRXS tRXH tRXS tRXH tTRGS tRESD Symbol Min. tPWD tPRS tPRH tPWOD tScyc 19.6 19.6 4 6 0.4 19.6 19.6 30.0 30.0 19.6 Max. 29.4 29.4 0.6 1.5 1.5 29.4 50 Figure 31.26 Figure 31.27 ns Figure 31.25 ns Figure 31.25 tScyc tcyc ns tcyc Figure 31.23 Figure 31.24 Unit Test Conditions ns Figure 31.22
Input clock pulse width Input clock rise time Input clock fall time Transmit data delay time (synchronous) Receive data setup time (synchronous) Receive data hold time (synchronous) SCI Receive data setup time (multiplexed (synchronous) with P51) Receive data hold time (synchronous) A/D converter WDT Trigger input setup time RESO output delay time
RESO output pulse width Note: *
tRESOW
132
tcyc
Only the peripheral modules that can be used in subclock operation.
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Section 31 Electrical Characteristics
Table 31.11 Timing of On-Chip Peripheral Modules (2) Conditions: VCC = 3.0 V to 3.6 V, VSS = 0 V, = 20 MHz to 34 MHz
Item SSU
Clock cycle time Master Slave Clock high pulse width Master Slave Clock low pulse width Master Slave Clock rising time Clock falling time Data input setup time Master Slave Data input hold time SCS setup time SCS hold time Master Slave Master Slave Master Slave Data output delay time Master Slave Data output hold time Master Slave Consecutive transmit delay time Master Slave
Symbol tSUcyc tHI tLO tRISE tFALL tSU tH tLEAD tLAG tOD tOH tTD tSA tREL
Min. 4 4 80 80 80 80 25 30 10 10 2.5 2.5 2.5 2.5 30 30 2.5 2.5
Max. 256 256 20 20 40 40 1 1
Unit tcyc ns ns ns ns ns ns tcyc tcyc ns ns tcyc tcyc tcyc
Test Conditions Figure 31.28 Figure 31.29 Figure 31.30 Figure 31.31
Slave access time Slave out release time
Figure 31.30 Figure 31.31
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Section 31 Electrical Characteristics
T1
T2
tPRS Ports 1 to 9 and A to F (read)
tPRH
tPWD Ports 1 to 6, 8, 9 and A to F (write)
Figure 31.22 I/O Port Input/Output Timing
tPWOD PWX3 to PWX0
Figure 31.23 PWMX Output Timing
tSCKW tSCKr tSCKf
SCK1, SCK3
tScyc
Figure 31.24 SCK Clock Input Timing
SCK1, SCK3 tTXD TxD1, TxD3 (transmit data) tRXS RxD1, RxD3 (receive data) tRXH
Figure 31.25 SCI Input/Output Timing (Clock Synchronous Mode)
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Section 31 Electrical Characteristics
tTRGS ADTRG
Figure 31.26 A/D Converter External Trigger Input Timing
tRESD tRESD
RESO tRESOW
Figure 31.27 WDT Output Timing (RESO)
SCS (output) tLEAD SSCK (output) CPOS = 1 tLO tHI SSCK (output) CPOS = 0 tLO SSO (output) tOH SSI (input) tOD tSUcyc tHI tFALL tRISE tLAG tTD
tSU
tH
Figure 31.28 SSU Timing (Master, CPHS = 1)
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Section 31 Electrical Characteristics
SCS (output) tLEAD SSCK (output) CPOS = 1 tLO tHI SSCK (output) CPOS = 0 tLO SSO (output) tOH SSI (input) tOD tSUcyc tHI tFALL tRISE tLAG tTD
tSU
tH
Figure 31.29 SSU Timing (Master, CPHS = 0)
SCS (input) tLEAD SSCK (input) CPOS = 1 tLO tHI SSCK (input) CPOS = 0 tLO SSO (input) tREL tSUcyc tHI tFALL tRISE tLAG tTD
tSU SSI (output) tSA
tH
tOH
tOD
Figure 31.30 SSU Timing (Slave, CPHS = 1)
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Section 31 Electrical Characteristics
SCS (input) tLEAD SSCK (input) CPOS = 1 tLO tHI SSCK (input) CPOS = 0 tLO SSO (input) tREL tH tSUcyc tHI tFALL tRISE tLAG tTD
tSU SSI (output) tSA tOH
tOD
Figure 31.31 SSU Timing (Slave, CPHS = 0)
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Section 31 Electrical Characteristics
Table 31.12 I C Bus Timing Conditions: VCC = 3.0 V to 3.6 V, VSS = 0 V, = 20 MHz to 34 MHz
Item SCL input cycle time Symbol tSCL tSCLL tSr tSf tOf tSP tBUF tSTAH tSTAS tSTOS tSDAS tSDAH Cb Min. 12 3 5 5 3 3 3 0.5 0 Typ. Max. 7.5* 300 250 1 400 ns pF tcyc ns Unit tcyc Test Conditions Figure 31.32
2
SCL input high pulse width tSCLH SCL input low pulse width SCL, SDA input rise time SCL, SDA input fall time SCL, SDA output fall time SCL, SDA input spike pulse elimination time SDA input bus free time Start condition input hold time Repeated start condition input setup time Stop condition input setup time Data input setup time Data input hold time SCL, SDA capacitive load Note: *
20 + 0.1 Cb
17.5 tcyc or 37.5 tcyc can be set according to the clock selected for use by the IIC module.
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Section 31 Electrical Characteristics
SDA0 to SDA5 tBUF
VIH VIL
tSTAH SCL0 to SCL5 P* S* tSf tSCLL tSCL
tSCLH
tSTAS
tSP
tSTOS
Sr* tSr tSDAH tSDAS
P*
Note: * S, P, and Sr indicate the following conditions: S: Start condition P: Stop condition Sr: Repeated start condition
Figure 31.32 I C Bus Interface Input/Output Timing Table 31.13 LPC Module Timing Conditions: VCC = 3.0 V to 3.6V, VSS = 0 V, = 20 MHz to 34 MHz
Item Input clock cycle Input clock pulse width (H) Input clock pulse width (L) Transmit signal delay time Transmit signal floating delay time Receive signal setup time Receive signal hold time Symbol tLcyc tLCKH tLCKL tTXD tOFF tRXS tRXH Min. 30 11 11 2 7 0 Typ. Max. 11 28 Unit ns Test Conditions Figure 31.33
2
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Section 31 Electrical Characteristics
tLCKH
tLcyc
LCLK
tLCKL LCLK tTXD LAD3 to LAD0, SERIRQ, CLKRUN (Transmit signal) tRXS LAD3 to LAD0, SERIRQ, CLKRUN, LFRAME (Receive signal) tOFF LAD3 to LAD0, SERIRQ, CLKRUN (Transmit signal) tRXH
Figure 31.33 LPC Interface (LPC) Timing
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Section 31 Electrical Characteristics
Table 31.14 Ethernet Controller Signal Timing Conditions: VCC = 3.0 V to 3.6V, VSS = 0 V, = 20 MHz to 34 MHz
Item RM_REF-CLK cycle time RM_REF-CLK frequency RM_REF-CLK duty cycle RM_REF-CLK rise/fall time RM_xxxx* output delay time RM_xxxx* setup time RM_xxxx* hold time RM_xxxx* rise/fall time MDIO setup time MDIO hold time MDIO output data hold time* WOL output delay time
2 1 1 1 1
Symbol Tck Tckr/Tckf Tco Tsu Thd Tr/Tf tMDIOS tMDIOH tMDIODH tWOLD
Min. 20 35 0.5 2.5 3 1 0.5 10 10 5 1
Typ. 50
Max.
Unit ns
Test Conditions Figure 31.34
50 + MHz 100 ppm 65 3.5 12.5 6 18 20 Figure 31.39 Figure 31.40 Figure 31.38 % ns
Notes: 1. RM_TXD-EN, RM_TXD1, RM_TXD0, RM_CRS-DV, RM_RXD1, RM_RXD0, and RM_RX-ER 2. This specification must be satisfied by the user by software.
Tck 90 % RM_REF-CLK 50 % Tckf 10 % Tco Tf Signal transition Tsu Thd
Tckr
Tr 90 % RM_xxxx 50 % 10 %
Signal transition
Signal
Signal
Signal transition
Figure 31.34 Timing of RM_REF-CLK and RMII Signals
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Section 31 Electrical Characteristics
Tck RM_REF-CLK Tco
RM_TXD_EN Tco
RM_TXD1, RM_TXD0
Preamble
SFD
DATA
CRC
Figure 31.35 RMII Transmit Timing
RM_REF-CLK Tsu RM_CRS-DV Tsu RM_RXD1, RM_RXD0 Preamble SFD RM_RX-ER L DATA CRC Thd Thd
Figure 31.36 RMII Receive Timing (Normal Operation)
RM_REF-CLK
RM_CRS-DV RM_RXD1, RM_RXD0 Preamble SFD DATA Tsu RM_RX-ER Thd XXXX
Figure 31.37 RMII Receive Timing (When an Error is Detected)
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Section 31 Electrical Characteristics
MDC tMDIOs MDIO tMDIOh
Figure 31.38 MDIO Input Timing
MDC tMDIOdh MDIO
Figure 31.39 MDIO Output Timing
RM_REF-CLK tWOLd WOL
Figure 31.40 WOL Output Timing
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Section 31 Electrical Characteristics
Table 31.15 USB Characteristics when On-Chip USB Transceiver is Used (USD+, USD- pin characteristics) Conditions: VCC = DrVCC = 3.0 V to 3.6 V, VSS = DrVSS = AVSS= 0 V, = 20 MHz to 34 MHz
Item Input Input high voltage Input low voltage Differential input sensitivity Differential common mode range Output Output high voltage Output low voltage Crossover voltage Rising time Falling time Ratio of rising time to falling time Output resistance Symbol VIH VIL VDI VCM VOH VOL VCRS tR tF tRFM ZDRV Min. 2.0 0.2 0.8 2.8 1.3 4 4 90 28 Max. 0.8 2.5 0.3 2.0 20 20 111.11 44 Unit Test Conditions V V V V V V V ns ns %
(TR/TF) Including RS = 22 IOH = -200 A IOL = 2 mA (D+) - (D-) Figures 31.40, 31.41
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Section 31 Electrical Characteristics
Rise time USD+, USDVCRS 10% Differential data lines tR 90%
Fall time 90% 10% tF
Figure 31.41 Data Signal Timing
USD+
RS = 22
Test point
CL = 50 pF
USD-
RS = 22
Test point
CL = 50 pF
Figure 31.42 Load Condition
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Section 31 Electrical Characteristics
Table 31.16 JTAG Timing Conditions: VCC = 3.0 V to 3.6 V, VSS = 0 V, = 20 MHz to 34 MHz
Item ETCK clock cycle time ETCK clock high pulse width ETCK clock low pulse width ETCK clock rise time ETCK clock fall time ETRST pulse width Reset hold transition pulse width ETMS setup time ETMS hold time ETDI setup time ETDI hold time ETDO data delay time Note: * When tcyc tTCKcyc Symbol Min. tTCKcyc tTCKH tTCKL tTCKr tTCKf tTRSTW tRSTHW tTMSS tTMSH tTDIS tTDIH tTDOD 29.4* 15 15 20 3 20 20 20 20 Max. 50* 5 5 20 ns Figure 31.44 tcyc Figure 31.43 Unit ns Test Conditions Figure 31.42
tTCKcyc
tTCKH
tTCKf
ETCK
tTCKL tTCKr
Figure 31.43 JTAG ETCK Timing
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Section 31 Electrical Characteristics
ETCK
RES ETRST
tRSTHW
tTRSTW
Figure 31.44 Reset Hold Timing
ETCK
tTMSS tTMSH
ETMS
tTDIS tTDIH
ETDI
tTDOD
ETDO
Figure 31.45 JTAG Input/Output Timing
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Section 31 Electrical Characteristics
31.4
A/D Conversion Characteristics
Table 31.17 lists the A/D conversion characteristics. Table 31.17 A/D Conversion Characteristics (AN7 to AN0 Input: 80/160-State Conversion) Condition A: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, AVref = 3.0 V to AVCC VSS = AVSS = 0 V, = 20 MHz Condition B: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, AVref = 3.0 V to AVCC, VSS = AVSS = 0 V, = 20 MHz to 34 MHz
Condition A Item Resolution Conversion time Min. 10 Typ. 10 Max. 10 4.0* 20 5 7.0 7.5 7.5 0.5 8.0
1
Condition B Min. 10 Typ. 10 Max. 10 4.7* 20 5 7.0 7.5 7.5 0.5 8.0
2
Unit Bits s pF k LSB
Analog input capacitance Permissible signalsource impedance Nonlinearity error Offset error Full-scale error Quantization error Absolute accuracy
Notes: 1. Value when using the maximum operating frequency in single mode of 80 states. 2. Value when using the maximum operating frequency in single mode of 160 states.
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Section 31 Electrical Characteristics
31.5
Flash Memory Characteristics
Table 31.18 lists the flash memory characteristics. Table 31.18 Flash Memory Characteristics Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Avref = 3.0 V to AVCC, VSS = AVSS = 0 V Ta = 0C to +75C (operating temperature range for programming/erasing in regular specifications)
Test Conditions
Item
124
Symbol
Min.
Typ.
Max.
Unit
Programming time* * * tP Erase time* * *
124

1 40 300 600 9.2 9.2 18.4
3
10 130 800 1500 24 24 48
ms/128 bytes ms/4-kbyte block ms/32-kbyte block ms/64-kbyte block s/512 kbytes Times Years Ta = 25C
tE
Programming time 124 (total)* * * Erase time (total)* * *
124
tP tE tPE NWEC
4
100* 10
Programming and 124 Erase time (total)* * * Reprogramming 5 count* Data retention time*
1000
tDRP
Notes: 1. Programming and erase time depends on the data. 2. Programming and erase time do not include data transfer time. 3. This value indicates the minimum number of which the flash memory are reprogrammed with all characteristics guaranteed. (The guaranteed value ranges from 1 to the minimum number.) 4. This value indicates the characteristics while the flash memory is reprogrammed within the specified range (including the minimum number). 5. Reprogramming count in each erase block.
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Section 31 Electrical Characteristics
31.6
Usage Notes
It is necessary to connect a bypass capacitor between the VCC pin and VSS pin and a capacitor between the VCL pin and VSS pin for stable internal step-down power. An example of connection is shown in figure 31.45.
Vcc power supply External capacitor for internal step-down power stabilization One 0.1 F / 0.47 F or two in parallel VSS VSS
Bypass capacitor
VCC
VCL
10 F
0.01 F
It is recommended that a bypass capacitor be connected to the VCC pin. (The values are reference values.) When connecting, place a bypass capacitor near the pin.
Do not connect Vcc power supply to the VCL pin. Always connect a capacitor for internal step-down power stabilization. Use one or two ceramic multilayer capacitor(s) (0.1 F / 0.47 F: connect in parallel when using two) and place it (them) near the pin.
Figure 31.46 Connecting Capacitors to VCC and VCL Pins
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Section 31 Electrical Characteristics
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Appendix
Appendix
A. I/O Port States in Each Processing State
I/O Port States in Each Processing State
MCU Operating Port Name Pin Name Port 1 A7 to A0 Mode EXPE Setting 0 / 1 (DDR=0) 1 (DDR=1) T T T T Reset T Hardware Software Sleep Mode kept kept* kept kept kept* kept T kept kept* kept T kept H T Program Execution State I/O port Address output I/O port I/O port Address output I/O port D15 to D8 I/O port A15 to A12 I/O port D7 to D4 I/O port WR, HWR Input port EXCL H T T T T T T kept kept kept T T T T T T kept output kept kept kept T T kept I/O port I/O port I/O port D3 to D0 Input port I/O port
Table A.1
Standby Mode Standby Mode T kept kept* kept kept kept*
Port 27 to 24 X Port 23 to 20 0 / 1 (DDR=0) A11 to A8 Port 3 D15 to D8 1 (DDR=1) 0 1
T
T
kept T
Port 47 to 44 0 A15 to A12 1
T
T
kept kept*
Port 43 to 40 0 / 1 (8 bits) D7 to D4 Port 57 WR, HWR Port 56 EXCL 1 (16 bits) 0 1 0 1 (DDR=0) 1 (DDR=1)
T
T
kept T
T
T
kept H
T
T
T
Port 55 to 50 X Port 67 to 64 X Port 63 to 60 0 / 1 (8 bits) D3 to D0 Port 7 Port 8 1 (16 bits) X X
Rev. 2.00 Aug. 20, 2008 Page 1165 of 1198 REJ09B0403-0200
Appendix
MCU Operating Port Name Pin Name Port 97 WAIT CS256 Port 96 Port 95 AS, IOS Port 94, 93 Port 92 HBE Port 91 AH Port 90 LBE Port A7 to A2 A23 to A18 Mode EXPE Setting 0 1 (CS256E=0) 1 (CS256E=1) X 0 1 X 0 1 0 / 1 (ADMXE=0) 1 (ADMXE=1) 0 1 0/1 (address 18=1) 1 (address 18=0) Port A1, A0 0/1 (address 13=1) A17, A16 1 (address 13=0) Port B Port C7 RD Port C6 LWR Port C5 to C0 X 0 1 0 / 1 (8 bits) 1 (16 bits) X T T T T T T T T kept kept H kept H kept kept kept H kept H kept I/O port I/O port RD I/O port LWR I/O port kept* kept* A17, A16 T T kept kept I/O port kept* kept* A23 to A18 T T T T T T T T T T T T T T Reset T Hardware Software Sleep Mode kept T H kept kept H kept kept H kept H kept H kept Program Execution State I/O port WAIT CS256 I/O port I/O port AS/IOS I/O port I/O port HBE I/O port AH I/O port LBE I/O port
Standby Mode Standby Mode T kept T H kept kept H kept kept H kept H kept H kept
Rev. 2.00 Aug. 20, 2008 Page 1166 of 1198 REJ09B0403-0200
Appendix
MCU Operating Port Name Pin Name Port D Port E Port F Mode EXPE Setting X X X Reset T T T Hardware Software Sleep Mode kept kept kept Program Execution State I/O port I/O port I/O port
Standby Mode Standby Mode T T T kept kept kept
[Legend] H: High level L: Low level T: High impedance kept: Input port pins are in the high-impedance state (when DDR = 0 and PCR = 1, the input pullup MOS remains on). Output port pins retain their states. Functions of some pins will be changed to the I/O port function, which is determined by DDR and DR, because the on-chip peripheral module associated with that pin function is initialized. DDR: Data direction register x: Don't care Note: * In the case of address output, the last address accessed is retained.
Rev. 2.00 Aug. 20, 2008 Page 1167 of 1198 REJ09B0403-0200
Appendix
B.
Product Lineup
Type Code
R4F2472 R4F2472 R4F2463 R4F2463 R4F2462 R4F2462
Product Type
H8S/2472 F-ZTAT version (regular specifications) F-ZTAT version (wide temperature specifications) H8S/2463 F-ZTAT version (regular specifications) F-ZTAT version (wide temperature specifications) H8S/2462 F-ZTAT version (regular specifications) F-ZTAT version (wide temperature specifications)
Mark Code
F2472VBR34V F2472VBR34DV F2463VTE34V F2463VTE34DV F2462VFQ34V F2462VFQ34DV
Package (Code)
176-pin LFBGA (PLBGA0176GA-A)
144-pin TQFP (PTQP0144LC-A)
144-pin LQFP (PLQP0144KA-A)
Rev. 2.00 Aug. 20, 2008 Page 1168 of 1198 REJ09B0403-0200
Appendix
C.
Package Dimensions
JEITA Package Code P-LFBGA176-13x13-0.80 RENESAS Code PLBG0176GA-A D wSA wSB Previous Code BP-176/BP-176V MASS[Typ.] 0.45g
x4
v
y1 S
S
A
y
S
e A
ZD
A1
E
P N M L K J H G F E D
e
R
Reference Dimension in Millimeters Symbol Min Nom Max
D B E v w A A1 e
ZE
13.0 13.0 0.15 0.20 1.40 0.35 0.45 0.40 0.80 0.50 0.45 0.55 0.08 0.10 0.2
C B A
b x y
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
y1 SD SE ZD ZE 0.90 0.90
b
x M S A B
Figure C.1 Package Dimensions (PLBGA0176GA-A)
Rev. 2.00 Aug. 20, 2008 Page 1169 of 1198 REJ09B0403-0200
Appendix
JEITA Package Code P-LQFP144-20x20-0.50 RENESAS Code PLQP0144KA-A Previous Code 144P6Q-A / FP-144L / FP-144LV MASS[Typ.] 1.2g
HD *1 108 D 73 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. bp b1
109
72
c1 HE E
c
Reference Symbol
*2
Dimension in Millimeters
Terminal cross section
1 ZD
A2
A
36 Index mark F
ZE
144
37
L L1
D E A2 HD HE A A1 bp b1 c c1 e x y ZD ZE L L1
*3 e y
bp
x
Detail F
Min Nom Max 19.9 20.0 20.1 19.9 20.0 20.1 1.4 21.8 22.0 22.2 21.8 22.0 22.2 1.7 0.05 0.1 0.15 0.17 0.22 0.27 0.20 0.09 0.145 0.20 0.125 0 8 0.5 0.08 0.10 1.25 1.25 0.35 0.5 0.65 1.0
Figure C.2 Package Dimensions (PLQP0144KA-A)
Rev. 2.00 Aug. 20, 2008 Page 1170 of 1198 REJ09B0403-0200
A1
c
Appendix
JEITA Package Code P-TQFP144-16x16-0.40 RENESAS Code PTQP0144LC-A Previous Code TFP-144/TFP-144V MASS[Typ.] 0.6g
HD
*1
D
108 109
73 72
NOTE: 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
bp
*2
HE
E
b1
c1
c
ZE
144 1 ZD Index mark 36
37
Reference Symbol
Dimension in Millimeters
Terminal cross section
F
e
*3
y
bp
x
M
A1
L L1
Detail F
D E A2 HD HE A A1 bp b1 c c1 e x y ZD ZE L L1
Min Nom Max 16 16 1.00 17.8 18.0 18.2 17.8 18.0 18.2 1.20 0.05 0.10 0.15 0.13 0.18 0.23 0.16 0.12 0.17 0.22 0.15 0 8 0.4 0.07 0.08 1.0 1.0 0.4 0.5 0.6 1.0
A
A2
Figure C.3 Package Dimensions (PTQP0144LC-A)
Rev. 2.00 Aug. 20, 2008 Page 1171 of 1198 REJ09B0403-0200
c
Appendix
Rev. 2.00 Aug. 20, 2008 Page 1172 of 1198 REJ09B0403-0200
Main Revisions and Additions in this Edition
Item Page Revision (See Manual for Details) Lineup of the H8S/2463 Group products added Section 1 Overview 1.1 Overview 1 Amended USB function module (USB)* 10-bit A/D converter Platform Environment Control Interface (PECI)* Boundary scan (JTAG) Clock pulse generator Notes: 1. Supported only by the H8S/2472 Group. 2. Supported only by the H8S/2472 Group and the H8S/2462 Group. 2 Added * On-chip memory
Model ROM RAM Remarks 176 pins, USB incorporated 144 pins, USB and PECI not incorporated 144 pins, USB not incorporated ROM Type Flash memory version
2 1
R4F2472 512 Kbytes 40 Kbytes R4F2463 512 Kbytes 40 Kbytes
R4F2462 512 Kbytes 40 Kbytes
*
Compact package
Body Size 13 x 13 mm 16 x 16 mm 20 x 20 mm Pin Pitch 0.8 mm 0.4 mm 0.5 mm
Package (code) PLBG0176GA-A PTQP0144LC-A PLQP0144KA-A
Rev. 2.00 Aug. 20, 2008 Page 1173 of 1198 REJ09B0403-0200
Item 1.2 Block Diagram Figure 1.1 Internal Block Diagram
Page 3
Revision (See Manual for Details) Amended
SCIF
Port 5
8-bit timer x 4
SSU
CRC calculator
FRT
Port 6
USB* 1 PECI* 2
Port A
M N P R P61 AVCC P76 15 AVref P75 P74 14 P77 P73 P71 13 P70 AVSS NC 12 PD3 PD1 PD2 11 PD6 PD4 PD5 10 PE1 VCC PE0 9 PE5 PE3 PE4 8 NC NC PE7 7 P83 P81 P82 6 P87 P86 P85 5 NC NC NC 4 PA2 PA1 PA0 3 VCC PA3 NC 2 PA6 N PA4 P NC R 1 M
IIC_0 to IIC_5
Port 7
[Legend] CPU: DTC: EVC: SCI: SCIF: IIC: EtherC: E-DMAC: SSU: USB: FRT: PWM: LPC: WDT: JTAG: PECI:
Port 8
Port 9
Central processing unit Data transfer controller Event counter Serial communication interface Serial communication interface with FIFO I2C bus interface Ethernet controller Direct memory access controller for Ethernet controller Synchronous serial communication unit USB function module 16-bit free running timer 14-bit PWM timer LPC interface Watchdog timer Boundary scan PECI interface
Notes: 1. Supported only by the H8S/2472 Group. 2. Supported only by the H8S/2472 Group and the H8S/2462 Group.
Figure 1.2 Pin 4 Assignments (H8S/2472 Group)
Replaced
A B C D E F G H J K L 15 P11 P13 P16 P21 P24 P27 PF1 ETDI
PUPDPLS
USD-
P67
P64
14
P10
P12
P14
P20
P23
P26
PF0
ETCK
VBUS
USD+
P66
P62
13
PB5
PB7
VSS
P17
P25
VSS
PF2
ETD0
DrVSS
DrVCC
P65
P60
12
PB2
PB4
PB6
P15
P22
NC
ETRST
ETMS
NC
VCC
P63
P72
11
VCC
PB0
PB1
PB3
PD0
10
P32
P33
P31
P30
PD7
9
P36
P37
P35
P34
PE2
8
P42
P43
P41
P40
H8S/2472 Group PLBG0176GA-A BP-176V (Top view)
PE6
7
P52
P53
PECI
PEVref
P80
6
P55
P44
P54
FWE
P84
5
UXTAL UEXTAL
VCC
UXSEL
UXSEL
F
PEVref
P34
P30
PB3
VSS
4
PF5
PF4
NC
PF3
RES
NC
P50
P94
P91
PC6
PC1
PA5
3
VSS
RESO
P45
P56
PF6
VCL
P97
P93
P90
PC5
NC
PA7
2
XTAL
EXTAL
P47
VSS
NMI
P51
P95
P92
PC7
PC3
NC
PC0
1
VCC A
P46 B
P57 C
MD1 D
STBY E
MD2 F
P96 G
NC H
NC J
PC4 K
PC2 L
NC
: NC pin
5 Figure 1.3 Pin Assignments (H8S/2463 Group)
Added
Rev. 2.00 Aug. 20, 2008 Page 1174 of 1198 REJ09B0403-0200
Port B
Item
Page
Revision (See Manual for Details) Modified
P32/ExDB2/D10 123 P33/ExDB3/D11 124 P34/ExDB4/D12 125 P35/ExDB5/D13 126 P36/ExDB6/D14 127 P37/ExDB7/D15 128 P40/IRQ0/RS0/HC0/D4 129 P41/IRQ1/RS1/HC1/D5 130 P42/IRQ2/RS2/HC2/D6 131 P43/IRQ3/RS3/HC3/D7 132 PEVref 133 PECI 134 P52/IRQ10/TxD1 135 P53/IRQ11/RxD1 136 FWE 137 P54/IRQ12/SSO 138 P55/IRQ13/SSI 139 P44/IRQ4/RS4/DB4/HC4/A12/AD12 140 VSS 141 RESO 142 XTAL 143 EXTAL 144 12 3 4 567 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
Figure 1.4 Pin 6 Assignments (H8S/2462 Group)
H8S/2462 Group PLQP0144KA-A FP-144LV (Top view)
58 PE0/LAD0 57 PE1/LAD1 56 PE2/LAD2 55 PE3/LAD3 54 PE4/LFRAME 53 PE5/LRESET 52 PE6/LCLK 51 PE7/SERIRQ 50 P80/SCL0 49 P81/SDA0 48 P82/SCL1 47 P83/SDA1 46 P84/ExIRQ12/SCK3 45 P85/ExIRQ13/SCK1 44 P86/ExIRQ14/RxD3 43 P87/ExIRQ15/TxD3/ADTRG 42 VSS 41 PA0/ExIRQ0/EVENT0/A16 40 PA1/ExIRQ1/EVENT1/A17 39 PA2/ExIRQ2/EVENT2/A18 38 PA3/ExIRQ3/EVENT3/A19 37 PA4/ExIRQ4/EVENT4/A20
VCC
NMI
STBY
RES
VSS
P45/IRQ5/RS5/DB5/HC5/A13/AD13
P46/IRQ6/RS6/DB6/HC6/A14/AD14
P47/IRQ7/RS7/DB7/HC7/A15/AD15
PF6/ExPWX2/RS14
MD2
PA7/ExIRQ7/EVENT7/EXOUT/A23
PA6/ExIRQ6/EVENT6/LNKSTA/A22
PC4/SCL4
PC2/SCL3
PC0/SCL2
Table 1.1 Pin Assignments in Each Operating Mode
7,13
H8S/2463 added Pin No. H8S/2462 (FP-144LV) 1 144 H8S/2463 (TFP-144V) 1 144 H8S/2472 (BP-176V) A1 B2
7
Added Pin No. H8S/2462 (FP-144LV) 17 Pin Name Extended Mode (EXPE=1) P97/CS256/WAIT
Table 1.2 Pin Functions 14, 18
H8S/2463 added
Pin No. Type Power supply Symbol VCC H8S/2462 H8S/2463 H8S/2472 144-Pin 144-Pin 176-Pin 1, 36, 86, 120 139 84 1, 36, 86, 120 137 83 A1, N2, P9, K12, A11, C5 A6 L14
Synchronous serial communication unit (SSU)
SSI SCS
Rev. 2.00 Aug. 20, 2008 Page 1175 of 1198 REJ09B0403-0200
PA5/ExIRQ5/EVENT5/WOL/A21
P56/EXCL/
P57/WR/HWR
P91/AH
P51/IRQ9/RxDF
P97/CS256/WAIT
P94/ExPWX1
P50/IRQ8/TxDF
P93/ExPWX0
PC7/RD
PC6/LWR
PC5/SDA4
PC3/SDA3
P95/AS/IOS
PC1/SDA2
P92/HBE
P90/LBE
VCC
MD1
VCL
P96
Item Section 3 MCU Operating Modes 3.2.3 Serial Timer Control Register (STCR)
Page 67
Revision (See Manual for Details) Added
Initial Bit 3 Bit Name Value FLSHE 0 R/W R/W Description Flash Memory Control Register Enable Enables or disables CPU access for flash memory registers (FCCS, FPCS, FECS, FKEY, FMATS, FTDAR), control registers of power-down states (SBYCR, LPWRCR, MSTPCRH, MSTPCRL), and control registers of on-chip peripheral modules (BCR2, WSCR2, PCSR, SYSCR2). 0: Area from H'FFFE88 to H'FFFE8F is reserved. Area from H'FFFEA0 to H'FFFEBF is allocated to registers of AD, serial multiplexed functions, and I/O ports. Area from H'FFFF80 to H'FFFF87 is allocated to control registers of powerdown states and on-chip peripheral modules. 1: Area from H'FFFE88 to H'FFFE8F is allocated to control registers of flash memory. Area from H'FFFEA0 to H'FFFEBF is reserved. Area from H'FFFF80 to H'FFFF87 is reserved.
Section 4 Exception Handling 4.3.3 On-Chip Peripheral Modules after Reset is Cancelled
75
After a reset is cancelled, the module stop control registers (MSTPCR, MSTPCRA, and SUBMSTPB, and SUBMSTPA) are initialized, ...
Rev. 2.00 Aug. 20, 2008 Page 1176 of 1198 REJ09B0403-0200
Item Section 5 Interrupt Controller Table 5.2 Correspondence between Interrupt Source and ICR
Page 82
Revision (See Manual for Details) Amended
Register Bit 7 2 1 0 ICRC SCI_3 IIC_2, IIC_3 LPC USB*
1
ICRD IRQ8 to IRQ11 PECI*2 SCIF --
[Legend] n: A to D : Reserved. The write value should always be 0. Notes: 1. Supported only by the H8S/2472 Group. 2. Supported only by the H8S/2472 Group and the H8S/2462 Group. Table 5.3 Interrupt Sources, Vector Addresses, and Interrupt Priorities 92 Amended
Origin of Interrupt Source PECI*2 USB*1
Notes: 1. Supported only by the H8S/2472 Group. 2. Supported only by the H8S/2472 Group and the H8S/2462 Group. Section 8 I/O Ports 8.1 I/O Ports for the H8S/2472 Group 189 Description amended Table 8.1 is a summary of the port functions. ... For port A pins and D0 to D5 pins, the on/off status of the input pull-up MOS is controlled by their respective DDR and the output data register (ODR). Ports 1 to 4, and 6 have an input pull-up MOS control register (PCR), ... 237 Deleted * P97/WAIT/CS256 The pin function is switched as shown below according to the operating mode and the combination of the CS256E bit in SYSCR, the WMS1 bit in WSCR, the WMS21 bit in WSCR2, and the P97DDR bit.
Operating Mode WMS1, WMS21 Extended mode All 0 Either bit is 1
8.1.9 Port 9 (3) Pin Functions
Rev. 2.00 Aug. 20, 2008 Page 1177 of 1198 REJ09B0403-0200
Item 8.1.10 Port A
Page 243
Revision (See Manual for Details) Amended * PA5/ExIRQ5/EVENT5/A21/WOL The pin function is switched as shown below according to the setting of the address 18, and the PA5DDR bit. Setting the ISS5 bit in ISSR to 1 makes the pin function as the ExIRQ5 input pin. When using the pin as the ExIRQ5 input, or an EVENT input pin, clear the PA5DDR bit to 0. Though the settings for the EVENT input pin have been made, set the PA5DDR bit to 1 when using the pin as the A21 or PA5 output pin. When the module stop mode is cleared in both the EtherC, and E-DMAC, this pin functions as the WOL output pin.
8.1.15 Port F
271
Amended * PF1/RS9/MDC, PF0/RS8/MDIO
Ether of them is stopped 0 PFn input pin 1 PFn output pin Both of them are stopped X MDC output pin/ MDIO input/output pin
EtherC, E-DMAC PFnDDR Pin function
8.2 I/O Ports for the H8S/2463 Group and the H8S/2462 Group
272
Title and description amended Table 8.9 is a summary of the port functions. ... For port A pins and D0 to D5 pins, the on/off status of the input pull-up MOS is controlled by their respective DDR and the output data register (ODR). Ports 1 to 4, and 6 have an input pull-up MOS control register (PCR), ...
8.2.9 Port 9 (3) Pin Functions
321
Deleted * P97/WAIT/CS256 The pin function is switched as shown below according to the operating mode and the combination of the CS256E bit in SYSCR, the WMS1 bit in WSCR, the WMS21 bit in WSCR2, and the P97DDR bit.
Operating Mode WMS1, WMS21 Extended mode All 0 Either bit is 1
Rev. 2.00 Aug. 20, 2008 Page 1178 of 1198 REJ09B0403-0200
Item 8.2.10 Port A
Page 327
Revision (See Manual for Details) Amended * PA5/ExIRQ5/EVENT5/A21/WOL The pin function is switched as shown below according to the setting of the MPDE bit in ECMR in EtherC, the address 18, and the PA5DDR bit. Setting the ISS5 bit in ISSR to 1 makes the pin function as the ExIRQ5 input pin. When using the pin as the ExIRQ5 input, or an EVENT input pin, clear the PA5DDR bit to 0. Though the settings for the EVENT input pin have been made, set the PA5DDR bit to 1 when using the pin as the A21 or PA5 output pin. When the module stop mode is cleared in both the EtherC and E-DMAC, this pin functions as the WOL output pin.
8.2.15 Port F
355
Amended * PF1/RS9/MDC
Either of them is stopped 0 PF1 input pin 1 PF1 output pin Both of them are stopped X MDC output pin
EtherC, E-DMAC PF1DDR Pin function
Section 10 16-Bit FreeRunning Timer (FRT) Figure 10.3 Timing of Output Compare A Output Section 12 Watchdog Timer (WDT) 12.3.2 Timer Control/ Status Register (TCSR) * TCSR_0
383
Replaced
418
Amended Bit 4 Bit Name Initial Value 0 R/W R/W
Rev. 2.00 Aug. 20, 2008 Page 1179 of 1198 REJ09B0403-0200
Item * TCSR_1
Page 420
Revision (See Manual for Details) Amended
Bit 5 Bit Name TME Description Timer Enable When this bit is set to 1, TCNT starts counting. When this bit is cleared, TCNT stops counting and is initialized to H'00. When PSS = 1, TCNT is not initialized. Write H'00 to TCNT to initialize TCNT.
Section 15 Serial Communication Interface with FIFO (SCIF) 15.3 Register Descriptions Table 15.2 Register Access
510
Register name amended * Sub-chip module stop control register BL (SUBMSTPBL)
510
Description in this table amended
SCIFE Bit in HICR5 Bit 3 in SUBMSTPBL 0 0 1
Figure 15.4 Example of Data Transmission Flowchart
531
Modified
[1] Confirm that the THRE flag in FLSR is 1, and write transmit data to FTHR. When FIFOs are used, write 1-byte to 16-byte transmit data. When the OUT2 bit in FMCR and the ETBEI bit in FIER are set to 1, an FTHR empty interrupt occurs. When data is written to FTHR, it is transferred automatically to FTSR. The data is then transmitted from the TxDF pin in the order of the start bit, transmit data, parity bit, and stop bit.
Figure 15.5 Example of DATA Reception Flowchart
532
Modified
Yes Read RXFIFOERR, BI, PE and OE flag in FLSR [2]
RXFIFOERR = 1, BI = 1, FE = 1, PE = 1, or OE = 1 No
Yes
Error processing
[3]
Read FRBR
Read DR flag in FLSR
[4]
Rev. 2.00 Aug. 20, 2008 Page 1180 of 1198 REJ09B0403-0200
Item Section 19 LPC Interface (LPC) 19.3.1 Host Interface Control Registers 0 and 1 (HICR0 and HICR1) * HICR1
Page 678
Revision (See Manual for Details) Amended
Bit 0 Bit Name LSCIB Description LSCI output Bit Controls LSCI output in combination with the LSCIE bit. For details, refer to description on the LSCIE bit in HICR0.
Figure 19.11 Clock Start 749 Request Timing
Amended
LCLK
1 2 3 4 5 6
CLKRUN
Pull-up enable
Driven by the slave processor
Driven by the host processor
Table 19.14 Host Address Example
755
Amended
Register Host Address when LADR3 = H'A24F Host Address when LADR3 = H'3FD0
Section 20 Ethernet Controller (EtherC) Table 20.1 Pin Configuration
759
Amended and added
Type Abbreviation I/O Output Function Management Data Clock Reference clock signal for information transfer via MDIO EXOUT Output External Output
PHY register MDC interface signals Others
Figure 20.10 1-Bit Data Read Flowchart
784
Modified
(1) Write to PHY interface register MMD = 0 MDC = 1 (2) Write to PHY interface register read MMD = 0 MMC = 1 MDI is read data
Rev. 2.00 Aug. 20, 2008 Page 1181 of 1198 REJ09B0403-0200
Item Section 21 Ethernet Controller Direct Memory Access Controller (E-DMAC) 21.2.8 Transmit/Receive Status Copy Enable Register (TRSCER)
Page 806
Revision (See Manual for Details) Amended TRSCER specifies whether or not transmit and receive status information reported by bits 7 and 4 in the EtherC/E-DMAC status register is to be indicated in bit RFE in the corresponding descriptor. Bits in this register correspond to bits 7 and 4 in the EtherC/E-DMAC status register (EESR). When a bit is cleared to 0, the transmit status (bits 11 to 8 in EESR) is indicated in bits TFS3 to TFS0 in the transmit descriptor, and the receive status (bits 7 and 4 in EESR) is indicated in bit RFE of the receive descriptor. When a bit is set to 1, the occurrence of the corresponding interrupt is not indicated in the descriptor. After this LSI is reset, all bits are cleared to 0.
Initial Bit Bit Name value All 0 R/W R Description Reserved These bits are always read as 0. The initial value should not be changed. 7 RMAFCE 0 R/W RMAF Bit Copy Directive 0: Indicates the RMAF bit state in bit RFE of the receive descriptor 1: Occurrence of the corresponding interrupt is not indicated in bit RFE of the receive descriptor 6, 5 All 0 R Reserved These bits are always read as 0. The initial value should not be changed. 4 RRFCE 0 R/W RRF Bit Copy Directive 0: Indicates the RRF bit state in bit RFE of the receive descriptor 1: Occurrence of the corresponding interrupt is not indicated in bit RFE of the receive descriptor 3 to 0 All 0 R Reserved These bits are always read as 0. The initial value should not be changed.
31 to 8
Rev. 2.00 Aug. 20, 2008 Page 1182 of 1198 REJ09B0403-0200
Item 21.3.1 Descriptor List and Data Buffers (1) Transmit Descriptor (a) Transmit Descriptor 0 (TD0)
Page 818
Revision (See Manual for Details) Amended
Bit 27 Bit Name TFE Initial value 0 R/W R/W Description Transmit Frame Error Indicates that one or other bit of the transmit frame status indicated by bits 26 to 0 is set. Whether or not the transmit frame status information is copied into this bit is specified by the transmit/receive status copy enable register. 0: No error during transmission 1: An error occurred during transmission 26 to 0 TFS26 All 0 to TFS0 R/W Transmit Frame Status TFS26 to TFS9: Reserved (The write value should always be 0.) TFS8: Transmit Abort Detection (indicates any of bits TFS3 to TFS0 has been set.) TFS7 to TFS4: Reserved (The write value should always be 0.) TFS3: Carrier Not Detected (corresponds to CND bit in EESR) TFS2: Detect Loss of Carrier (corresponds to DLC bit in EESR) TFS1: Delayed Collision Detect (corresponds to CD bit in EESR) TFS0: Transmit Retry Over (corresponds to TRO bit in EESR)
Rev. 2.00 Aug. 20, 2008 Page 1183 of 1198 REJ09B0403-0200
Item 21.3.1 Descriptor List and Data Buffers (2) Receive Descriptor (a) Receive Descriptor 0 (RD0)
Page 823
Revision (See Manual for Details) Amended
Bit 26 to 0 Bit Name Initial value R/W R/W Description Receive Frame Status These bits indicate the error status during frame reception. ... RFS8: Abort Detection (indicates any of bits RFS3 to RFS0 has been set.) ...
RFS26 to All 0 RFS0
22.10.7 Restrictions on 892 Peripheral Module Clock () Operating Frequency Section 23 A/D Converter Figure 23.1 Block Diagram of the A/D Converter 894
Modified When UXSEL is set to 0, connect USEXTAL to the system power supply (0 V). Added
AVCC AVref* AVSS 10-bit D/A
Note: * Supported only by the H8S/2472 Group and the H8S/2462 Group.
Table 23.1 Pin Configuration
895
Added
Pin Name Reference power supply pin Function Reference voltage for A/D converter Supported only by the H8S/2472 Group and the H8S/2462 Group.
Rev. 2.00 Aug. 20, 2008 Page 1184 of 1198 REJ09B0403-0200
Item Section 25 Flash Memory 25.7 Programmer Mode
Page 985
Revision (See Manual for Details) Description amended ... , this LSI also has a programmer mode as a further mode for the programming and erasing of programs and data. In the programmer mode, a general-purpose PROM programmer, which supports microcomputers with 256-Kbyte or 512-Kbyte 1 flash memory as a device type* , can freely be used to write programs to the on-chip ROM. ... In programmer mode, provide a 6-MHz input-clock signal.
25.8 Serial Communication Interface Specification for Boot Mode (4) Inquiry and Selection States (b) Device Selection (9) Programming/ Erasing State (b) 128-byte programming
992
Amended * Size (1 byte): Amount of device-code data This is fixed at 4
1006
Amended * Programming Address (4 bytes): Start address for programming ... (i.e. H'00, H'01, H'00, H'00 : H'00010000)
Rev. 2.00 Aug. 20, 2008 Page 1185 of 1198 REJ09B0403-0200
Item Section 26 Boundary Scan (JTAG) Table 26.1 Pin Configuration
Page
1019
Revision (See Manual for Details) Deleted
Pin Name Test clock Function Test clock inputProvides an independent clock supply to the JTAG. As the clock input to the ETCK pin is supplied directly to the JTAG, a clock waveform with a duty cycle close to 50% should be input. For details, see section 31, Electrical Characteristics. If there is no input, the ETCK pin is fixed to 1 by an internal pull Test mode select input Sampled on the rise of the ETCK pin. The ETMS pin controls the internal state of the TAP controller. If there is no input, the ETMS pin is fixed to 1 by an internal pull Serial data inputPerforms serial input of instructions and data for JTAG registers. ETDI is sampled on the rise of the ETCK pin. If there is no input, the ETDI pin is fixed to 1 by an internal pull Serial data outputPerforms serial output of instructions and data from JTAG registers. Transfer is performed in synchronization with the ETCK pin. If there is no output, the ETDO pin goes to the high Test reset input signalInitializes the JTAG asynchronously. If there is no input, the ETRST pin is fixed to 1 by an internal pull
Test mode select
Test data input
Test data output
Test reset
Table 26.3 1025, Correspondence 1029 between Pins and Boundary Scan Register (H8S/2472 Group)
Amended
Pin No. R6 Pin Name P82 Input/Output Input Enable Output D13 P17 Input Enable Output Bit No. 231 230 229 108 107 106
Rev. 2.00 Aug. 20, 2008 Page 1186 of 1198 REJ09B0403-0200
Item
Page
Revision (See Manual for Details) Description added Though the pin no. for the H8S/2462 Group and the H8S/2463 Group differs, the bit no. for these products is the same. The following table is listed with the pin no. of the H8S/2462 Group. Amended
Pin No. 35 Pin Name PA5 Input/Output Input Enable Output 36 VCC -- -- -- Bit No. 251 252 249 -- -- --
Table 26.4 1031 Correspondence between Pins and Boundary Scan Register (H8S/2462 Group and H8S/2463 Group)
1033
26.6 Usage Notes
1045
Deleted 1. A reset must always be executed by driving the ETRST pin to 0, regardless of whether or not the JTAG is to be activated. ... If the JTAG is not to be activated, drive the ETRST, ETCK, ETMS, and ETDI pins to 1 or the high-impedance state. These pins are internally pulled up and are noted in standby mode.
Section 28 Power-Down 1062 Modes 28.1.4 Sub-Chip Module Stop Control Registers BH, BL (SUBMSTPBH, SUBMSTPBL)
Amended * SUBMSTPBL
Corresponding Module PECI This bit is not incorporated in the H8S/2463 Group. The initial values should not be changed. Bit Name SMSTPB4
Section 29 List of Registers 29.1 Register Addresses (Address Order)
1085
Added Notes: 1. The registers related to USB are supported only by the H8S/2472 Group. 2. The registers related to PECI are supported only by the H8S/2472 Group and the H8S/2462 Group.
Rev. 2.00 Aug. 20, 2008 Page 1187 of 1198 REJ09B0403-0200
Item 29.2 Register Bits
Page
1089, 1103
Revision (See Manual for Details) Amended
Register Abbreviation TRSCER Bit 3 Bit 2 Bit 1 Bit 0 Module E-DMAC
Notes: The registers related to USB are supported only by the H8S/2472 Group. The registers related to PECI are supported only by the H8S/2472 Group and the H8S/2462 Group. 29.3 Register States in Each Operating Mode
1116
Added Notes: 1. The registers related to USB are supported only by the H8S/2472 Group. 2. The registers related to PECI are supported only by the H8S/2472 Group and the H8S/2462 Group.
Section 30 Platform Environment Control Interface (PECI) Section 31 Electrical Characteristics Table 31.1 Absolute Maximum Ratings Table 31.10 Timing of On-Chip Peripheral Modules
1117
Added If this module is not used, the PECI-related pins should be handled as follows. PECI is not supported by the H8S/2463 Group.
1119
Amended
Item Symbol Value -0.3 to +1.5
PECI reference power supply voltage PEVref 1145
Item added
Item SCI (multiplexed with P51) Symbol Receive data setup time tRXS (synchronous) Receive data hold time (synchronous) tRXH Min. 30.0 30.0 Max.
Figure 31.30 SSU Timing (Slave, CPHS = 1) Table 31.16 JTAG Timing
1149
Figure title amended
1159
Amended
Item ETCK clock cycle time Symbol tTCKcyc Min. 29.4* Max. 50*
Rev. 2.00 Aug. 20, 2008 Page 1188 of 1198 REJ09B0403-0200
Item Appendix B. Product Lineup
Page
1168
Revision (See Manual for Details) Amended and added
Product Type H8S/2472 F-ZTAT version (wide temperature specifications) Type Code Mark Code R4F2472 F2472VBR34DV
H8S/2463 F-ZTAT version R4F2463 (regular specifications) F-ZTAT version (wide temperature specifications) H8S/2462 F-ZTAT version (wide temperature specifications) R4F2463
F2463VTE34V F2463VTE34DV
R4F2462
F2462VFQ34DV
Figure C.3 Package Dimensions (PTQP0144LC-A)
1171
Added
Rev. 2.00 Aug. 20, 2008 Page 1189 of 1198 REJ09B0403-0200
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Index
Numerics
14-bit PWM timer (PWMX)................... 359 16-bit count mode................................... 408 16-bit free-running timer (FRT) ............. 375 16-bit, 2-state access space ..................... 133 16-bit, 3-state access space ..................... 136 256-kbyte expansion area ....................... 121 8-bit timer (TMR)................................... 393 8-bit, 2-state access space ....................... 131 8-bit, 3-state access space ....................... 132
B
Basic expansion area............................... 120 Basic operation timing ............................ 154 Bcc ...................................................... 41, 49 Bit rate .................................................... 447 Block transfer mode................................ 180 Boot mode............................................... 946 Boundary scan....................................... 1042 Bulk-in transfer ....................................... 877 Bulk-out transfer ..................................... 876 Burst ROM interface............................... 154 Bus Controller (BSC).............................. 107 Bus specifications of basic bus interface ............................................ 120
A
A/D conversion time............................... 903 A/D converter ......................................... 893 Accessing MII registers .......................... 782 Acknowledge .......................................... 620 Activation by interrupt............................ 185 Activation by software............................ 185 Address map ............................................. 69 Address ranges and external address spaces......................................... 119 Address space ........................................... 32 Addressing modes..................................... 53 Absolute address................................... 54 Immediate ............................................. 55 Memory indirect ................................... 56 program-counter relative ...................... 55 Register direct....................................... 53 Register indirect.................................... 53 Register indirect with displacement...... 54 Register indirect with post-Increment... 54 Register indirect with pre-decrement.... 54 ADI ......................................................... 907 Advanced mode ...................................... 125 Asynchronous mode ............................... 451
C
Cascaded connection............................... 408 Chain transfer.......................................... 181 Clock pulse generator ........................... 1049 Clock synchronous communication mode ....................................................... 579 Clocked synchronous mode .................... 468 CMIA...................................................... 409 CMIA0 .................................................... 409 CMIA1 .................................................... 409 CMIAX ................................................... 409 CMIAY ................................................... 409 CMIB ...................................................... 409 CMIB0 .................................................... 409 CMIB1 .................................................... 409 CMIBX ................................................... 409 CMIBY ................................................... 409 Communications protocol....................... 988 Compare-match count mode ................... 408 Condition field .......................................... 52 Condition-code register (CCR) ................. 36
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Control transfer....................................... 870 Conversion cycle .................................... 367 CPU operating modes Advanced mode .................................... 30 CPU operating modes ............................... 28 Normal mode ........................................ 28 CRC operation circuit ............................. 499 Crystal oscillator................................... 1050
Flash multipurpose address area parameter ................................................ 940 Flash multipurpose data destination parameter ................................................ 940 Flash pass/fail parameter......................... 944 Flash programming/erasing frequency parameter ................................................ 938 Flow control............................................ 786 FOVI ....................................................... 386 Framing error .......................................... 458
D
Data direction register .................... 189, 272 Data register.................................... 189, 272 Data stage ............................................... 872 Data transfer controller (DTC) ............... 161 Download pass/fail result parameter....... 936 DTC vector table .................................... 175
G
General registers ....................................... 34
H
Hardware protection................................ 980 Hardware standby mode ....................... 1069
E
Effective address................................. 53, 57 Effective address extension ...................... 52 ERI1........................................................ 489 ERI2........................................................ 489 Error protection ...................................... 982 EtherC receiver ....................................... 779 EtherC transmitter................................... 776 Ethernet controller (EtherC) ................... 757 Ethernet controller direct memory access controller (E-DMAC) .................. 791 Exception handling ................................... 71 Exception handling vector table ............... 72 Extended control register (EXR) .............. 35 External clock ....................................... 1051
I
I/O ports .................................................. 189 I/O select signals ..................................... 126 I2C bus formats ....................................... 619 I2C bus interface (IIC)............................. 587 Input pull-up MOS control register ............................................ 189, 272 Input pull-up MOSs ........................ 189, 272 Instruction set............................................ 41 Arithmetic operations instructions ........ 44 Bit manipulation instructions ................ 47 Block sata transfer instructions ............. 51 Branch instructions ............................... 49 Data transfer instructions ...................... 43 Logic operations instructions ................ 46 Shift instructions ................................... 46 System control instructions ................... 50 Interface .................................................. 431 Internal block diagram ................................ 3
F
Flash erase block select parameter.......... 943 Flash MAT configuration ....................... 919
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Interrupt control modes ............................ 93 Interrupt controller.................................... 79 Interrupt exception handling..................... 76 Interrupt exception handling sequence ... 100 Interrupt exception handling vector table ............................................... 90 Interrupt mask bit...................................... 36 interrupt mask level .................................. 35 Interrupt-in transfer................................. 879 Interval timer mode ................................ 424 IRQ15 to IRQ0 interrupts ......................... 88
O
OCIA....................................................... 386 OCIB....................................................... 386 On-board programming .......................... 945 On-board programming mode................. 915 Operating modes ....................................... 63 Operation by IPG setting ........................ 786 Operation field .......................................... 52 Output compare....................................... 383 Overflow ................................................. 422 Overrun error .......................................... 458 OVI0 ....................................................... 409 OVI1 ....................................................... 409 OVIX ...................................................... 409 OVIY ...................................................... 409
L
LPC interface (LPC) ............................... 665 LPC interface clock start request ............ 749 LSI internal states in each mode........... 1064
P M
Magic Packet detection........................... 785 Master receive operation......................... 625 Master transmit operation ....................... 621 Medium-speed mode ............................ 1065 MII frame timing .................................... 780 Mode comparison ................................... 918 Mode transition diagram....................... 1063 Module stop mode ................................ 1070 Multi-buffer frame transmit/ receive processing................................... 829 Multiply-accumulate register (MAC) ....... 37 Multiprocessor communication function................................................... 462 Parity error .............................................. 458 PDM...................................................... 1055 Pin arrangement .......................................... 4 Pin functions ............................................. 14 Procedure program.................................. 970 Program counter (PC) ............................... 35 Programmer mode................................... 985 Programming/erasing interface register .................................................... 926 Protection ................................................ 980
R
RAM ............................................. 913, 1117 Receive descriptor 0 (RD0)..................... 821 Receive descriptor 1 (RD1)..................... 824 Receive descriptor 2 (RD2)..................... 824 Register field............................................. 52 Registers ABRKCR .............................................. 82 ADCR ................................................. 899 ADCSR ............................................... 897
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N
NMI interrupt............................................ 88 Normal mode .................................. 178, 186 Number of DTC execution states ........... 184
ADDR................................................. 896 APR .................................................... 774 BARA ................................................... 83 BARB ................................................... 83 BARC ................................................... 83 BRR .................................................... 447 BTCR.................................................. 727 BTCSR ............................................... 724 BTDTR ............................................... 730 BTFVSR ............................................. 732 BTIMSR ............................................. 730 BTSR .................................................. 718 CDCR ................................................. 771 CEFCR ............................................... 772 CNDCR .............................................. 771 CRA.................................................... 166 CRB .................................................... 166 CRCCR............................................... 500 CRCDIR ............................................. 501 CRCDOR............................................ 501 CTLR.................................................. 852 CVR.................................................... 852 DACNT .............................................. 361 DACR ................................................. 364 DADRA.............................................. 362 DADRB .............................................. 362 DAR.................................................... 165 DASTS ............................................... 846 DMA................................................... 848 DTCER ............................................... 166 DTCERA ............................................ 167 DTCERB ............................................ 167 DTCERC ............................................ 167 DTCERD ............................................ 167 DTCERE............................................. 167 DTVECR ............................................ 167 ECMR................................................. 761 ECSIPR............................................... 766 ECSR .................................................. 764 EDMR................................................. 794
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EDRRR ............................................... 796 EDTRR ............................................... 795 EESIPR ............................................... 803 EESR................................................... 798 EPDR .................................................. 843 EPDR0i ............................................... 841 EPDR0o .............................................. 842 EPDR0s............................................... 842 EPIR.................................................... 854 EPSTL................................................. 851 EPSZ0o ............................................... 844 EPSZ1 ................................................. 844 FCCS................................................... 926 FCFTR ................................................ 812 FCLR .................................................. 847 FDLH .................................................. 512 FDLL .................................................. 512 FDR..................................................... 809 FECS................................................... 930 FFCR................................................... 516 FIER.................................................... 513 FIIR..................................................... 514 FKEY .................................................. 931 FLCR .................................................. 517 FLSR................................................... 520 FMATS ............................................... 932 FMCR ................................................. 518 FMSR.................................................. 524 FPCS ................................................... 930 FRBR .................................................. 511 FRC..................................................... 377 FRECR................................................ 772 FRSR................................................... 511 FSCR................................................... 525 FTDAR ............................................... 933 FTHR .................................................. 512 FTSR................................................... 511 HICR................................................... 671 HISEL ................................................. 711 ICCR ................................................... 600
ICDR................................................... 591 ICMR.................................................. 595 ICRA..................................................... 82 ICRB..................................................... 82 ICRC..................................................... 82 ICRD..................................................... 82 ICSMBCR .......................................... 617 ICSR ................................................... 609 ICXR................................................... 613 IDR ..................................................... 689 IER........................................................ 86 IER (USB) .......................................... 840 IER16.................................................... 86 IFR (USB) .......................................... 834 IIC3..................................................... 597 IPGR ................................................... 774 ISCR ..................................................... 84 ISCR16H .............................................. 84 ISCR16L............................................... 84 ISCRH .................................................. 85 ISCRL................................................... 85 ISR........................................................ 87 ISR (USB) .......................................... 838 ISR16.................................................... 87 ISSR.................................................... 356 ISSR16................................................ 356 KBCOMP ........................................... 163 LADR12 ............................................. 684 LADR3 ............................................... 686 LCCR.................................................. 771 LPCPD................................................ 743 LPWRCR.......................................... 1059 MAFCR .............................................. 773 MAHR ................................................ 768 MALR................................................. 768 MDCR .................................................. 64 MPR.................................................... 775 MRA ................................................... 164 MRB ................................................... 165 MSTPCRA ....................................... 1061
MSTPCRH........................................ 1060 MSTPCRL ........................................ 1060 NCCS .......... 205, 211, 251, 288, 294, 335 OCRA ................................................. 377 OCRAF ............................................... 378 OCRAR............................................... 378 OCRB.................................................. 377 ODR .................................................... 689 P1DDR........................................ 194, 277 P1DR........................................... 195, 278 P1PCR......................................... 195, 278 P2DDR........................................ 197, 280 P2DR........................................... 198, 281 P2PCR................................. 198, 281, 306 P3DDR................................ 202, 285, 332 P3DR................................... 203, 286, 333 P3NCE ........................................ 204, 287 P3NCMC .................................... 204, 287 P3PCR......................................... 203, 286 P4BNCE...................... 210, 250, 293, 334 P4BNCMC.................. 211, 250, 294, 334 P4DDR........................................ 208, 291 P4DR........................................... 209, 292 P4PCR......................................... 210, 293 P5DDR........................................ 216, 299 P5DR........................................... 217, 300 P6DDR........................................ 221, 304 P6DR........................................... 222, 305 P6PCR................................................. 223 P7PIN.................................. 227, 311, 333 P8DDR................................ 231, 315, 320 P8DR................................... 232, 316, 321 P9DDR................................................ 236 P9DR................................................... 237 PADDR ....................................... 240, 324 PAODR ....................................... 241, 325 PAPIN......................................... 241, 325 PBDDR ............................................... 248 PBODR ............................................... 249 PBPIN ................................................. 249
Rev. 2.00 Aug. 20, 2008 Page 1195 of 1198 REJ09B0403-0200
PCDDR....................... 254, 259, 338, 343 PCODR............................... 255, 339, 344 PCPIN................................. 255, 339, 344 PCSR .................................................. 365 PDODR............................................... 260 PDPIN................................................. 260 PEDDR ............................... 264, 348, 353 PEODR ....................... 264, 269, 349, 354 PEPIN ......................... 265, 269, 349, 354 PFDDR ............................................... 268 PINFNCR ........................................... 684 PIR...................................................... 767 PSR ..................................................... 770 PTCNT0 ............................................. 358 RBWAR ............................................. 810 RDFAR............................................... 811 RDLAR............................................... 797 RDR.................................................... 435 RFCR.................................................. 773 RFLR .................................................. 769 RMCR................................................. 810 RMFCR .............................................. 806 RSR .................................................... 435 SAR ............................................ 165, 592 SARX ................................................. 593 SBYCR ............................................. 1056 SCIFADR ........................................... 712 SCIFCR .............................................. 526 SCMR ................................................. 446 SCR .................................................... 439 SDBPR ............................................. 1022 SDBSR ............................................. 1022 SDIDR .............................................. 1040 SDIR ................................................. 1021 SERIRQ .............................................. 747 SIRQCR.............................................. 699 SMICCSR........................................... 714 SMICDTR .......................................... 714 SMICFLG........................................... 713 SMICIR .............................................. 715
Rev. 2.00 Aug. 20, 2008 Page 1196 of 1198 REJ09B0403-0200
SMR .................................................... 436 SSCR2................................................. 563 SSCRH................................................ 556 SSCRL ................................................ 558 SSER................................................... 560 SSMR.................................................. 559 SSR ..................................................... 442 SSRDR................................................ 565 SSSR ................................................... 561 SSTDR ................................................ 564 SSTRSR .............................................. 565 STCR .................................................... 66 STR ..................................................... 691 SUBMSTPBH................................... 1062 SUBMSTPBL ................................... 1062 SYSCR.................................................. 65 SYSCR2.............................................. 117 TBRAR ............................................... 811 TCNT .......................................... 396, 417 TCONRS............................................. 405 TCORA............................................... 397 TCORB ............................................... 397 TCR............................................. 381, 398 TCSR .......................... 380, 401, 402, 418 TDFAR ............................................... 811 TDLAR ............................................... 797 TDR .................................................... 435 TFTR................................................... 807 TIER.................................................... 379 TLFRCR ............................................. 773 TOCR.................................................. 382 TPAUSER................... 775, 793, 813, 814 TRG .................................................... 844 TRNTREG .......................................... 858 TROCR ............................................... 770 TRSCER ............................................. 806 TSFRCR.............................................. 772 TSR ..................................................... 435 TWR.................................................... 690 Repeat mode ........................................... 179
Reset ......................................................... 74 Reset exception handling.......................... 74 RXI1 ....................................................... 489 RXI2 ....................................................... 489
T
TAP controller ...................................... 1041 TEI1 ........................................................ 489 TEI2 ........................................................ 489 Trace bit .................................................... 35 Transfer clock ......................................... 566 Transfer rate............................................ 598 Transmit descriptor 0 (TD0) ................... 817 Transmit descriptor 1 (TD1) ................... 819 Transmit descriptor 2 (TD2) ................... 819 Trap instruction exception handling.......... 76 TRAPA instruction ............................. 55, 76 TXI1........................................................ 489 TXI2........................................................ 489
S
Sample-and-hold circuit ......................... 903 Scan mode .............................................. 901 SCIF Control from LPC Interface .......... 749 Serial communication interface (SCI) .... 431 Serial communication interface specification............................................ 986 Serial communication interface with FIFO (SCIF) ................................... 507 Serial data reception ....................... 458, 473 Serial data transmission .................. 456, 470 Serial formats.......................................... 619 Setup stage.............................................. 871 Single mode ............................................ 900 Slave address .......................................... 620 Slave receive operation........................... 634 Slave transmit operation ......................... 642 Sleep mode ........................................... 1066 Smart card............................................... 431 Software protection................................. 982 Software standby mode ........................ 1067 SSU mode............................................... 570 Stack pointer (SP)..................................... 34 Stack status ............................................... 77 Stall operations ....................................... 881 Start condition ........................................ 620 Status stage ............................................. 874 Stop condition......................................... 620 Synchronous serial communication unit (SSU) ............................................... 553
U
USB function module ............................. 831 USB standard commands ........................ 880 User boot MAT ....................................... 984 User boot mode ....................................... 965 User MAT ............................................... 984 User program mode................................. 954
V
Vector number for the software activation interrupt .................................. 167
W
Wait control ............................................ 155 Watchdog timer (WDT) .......................... 415 Watchdog timer mode............................. 422 WOVI ..................................................... 426
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Renesas 16-Bit Single-Chip Microcomputer Hardware Manual H8S/2472, H8S/2463, H8S/2462 Group
Publication Date: Rev.1.00, Mar. 12, 2008 Rev.2.00, Aug. 20, 2008 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp.
2008. Renesas Technology Corp., All rights reserved. Printed in Japan.
Sales Strategic Planning Div.
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RENESAS SALES OFFICES
Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology (Shanghai) Co., Ltd. Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120 Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7858/7898 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2377-3473 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 3518-3399 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 Renesas Technology Korea Co., Ltd. Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145
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